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Latchup [[electronic resource] /] / Steven H. Voldman
Latchup [[electronic resource] /] / Steven H. Voldman
Autore Voldman Steven H
Pubbl/distr/stampa Chichester, West Sussex, England ; ; Hoboken, NJ, : John Wiley, c2007
Descrizione fisica 1 online resource (474 p.)
Disciplina 621.3815/2
621.38152
Soggetto topico Metal oxide semiconductors, Complementary - Defects
Metal oxide semiconductors, Complementary - Reliability
Soggetto genere / forma Electronic books.
ISBN 1-281-31816-7
9786611318161
0-470-51617-8
0-470-51616-X
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Latchup; Contents; About the Author; Preface; Acknowledgements; 1 CMOS Latchup; 1.1 CMOS LATCHUP; 1.1.1 CMOS Latchup-What is Latchup?; 1.1.2 CMOS Latchup-Why is Latchup Still an Issue ?; 1.1.3 Early CMOS Latchup History; 1.2 FUNDAMENTAL CONCEPTS OF LATCHUP DESIGN PRACTICE; 1.3 BUILDING A CMOS LATCHUP STRATEGY; 1.3.1 Building a CMOS Business Strategy - 18 Steps in Building a CMOS Latchup Business Strategy; 1.3.2 Building a CMOS Latchup Technology Strategy - 18 Steps in Building a CMOS Latchup Technology Strategy; 1.4 CMOS LATCHUP TECHNOLOGY MIGRATION STRATEGY
1.5 KEY METRICS OF LATCHUP DESIGN PRACTICE1.6 CMOS LATCHUP TECHNOLOGY TRENDS AND SCALING; 1.7 KEY DEVELOPMENTS; 1.7.1 Key Innovations; 1.7.2 Key Contributions; 1.7.3 Key Patents; 1.8 LATCHUP FAILURE MECHANISMS; 1.9 CMOS LATCHUP EVENTS; 1.9.1 Power-Up Sequence Initiated Latchup; 1.9.2 Input Pin Overshoot and Power-Up Sequence Initiated Latchup; 1.9.3 Input Pin Undershoot and Power-Up Sequence Initiated Latchup; 1.9.4 Multiple Power Supply Power-Up Sequence Initiated Latchup; 1.9.5 Power Supply Overshoot Initiated Latchup; 1.9.6 Power Supply Undershoot Initiated Latchup
1.9.7 Power Supply (Ground Rail) Undershoot Initiated Latchup1.10 ELECTROSTATIC DISCHARGE SOURCES; 1.10.1 Human Body Model ESD Event; 1.10.2 Machine Model ESD Event; 1.10.3 Cable Discharge Event Source; 1.11 SINGLE EVENT LATCHUP; 1.11.1 High-Energy Photon Emissions; 1.11.2 Alpha Particle Ionizing Source; 1.11.3 Cosmic Ray Source; 1.11.4 Heavy Ion Source; 1.12 SUMMARY AND CLOSING COMMENTS; PROBLEMS; REFERENCES; 2 Bipolar Transistors; 2.1 THE BIPOLAR TRANSISTOR AND CMOS LATCHUP; 2.1.1 Fundamental Equations of Semiconductors and the Drift-Diffusion Current Constitutive Relationships
2.1.2 Diode Forward Bias Conditions2.1.3 Diode Forward Bias Conditions and High-level Injection; 2.2 BIPOLAR TRANSISTOR; 2.2.1 Bipolar Current Gain; 2.2.2 Bipolar Collector-to-Emitter Transport Factor; 2.2.3 Bipolar Current Characteristics; 2.2.4 Bipolar Model Gummel Plot; 2.2.5 Bipolar Current Model-Ebers-Moll Model; 2.2.6 Bipolar Transistor Base Defect; 2.2.7 Bipolar Transistor Emitter Defect; 2.2.8 Bipolar Base Current - Base Defect and Emitter Defect Relation to Bipolar Current Gain; 2.3 RECOMBINATION MECHANISMS; 2.3.1 Shockley-Read-Hall (SRH) Generation-Recombination Model
2.3.2 Auger Recombination Model2.3.3 Surface Recombination Mechanisms; 2.3.4 Surface Recombination Velocity; 2.3.5 Recombination Mechanisms and Neutron Irradiation; 2.3.6 Recombination Mechanisms and Gold Recombination Centers; 2.4 PHOTON CURRENTS IN METALLURGICAL JUNCTIONS; 2.5 AVALANCHE BREAKDOWN; 2.5.1 Bipolar Transistor Breakdown; 2.5.2 MOSFET Avalanche Breakdown; 2.6 VERTICAL BIPOLAR TRANSISTOR MODEL; 2.7 LATERAL BIPOLAR TRANSISTOR MODELS; 2.7.1 Lindmayer-Schneider Model; 2.7.2 Bipolar Current Gain with Lateral and Vertical Contributions
2.7.3 Lateral Bipolar Transistor Models - Nonfield-Assisted
Record Nr. UNINA-9910145424903321
Voldman Steven H  
Chichester, West Sussex, England ; ; Hoboken, NJ, : John Wiley, c2007
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Latchup [[electronic resource] /] / Steven H. Voldman
Latchup [[electronic resource] /] / Steven H. Voldman
Autore Voldman Steven H
Pubbl/distr/stampa Chichester, West Sussex, England ; ; Hoboken, NJ, : John Wiley, c2007
Descrizione fisica 1 online resource (474 p.)
Disciplina 621.3815/2
621.38152
Soggetto topico Metal oxide semiconductors, Complementary - Defects
Metal oxide semiconductors, Complementary - Reliability
ISBN 1-281-31816-7
9786611318161
0-470-51617-8
0-470-51616-X
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Latchup; Contents; About the Author; Preface; Acknowledgements; 1 CMOS Latchup; 1.1 CMOS LATCHUP; 1.1.1 CMOS Latchup-What is Latchup?; 1.1.2 CMOS Latchup-Why is Latchup Still an Issue ?; 1.1.3 Early CMOS Latchup History; 1.2 FUNDAMENTAL CONCEPTS OF LATCHUP DESIGN PRACTICE; 1.3 BUILDING A CMOS LATCHUP STRATEGY; 1.3.1 Building a CMOS Business Strategy - 18 Steps in Building a CMOS Latchup Business Strategy; 1.3.2 Building a CMOS Latchup Technology Strategy - 18 Steps in Building a CMOS Latchup Technology Strategy; 1.4 CMOS LATCHUP TECHNOLOGY MIGRATION STRATEGY
1.5 KEY METRICS OF LATCHUP DESIGN PRACTICE1.6 CMOS LATCHUP TECHNOLOGY TRENDS AND SCALING; 1.7 KEY DEVELOPMENTS; 1.7.1 Key Innovations; 1.7.2 Key Contributions; 1.7.3 Key Patents; 1.8 LATCHUP FAILURE MECHANISMS; 1.9 CMOS LATCHUP EVENTS; 1.9.1 Power-Up Sequence Initiated Latchup; 1.9.2 Input Pin Overshoot and Power-Up Sequence Initiated Latchup; 1.9.3 Input Pin Undershoot and Power-Up Sequence Initiated Latchup; 1.9.4 Multiple Power Supply Power-Up Sequence Initiated Latchup; 1.9.5 Power Supply Overshoot Initiated Latchup; 1.9.6 Power Supply Undershoot Initiated Latchup
1.9.7 Power Supply (Ground Rail) Undershoot Initiated Latchup1.10 ELECTROSTATIC DISCHARGE SOURCES; 1.10.1 Human Body Model ESD Event; 1.10.2 Machine Model ESD Event; 1.10.3 Cable Discharge Event Source; 1.11 SINGLE EVENT LATCHUP; 1.11.1 High-Energy Photon Emissions; 1.11.2 Alpha Particle Ionizing Source; 1.11.3 Cosmic Ray Source; 1.11.4 Heavy Ion Source; 1.12 SUMMARY AND CLOSING COMMENTS; PROBLEMS; REFERENCES; 2 Bipolar Transistors; 2.1 THE BIPOLAR TRANSISTOR AND CMOS LATCHUP; 2.1.1 Fundamental Equations of Semiconductors and the Drift-Diffusion Current Constitutive Relationships
2.1.2 Diode Forward Bias Conditions2.1.3 Diode Forward Bias Conditions and High-level Injection; 2.2 BIPOLAR TRANSISTOR; 2.2.1 Bipolar Current Gain; 2.2.2 Bipolar Collector-to-Emitter Transport Factor; 2.2.3 Bipolar Current Characteristics; 2.2.4 Bipolar Model Gummel Plot; 2.2.5 Bipolar Current Model-Ebers-Moll Model; 2.2.6 Bipolar Transistor Base Defect; 2.2.7 Bipolar Transistor Emitter Defect; 2.2.8 Bipolar Base Current - Base Defect and Emitter Defect Relation to Bipolar Current Gain; 2.3 RECOMBINATION MECHANISMS; 2.3.1 Shockley-Read-Hall (SRH) Generation-Recombination Model
2.3.2 Auger Recombination Model2.3.3 Surface Recombination Mechanisms; 2.3.4 Surface Recombination Velocity; 2.3.5 Recombination Mechanisms and Neutron Irradiation; 2.3.6 Recombination Mechanisms and Gold Recombination Centers; 2.4 PHOTON CURRENTS IN METALLURGICAL JUNCTIONS; 2.5 AVALANCHE BREAKDOWN; 2.5.1 Bipolar Transistor Breakdown; 2.5.2 MOSFET Avalanche Breakdown; 2.6 VERTICAL BIPOLAR TRANSISTOR MODEL; 2.7 LATERAL BIPOLAR TRANSISTOR MODELS; 2.7.1 Lindmayer-Schneider Model; 2.7.2 Bipolar Current Gain with Lateral and Vertical Contributions
2.7.3 Lateral Bipolar Transistor Models - Nonfield-Assisted
Record Nr. UNINA-9910830310103321
Voldman Steven H  
Chichester, West Sussex, England ; ; Hoboken, NJ, : John Wiley, c2007
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Latchup / / Steven H. Voldman
Latchup / / Steven H. Voldman
Autore Voldman Steven H
Pubbl/distr/stampa Chichester, West Sussex, England ; ; Hoboken, NJ, : John Wiley, c2007
Descrizione fisica 1 online resource (474 p.)
Disciplina 621.3815/2
Soggetto topico Metal oxide semiconductors, Complementary - Defects
Metal oxide semiconductors, Complementary - Reliability
ISBN 9786611318161
9781281318169
1281318167
9780470516171
0470516178
9780470516164
047051616X
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Latchup; Contents; About the Author; Preface; Acknowledgements; 1 CMOS Latchup; 1.1 CMOS LATCHUP; 1.1.1 CMOS Latchup-What is Latchup?; 1.1.2 CMOS Latchup-Why is Latchup Still an Issue ?; 1.1.3 Early CMOS Latchup History; 1.2 FUNDAMENTAL CONCEPTS OF LATCHUP DESIGN PRACTICE; 1.3 BUILDING A CMOS LATCHUP STRATEGY; 1.3.1 Building a CMOS Business Strategy - 18 Steps in Building a CMOS Latchup Business Strategy; 1.3.2 Building a CMOS Latchup Technology Strategy - 18 Steps in Building a CMOS Latchup Technology Strategy; 1.4 CMOS LATCHUP TECHNOLOGY MIGRATION STRATEGY
1.5 KEY METRICS OF LATCHUP DESIGN PRACTICE1.6 CMOS LATCHUP TECHNOLOGY TRENDS AND SCALING; 1.7 KEY DEVELOPMENTS; 1.7.1 Key Innovations; 1.7.2 Key Contributions; 1.7.3 Key Patents; 1.8 LATCHUP FAILURE MECHANISMS; 1.9 CMOS LATCHUP EVENTS; 1.9.1 Power-Up Sequence Initiated Latchup; 1.9.2 Input Pin Overshoot and Power-Up Sequence Initiated Latchup; 1.9.3 Input Pin Undershoot and Power-Up Sequence Initiated Latchup; 1.9.4 Multiple Power Supply Power-Up Sequence Initiated Latchup; 1.9.5 Power Supply Overshoot Initiated Latchup; 1.9.6 Power Supply Undershoot Initiated Latchup
1.9.7 Power Supply (Ground Rail) Undershoot Initiated Latchup1.10 ELECTROSTATIC DISCHARGE SOURCES; 1.10.1 Human Body Model ESD Event; 1.10.2 Machine Model ESD Event; 1.10.3 Cable Discharge Event Source; 1.11 SINGLE EVENT LATCHUP; 1.11.1 High-Energy Photon Emissions; 1.11.2 Alpha Particle Ionizing Source; 1.11.3 Cosmic Ray Source; 1.11.4 Heavy Ion Source; 1.12 SUMMARY AND CLOSING COMMENTS; PROBLEMS; REFERENCES; 2 Bipolar Transistors; 2.1 THE BIPOLAR TRANSISTOR AND CMOS LATCHUP; 2.1.1 Fundamental Equations of Semiconductors and the Drift-Diffusion Current Constitutive Relationships
2.1.2 Diode Forward Bias Conditions2.1.3 Diode Forward Bias Conditions and High-level Injection; 2.2 BIPOLAR TRANSISTOR; 2.2.1 Bipolar Current Gain; 2.2.2 Bipolar Collector-to-Emitter Transport Factor; 2.2.3 Bipolar Current Characteristics; 2.2.4 Bipolar Model Gummel Plot; 2.2.5 Bipolar Current Model-Ebers-Moll Model; 2.2.6 Bipolar Transistor Base Defect; 2.2.7 Bipolar Transistor Emitter Defect; 2.2.8 Bipolar Base Current - Base Defect and Emitter Defect Relation to Bipolar Current Gain; 2.3 RECOMBINATION MECHANISMS; 2.3.1 Shockley-Read-Hall (SRH) Generation-Recombination Model
2.3.2 Auger Recombination Model2.3.3 Surface Recombination Mechanisms; 2.3.4 Surface Recombination Velocity; 2.3.5 Recombination Mechanisms and Neutron Irradiation; 2.3.6 Recombination Mechanisms and Gold Recombination Centers; 2.4 PHOTON CURRENTS IN METALLURGICAL JUNCTIONS; 2.5 AVALANCHE BREAKDOWN; 2.5.1 Bipolar Transistor Breakdown; 2.5.2 MOSFET Avalanche Breakdown; 2.6 VERTICAL BIPOLAR TRANSISTOR MODEL; 2.7 LATERAL BIPOLAR TRANSISTOR MODELS; 2.7.1 Lindmayer-Schneider Model; 2.7.2 Bipolar Current Gain with Lateral and Vertical Contributions
2.7.3 Lateral Bipolar Transistor Models - Nonfield-Assisted
Record Nr. UNINA-9911019641703321
Voldman Steven H  
Chichester, West Sussex, England ; ; Hoboken, NJ, : John Wiley, c2007
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Reliability wearout mechanisms in advanced CMOS technologies / / Alvin W. Strong ... [et al.]
Reliability wearout mechanisms in advanced CMOS technologies / / Alvin W. Strong ... [et al.]
Pubbl/distr/stampa Piscataway, New Jersey : , : IEEE Press, , c2009
Descrizione fisica 1 online resource (642 p.)
Disciplina 621.39732
Altri autori (Persone) StrongAlvin Wayne <1946->
Collana IEEE Press series on microelectronic systems
Soggetto topico Metal oxide semiconductors, Complementary - Reliability
Microelectronics
ISBN 1-282-33149-3
9786612331497
0-470-45526-8
0-470-45525-X
Classificazione ELT 358f
ZN 4960
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction / Alvin W. Strong -- Dielectric characterization and reliability methodology / Ernest Y. Wu, Rolf-Peter Vollertsen, and Jordi Suñé -- Dielectric breakdown of gate oxides: physics and experiments / Ernest Y. Wu, Rolf-Peter Vollertsen, and Jordi Suñé -- Negative bias temperature instabilities in pMOSFET devices / Giuseppe LaRosa -- Hot carriers / Stewart E. Rauch, III -- Stress-induced voiding / Timothy D. Sullivan -- Electromigration / Timothy D. Sullivan.
Record Nr. UNINA-9910139868803321
Piscataway, New Jersey : , : IEEE Press, , c2009
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Reliability wearout mechanisms in advanced CMOS technologies / / Alvin W. Strong ... [et al.]
Reliability wearout mechanisms in advanced CMOS technologies / / Alvin W. Strong ... [et al.]
Pubbl/distr/stampa Piscataway, New Jersey : , : IEEE Press, , c2009
Descrizione fisica 1 online resource (642 p.)
Disciplina 621.39732
Altri autori (Persone) StrongAlvin Wayne <1946->
Collana IEEE Press series on microelectronic systems
Soggetto topico Metal oxide semiconductors, Complementary - Reliability
Microelectronics
ISBN 1-282-33149-3
9786612331497
0-470-45526-8
0-470-45525-X
Classificazione ELT 358f
ZN 4960
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction / Alvin W. Strong -- Dielectric characterization and reliability methodology / Ernest Y. Wu, Rolf-Peter Vollertsen, and Jordi Suñé -- Dielectric breakdown of gate oxides: physics and experiments / Ernest Y. Wu, Rolf-Peter Vollertsen, and Jordi Suñé -- Negative bias temperature instabilities in pMOSFET devices / Giuseppe LaRosa -- Hot carriers / Stewart E. Rauch, III -- Stress-induced voiding / Timothy D. Sullivan -- Electromigration / Timothy D. Sullivan.
Record Nr. UNISA-996204768303316
Piscataway, New Jersey : , : IEEE Press, , c2009
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Reliability wearout mechanisms in advanced CMOS technologies / / Alvin W. Strong ... [et al.]
Reliability wearout mechanisms in advanced CMOS technologies / / Alvin W. Strong ... [et al.]
Pubbl/distr/stampa Piscataway, New Jersey : , : IEEE Press, , c2009
Descrizione fisica 1 online resource (642 p.)
Disciplina 621.39732
Altri autori (Persone) StrongAlvin Wayne <1946->
Collana IEEE Press series on microelectronic systems
Soggetto topico Metal oxide semiconductors, Complementary - Reliability
Microelectronics
ISBN 1-282-33149-3
9786612331497
0-470-45526-8
0-470-45525-X
Classificazione ELT 358f
ZN 4960
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction / Alvin W. Strong -- Dielectric characterization and reliability methodology / Ernest Y. Wu, Rolf-Peter Vollertsen, and Jordi Suñé -- Dielectric breakdown of gate oxides: physics and experiments / Ernest Y. Wu, Rolf-Peter Vollertsen, and Jordi Suñé -- Negative bias temperature instabilities in pMOSFET devices / Giuseppe LaRosa -- Hot carriers / Stewart E. Rauch, III -- Stress-induced voiding / Timothy D. Sullivan -- Electromigration / Timothy D. Sullivan.
Record Nr. UNINA-9910830485603321
Piscataway, New Jersey : , : IEEE Press, , c2009
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Reliability wearout mechanisms in advanced CMOS technologies / / Alvin W. Strong ... [et al.]
Reliability wearout mechanisms in advanced CMOS technologies / / Alvin W. Strong ... [et al.]
Pubbl/distr/stampa Hoboken, N.J., : Wiley, c2009
Descrizione fisica 1 online resource (642 p.)
Disciplina 621.39732
Altri autori (Persone) StrongAlvin Wayne <1946->
Collana IEEE Press series on microelectronic systems
Soggetto topico Metal oxide semiconductors, Complementary - Reliability
Microelectronics
ISBN 9786612331497
9781282331495
1282331493
9780470455265
0470455268
9780470455258
047045525X
Classificazione ELT 358f
ZN 4960
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction / Alvin W. Strong -- Dielectric characterization and reliability methodology / Ernest Y. Wu, Rolf-Peter Vollertsen, and Jordi Suñé -- Dielectric breakdown of gate oxides: physics and experiments / Ernest Y. Wu, Rolf-Peter Vollertsen, and Jordi Suñé -- Negative bias temperature instabilities in pMOSFET devices / Giuseppe LaRosa -- Hot carriers / Stewart E. Rauch, III -- Stress-induced voiding / Timothy D. Sullivan -- Electromigration / Timothy D. Sullivan.
Record Nr. UNINA-9911019652603321
Hoboken, N.J., : Wiley, c2009
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Transient-induced latchup in CMOS integrated circuits / / Ming-Dou Ker and Sheng-Fu Hsu
Transient-induced latchup in CMOS integrated circuits / / Ming-Dou Ker and Sheng-Fu Hsu
Autore Ker Ming-Dou
Pubbl/distr/stampa Singapore ; , : Wiley, , c2009
Descrizione fisica 1 online resource (265 p.)
Disciplina 621.3815
621.39/5
Altri autori (Persone) HsuSheng-Fu
Soggetto topico Metal oxide semiconductors, Complementary - Defects
Metal oxide semiconductors, Complementary - Reliability
ISBN 1-282-38218-7
9786612382185
0-470-82409-3
0-470-82408-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Physical Mechanism of TLU under the System-Level ESD Test -- Component-Level Measurement for TLU under System-Level ESD Considerations -- TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits -- TLU in CMOS ICs in the Electrical Fast Transient Test -- Methodology on Extracting Compact Layout Rules for Latchup Prevention -- Special Layout Issues for Latchup Prevention -- TLU Prevention in Power-Rail ESD Clamp Circuits -- Appendix A: Practical Application Extractions of Latchup Design Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOS Process.
Record Nr. UNINA-9910139930203321
Ker Ming-Dou  
Singapore ; , : Wiley, , c2009
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Transient-induced latchup in CMOS integrated circuits / / Ming-Dou Ker and Sheng-Fu Hsu
Transient-induced latchup in CMOS integrated circuits / / Ming-Dou Ker and Sheng-Fu Hsu
Autore Ker Ming-Dou
Edizione [1st ed.]
Pubbl/distr/stampa Singapore ; ; Hoboken, NJ, : Wiley, c2009
Descrizione fisica 1 online resource (265 p.)
Disciplina 621.3815
621.39/5
Altri autori (Persone) HsuSheng-Fu
Soggetto topico Metal oxide semiconductors, Complementary - Defects
Metal oxide semiconductors, Complementary - Reliability
ISBN 9786612382185
9781282382183
1282382187
9780470824092
0470824093
9780470824085
0470824085
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Physical Mechanism of TLU under the System-Level ESD Test -- Component-Level Measurement for TLU under System-Level ESD Considerations -- TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits -- TLU in CMOS ICs in the Electrical Fast Transient Test -- Methodology on Extracting Compact Layout Rules for Latchup Prevention -- Special Layout Issues for Latchup Prevention -- TLU Prevention in Power-Rail ESD Clamp Circuits -- Appendix A: Practical Application Extractions of Latchup Design Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOS Process.
Record Nr. UNINA-9910808037403321
Ker Ming-Dou  
Singapore ; ; Hoboken, NJ, : Wiley, c2009
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui