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2006 International Workshop on Nano CMOS : proceedings : Jan. 30, 31, Feb. 1, 2006, TORAY Sougou Kensyu Center, 21-9 Suehiro, Mishima, Shizuoka, 411-0032 Japan
| 2006 International Workshop on Nano CMOS : proceedings : Jan. 30, 31, Feb. 1, 2006, TORAY Sougou Kensyu Center, 21-9 Suehiro, Mishima, Shizuoka, 411-0032 Japan |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Electron Devices Society, 2006 |
| Disciplina | 621.39/5 |
| Soggetto topico |
Metal oxide semiconductors, Complementary - Design and construction
Nanoelectronics Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN | 1-5090-9617-5 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996207159703316 |
| [Place of publication not identified], : IEEE Electron Devices Society, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2006 International Workshop on Nano CMOS : proceedings : Jan. 30, 31, Feb. 1, 2006, TORAY Sougou Kensyu Center, 21-9 Suehiro, Mishima, Shizuoka, 411-0032 Japan
| 2006 International Workshop on Nano CMOS : proceedings : Jan. 30, 31, Feb. 1, 2006, TORAY Sougou Kensyu Center, 21-9 Suehiro, Mishima, Shizuoka, 411-0032 Japan |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Electron Devices Society, 2006 |
| Disciplina | 621.39/5 |
| Soggetto topico |
Metal oxide semiconductors, Complementary - Design and construction
Nanoelectronics Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN | 1-5090-9617-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910145691203321 |
| [Place of publication not identified], : IEEE Electron Devices Society, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
All-digital frequency synthesizer in deep-submicron CMOS [[electronic resource] /] / Robert Bogdan Staszewski, Poras T. Balasara
| All-digital frequency synthesizer in deep-submicron CMOS [[electronic resource] /] / Robert Bogdan Staszewski, Poras T. Balasara |
| Autore | Staszewski Robert Bogdan <1965-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley-Interscience, c2006 |
| Descrizione fisica | 1 online resource (281 p.) |
| Disciplina |
621.3815363
621.3815486 |
| Altri autori (Persone) | BalsaraPoras T. <1961-> |
| Soggetto topico |
Frequency synthesizers - Design and construction
Wireless communication systems - Equipment and supplies - Design and construction Metal oxide semiconductors, Complementary - Design and construction |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-65439-2
9786610654390 0-470-04195-1 0-470-04194-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS; CONTENTS; PREFACE; Acknowledgments; 1 INTRODUCTION; 1.1 Frequency Synthesis; 1.1.1 Noise in Oscillators; 1.1.2 Frequency Synthesis Techniques; 1.2 Frequency Synthesizer as an Integral Part of an RF Transceiver; 1.2.1 Transmitter; 1.2.2 Receiver; 1.2.3 Toward Direct Transmitter Modulation; 1.3 Frequency Synthesizers for Mobile Communications; 1.3.1 Integer-N PLL Architecture; 1.3.2 Fractional-N PLL Architecture; 1.3.3 Toward an All-Digital PLL Approach; 1.4 Implementation of an RF Synthesizer
1.4.1 CMOS vs. Traditional RF Process Technologies1.4.2 Deep-Submicron CMOS; 1.4.3 Digitally Intensive Approach; 1.4.4 System Integration; 1.4.5 System Integration Challenges for Deep-Submicron CMOS; 2 DIGITALLY CONTROLLED OSCILLATOR; 2.1 Varactor in a Deep-Submicron CMOS Process; 2.2 Fully Digital Control of Oscillating Frequency; 2.3 LC Tank; 2.4 Oscillator Core; 2.5 Open-Loop Narrowband Digital-to-Frequency Conversion; 2.6 Example Implementation; 2.7 Time-Domain Mathematical Model of a DCO; 2.8 Summary; 3 NORMALIZED DCO; 3.1 Oscillator Transfer Function and Gain; 3.2 DCO Gain Estimation 3.3 DCO Gain Normalization3.4 Principle of Synchronously Optimal DCO Tuning Word Retiming; 3.5 Time Dithering of DCO Tuning Input; 3.5.1 Oscillator Tune Time Dithering Principle; 3.5.2 Direct Time Dithering of Tuning Input; 3.5.3 Update Clock Dithering Scheme; 3.6 Implementation of PVT and Acquisition DCO Bits; 3.7 Implementation of Tracking DCO Bits; 3.7.1 High-Speed Dithering of Fractional Varactors; 3.7.2 Dynamic Element Matching of Varactors; 3.7.3 DCO Varactor Rearrangement; 3.8 Time-Domain Model; 3.9 Summary; 4 ALL-DIGITAL PHASE-LOCKED LOOP; 4.1 Phase-Domain Operation 4.2 Reference Clock Retiming4.3 Phase Detection; 4.3.1 Difference Mode of ADPLL Operation; 4.3.2 Integer-Domain Operation; 4.4 Modulo Arithmetic of the Reference and Variable Phases; 4.4.1 Variable-Phase Accumulator (PV Block); 4.5 Time-to-Digital Converter; 4.5.1 Frequency Reference Edge Estimation; 4.6 Fractional Error Estimator; 4.6.1 Fractional-Division Ratio Compensation; 4.6.2 TDC Resolution Effect on Estimated Frequency Resolution; 4.6.3 Active Removal of Fractional Spurs Through TDC (Optional); 4.7 Frequency Reference Retiming by a DCO Clock; 4.7.1 Sense Amplifier-Based Flip-Flop 4.7.2 General Idea of Clock Retiming4.7.3 Implementation; 4.7.4 Time-Deferred Calculation of the Variable Phase (Optional); 4.8 Loop Gain Factor; 4.8.1 Phase-Error Dynamic Range; 4.9 Phase-Domain ADPLL Architecture; 4.9.1 Close-in Spurs Due to Injection Pulling; 4.10 PLL Frequency Response; 4.10.1 Conversion Between the s- and z-Domains; 4.11 Noise and Error Sources; 4.11.1 TDC Resolution Effect on Phase Noise; 4.11.2 Phase Noise Due to DCO ΣΔ Dithering; 4.12 Type II ADPLL; 4.12.1 PLL Frequency Response of a Type II Loop; 4.13 Higher-Order ADPLL; 4.13.1 PLL Stability Analysis 4.14 Nonlinear Differential Term of an ADPLL |
| Record Nr. | UNINA-9910143413503321 |
Staszewski Robert Bogdan <1965->
|
||
| Hoboken, N.J., : Wiley-Interscience, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
All-digital frequency synthesizer in deep-submicron CMOS [[electronic resource] /] / Robert Bogdan Staszewski, Poras T. Balasara
| All-digital frequency synthesizer in deep-submicron CMOS [[electronic resource] /] / Robert Bogdan Staszewski, Poras T. Balasara |
| Autore | Staszewski Robert Bogdan <1965-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley-Interscience, c2006 |
| Descrizione fisica | 1 online resource (281 p.) |
| Disciplina |
621.3815363
621.3815486 |
| Altri autori (Persone) | BalsaraPoras T. <1961-> |
| Soggetto topico |
Frequency synthesizers - Design and construction
Wireless communication systems - Equipment and supplies - Design and construction Metal oxide semiconductors, Complementary - Design and construction |
| ISBN |
1-280-65439-2
9786610654390 0-470-04195-1 0-470-04194-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS; CONTENTS; PREFACE; Acknowledgments; 1 INTRODUCTION; 1.1 Frequency Synthesis; 1.1.1 Noise in Oscillators; 1.1.2 Frequency Synthesis Techniques; 1.2 Frequency Synthesizer as an Integral Part of an RF Transceiver; 1.2.1 Transmitter; 1.2.2 Receiver; 1.2.3 Toward Direct Transmitter Modulation; 1.3 Frequency Synthesizers for Mobile Communications; 1.3.1 Integer-N PLL Architecture; 1.3.2 Fractional-N PLL Architecture; 1.3.3 Toward an All-Digital PLL Approach; 1.4 Implementation of an RF Synthesizer
1.4.1 CMOS vs. Traditional RF Process Technologies1.4.2 Deep-Submicron CMOS; 1.4.3 Digitally Intensive Approach; 1.4.4 System Integration; 1.4.5 System Integration Challenges for Deep-Submicron CMOS; 2 DIGITALLY CONTROLLED OSCILLATOR; 2.1 Varactor in a Deep-Submicron CMOS Process; 2.2 Fully Digital Control of Oscillating Frequency; 2.3 LC Tank; 2.4 Oscillator Core; 2.5 Open-Loop Narrowband Digital-to-Frequency Conversion; 2.6 Example Implementation; 2.7 Time-Domain Mathematical Model of a DCO; 2.8 Summary; 3 NORMALIZED DCO; 3.1 Oscillator Transfer Function and Gain; 3.2 DCO Gain Estimation 3.3 DCO Gain Normalization3.4 Principle of Synchronously Optimal DCO Tuning Word Retiming; 3.5 Time Dithering of DCO Tuning Input; 3.5.1 Oscillator Tune Time Dithering Principle; 3.5.2 Direct Time Dithering of Tuning Input; 3.5.3 Update Clock Dithering Scheme; 3.6 Implementation of PVT and Acquisition DCO Bits; 3.7 Implementation of Tracking DCO Bits; 3.7.1 High-Speed Dithering of Fractional Varactors; 3.7.2 Dynamic Element Matching of Varactors; 3.7.3 DCO Varactor Rearrangement; 3.8 Time-Domain Model; 3.9 Summary; 4 ALL-DIGITAL PHASE-LOCKED LOOP; 4.1 Phase-Domain Operation 4.2 Reference Clock Retiming4.3 Phase Detection; 4.3.1 Difference Mode of ADPLL Operation; 4.3.2 Integer-Domain Operation; 4.4 Modulo Arithmetic of the Reference and Variable Phases; 4.4.1 Variable-Phase Accumulator (PV Block); 4.5 Time-to-Digital Converter; 4.5.1 Frequency Reference Edge Estimation; 4.6 Fractional Error Estimator; 4.6.1 Fractional-Division Ratio Compensation; 4.6.2 TDC Resolution Effect on Estimated Frequency Resolution; 4.6.3 Active Removal of Fractional Spurs Through TDC (Optional); 4.7 Frequency Reference Retiming by a DCO Clock; 4.7.1 Sense Amplifier-Based Flip-Flop 4.7.2 General Idea of Clock Retiming4.7.3 Implementation; 4.7.4 Time-Deferred Calculation of the Variable Phase (Optional); 4.8 Loop Gain Factor; 4.8.1 Phase-Error Dynamic Range; 4.9 Phase-Domain ADPLL Architecture; 4.9.1 Close-in Spurs Due to Injection Pulling; 4.10 PLL Frequency Response; 4.10.1 Conversion Between the s- and z-Domains; 4.11 Noise and Error Sources; 4.11.1 TDC Resolution Effect on Phase Noise; 4.11.2 Phase Noise Due to DCO ΣΔ Dithering; 4.12 Type II ADPLL; 4.12.1 PLL Frequency Response of a Type II Loop; 4.13 Higher-Order ADPLL; 4.13.1 PLL Stability Analysis 4.14 Nonlinear Differential Term of an ADPLL |
| Record Nr. | UNINA-9910830214603321 |
|
Staszewski Robert Bogdan <1965->
|
||
| Hoboken, N.J., : Wiley-Interscience, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
All-digital frequency synthesizer in deep-submicron CMOS [[electronic resource] /] / Robert Bogdan Staszewski, Poras T. Balasara
| All-digital frequency synthesizer in deep-submicron CMOS [[electronic resource] /] / Robert Bogdan Staszewski, Poras T. Balasara |
| Autore | Staszewski Robert Bogdan <1965-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley-Interscience, c2006 |
| Descrizione fisica | 1 online resource (281 p.) |
| Disciplina |
621.3815363
621.3815486 |
| Altri autori (Persone) | BalsaraPoras T. <1961-> |
| Soggetto topico |
Frequency synthesizers - Design and construction
Wireless communication systems - Equipment and supplies - Design and construction Metal oxide semiconductors, Complementary - Design and construction |
| ISBN |
1-280-65439-2
9786610654390 0-470-04195-1 0-470-04194-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS; CONTENTS; PREFACE; Acknowledgments; 1 INTRODUCTION; 1.1 Frequency Synthesis; 1.1.1 Noise in Oscillators; 1.1.2 Frequency Synthesis Techniques; 1.2 Frequency Synthesizer as an Integral Part of an RF Transceiver; 1.2.1 Transmitter; 1.2.2 Receiver; 1.2.3 Toward Direct Transmitter Modulation; 1.3 Frequency Synthesizers for Mobile Communications; 1.3.1 Integer-N PLL Architecture; 1.3.2 Fractional-N PLL Architecture; 1.3.3 Toward an All-Digital PLL Approach; 1.4 Implementation of an RF Synthesizer
1.4.1 CMOS vs. Traditional RF Process Technologies1.4.2 Deep-Submicron CMOS; 1.4.3 Digitally Intensive Approach; 1.4.4 System Integration; 1.4.5 System Integration Challenges for Deep-Submicron CMOS; 2 DIGITALLY CONTROLLED OSCILLATOR; 2.1 Varactor in a Deep-Submicron CMOS Process; 2.2 Fully Digital Control of Oscillating Frequency; 2.3 LC Tank; 2.4 Oscillator Core; 2.5 Open-Loop Narrowband Digital-to-Frequency Conversion; 2.6 Example Implementation; 2.7 Time-Domain Mathematical Model of a DCO; 2.8 Summary; 3 NORMALIZED DCO; 3.1 Oscillator Transfer Function and Gain; 3.2 DCO Gain Estimation 3.3 DCO Gain Normalization3.4 Principle of Synchronously Optimal DCO Tuning Word Retiming; 3.5 Time Dithering of DCO Tuning Input; 3.5.1 Oscillator Tune Time Dithering Principle; 3.5.2 Direct Time Dithering of Tuning Input; 3.5.3 Update Clock Dithering Scheme; 3.6 Implementation of PVT and Acquisition DCO Bits; 3.7 Implementation of Tracking DCO Bits; 3.7.1 High-Speed Dithering of Fractional Varactors; 3.7.2 Dynamic Element Matching of Varactors; 3.7.3 DCO Varactor Rearrangement; 3.8 Time-Domain Model; 3.9 Summary; 4 ALL-DIGITAL PHASE-LOCKED LOOP; 4.1 Phase-Domain Operation 4.2 Reference Clock Retiming4.3 Phase Detection; 4.3.1 Difference Mode of ADPLL Operation; 4.3.2 Integer-Domain Operation; 4.4 Modulo Arithmetic of the Reference and Variable Phases; 4.4.1 Variable-Phase Accumulator (PV Block); 4.5 Time-to-Digital Converter; 4.5.1 Frequency Reference Edge Estimation; 4.6 Fractional Error Estimator; 4.6.1 Fractional-Division Ratio Compensation; 4.6.2 TDC Resolution Effect on Estimated Frequency Resolution; 4.6.3 Active Removal of Fractional Spurs Through TDC (Optional); 4.7 Frequency Reference Retiming by a DCO Clock; 4.7.1 Sense Amplifier-Based Flip-Flop 4.7.2 General Idea of Clock Retiming4.7.3 Implementation; 4.7.4 Time-Deferred Calculation of the Variable Phase (Optional); 4.8 Loop Gain Factor; 4.8.1 Phase-Error Dynamic Range; 4.9 Phase-Domain ADPLL Architecture; 4.9.1 Close-in Spurs Due to Injection Pulling; 4.10 PLL Frequency Response; 4.10.1 Conversion Between the s- and z-Domains; 4.11 Noise and Error Sources; 4.11.1 TDC Resolution Effect on Phase Noise; 4.11.2 Phase Noise Due to DCO ΣΔ Dithering; 4.12 Type II ADPLL; 4.12.1 PLL Frequency Response of a Type II Loop; 4.13 Higher-Order ADPLL; 4.13.1 PLL Stability Analysis 4.14 Nonlinear Differential Term of an ADPLL |
| Record Nr. | UNINA-9910841612103321 |
|
Staszewski Robert Bogdan <1965->
|
||
| Hoboken, N.J., : Wiley-Interscience, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
CMOS : circuit design, layout, and simulation / / R. Jacob Baker
| CMOS : circuit design, layout, and simulation / / R. Jacob Baker |
| Autore | Baker R. Jacob <1964-> |
| Edizione | [Third edition] |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley & Sons, Inc., [2010] |
| Descrizione fisica | 1 online resource (1214 pages) |
| Disciplina |
621.3815
621.39/732 |
| Collana | IEEE Press series on microelectronic systems |
| Soggetto topico |
Metal oxide semiconductors, Complementary - Design and construction
Integrated circuits - Design and construction Metal oxide semiconductor field-effect transistors Metall-òxid-semiconductors complementaris - Disseny i construcció Circuits integrats Transistors MOSFET |
| ISBN |
9780470891179
1-118-03823-1 1-283-37262-2 9786613372628 0-470-89117-3 0-470-89116-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
CMOS Circuit Design, Layout, and Simulation; Contents; Preface; Chapter 1 Introduction to CMOS Design; Chapter 2 The Well; Chapter 3 The Metal Layers; Chapter 4 The Active and Poly Layers; Chapter 5 Resistors, Capacitors, MOSFETs; Chapter 6 MOSFET Operation; Chapter 7 CMOS Fabrication; Chapter 8 Electrical Noise: An Overview; Chapter 9 Models for Analog Design; Chapter 10 Models for Digital Design; Chapter 11 The Inverter; Chapter 12 Static Logic Gates; Chapter 13 Clocked Circuits; Chapter 14 Dynamic Logic Gates; Chapter 15 VLSI Layout Examples; Chapter 16 Memory Circuits
Chapter 17 Sensing Using ?S ModulationChapter 18 Special Purpose CMOS Circuits; Chapter 19 Digital Phase-Locked Loops; Chapter 20 Current Mirrors; Chapter 21 Amplifiers; Chapter 22 Differential Amplifiers; Chapter 23 Voltage References; Chapter 24 Operational Amplifiers I; Chapter 25 Dynamic Analog Circuits; Chapter 26 Operational Amplifiers II; Chapter 27 Nonlinear Analog Circuits; Chapter 28 Data Converter Fundamentals; Chapter 29 Data Converter Architectures; Chapter 30 Implementing Data Converters; Chapter 31 Feedback Amplifiers; Index; About the Author |
| Record Nr. | UNINA-9910140906703321 |
|
Baker R. Jacob <1964->
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| Hoboken, NJ, : John Wiley & Sons, Inc., [2010] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
CMOS analog integrated circuits : high-speed and power-efficient design / / Tertulien Ndjountche
| CMOS analog integrated circuits : high-speed and power-efficient design / / Tertulien Ndjountche |
| Autore | Ndjountche Tertulien |
| Pubbl/distr/stampa | Boca Raton, Fla. : , : CRC Press, , 2011 |
| Descrizione fisica | 1 online resource (914 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Linear integrated circuits - Design and construction
Metal oxide semiconductors, Complementary - Design and construction |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-315-21729-5
1-4398-5500-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Contents; Preface; List of Figures; List of Tables; 1. Mixed-Signal Integrated Systems: Limitations and Challenges; 2. MOS Transistors; Bibliography; 3. Physical Design of MOS Integrated Circuits; Bibliography; 4. Bias and Current Reference Circuits; Bibliography; 5. CMOS Amplifiers; Bibliography; 6. Nonlinear Analog Components; Bibliography; 7. Continuous-Time Circuits; Bibliography; 8. Switched-Capacitor Circuits; Bibliography; 9. Data Converter Principles; Bibliography; 10. Nyquist Digital-to-Analog Converters; Bibliography; 11. Nyquist Analog-to-Digital Converters
Bibliography12. Delta-Sigma Data Converters; Bibliography; 13. Circuits for Clock Signal Generation and Synchronization; Bibliography; Appendix A: Logic Building Blocks; Appendix B: Transistor sizing in building blocks; Appendix C: Signal-Flow Graph |
| Record Nr. | UNINA-9910464667303321 |
|
Ndjountche Tertulien
|
||
| Boca Raton, Fla. : , : CRC Press, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
CMOS analog integrated circuits : high-speed and power-efficient design / / Tertulien Ndjountche
| CMOS analog integrated circuits : high-speed and power-efficient design / / Tertulien Ndjountche |
| Autore | Ndjountche Tertulien |
| Pubbl/distr/stampa | Boca Raton, Fla. : , : CRC Press, , 2011 |
| Descrizione fisica | 1 online resource (914 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Linear integrated circuits - Design and construction
Metal oxide semiconductors, Complementary - Design and construction |
| ISBN |
1-351-83318-9
1-315-21729-5 1-4398-5500-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Contents; Preface; List of Figures; List of Tables; 1. Mixed-Signal Integrated Systems: Limitations and Challenges; 2. MOS Transistors; Bibliography; 3. Physical Design of MOS Integrated Circuits; Bibliography; 4. Bias and Current Reference Circuits; Bibliography; 5. CMOS Amplifiers; Bibliography; 6. Nonlinear Analog Components; Bibliography; 7. Continuous-Time Circuits; Bibliography; 8. Switched-Capacitor Circuits; Bibliography; 9. Data Converter Principles; Bibliography; 10. Nyquist Digital-to-Analog Converters; Bibliography; 11. Nyquist Analog-to-Digital Converters
Bibliography12. Delta-Sigma Data Converters; Bibliography; 13. Circuits for Clock Signal Generation and Synchronization; Bibliography; Appendix A: Logic Building Blocks; Appendix B: Transistor sizing in building blocks; Appendix C: Signal-Flow Graph |
| Record Nr. | UNINA-9910789488603321 |
|
Ndjountche Tertulien
|
||
| Boca Raton, Fla. : , : CRC Press, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
CMOS analog integrated circuits : high-speed and power-efficient design / / Tertulien Ndjountche
| CMOS analog integrated circuits : high-speed and power-efficient design / / Tertulien Ndjountche |
| Autore | Ndjountche Tertulien |
| Pubbl/distr/stampa | Boca Raton, Fla. : , : CRC Press, , 2011 |
| Descrizione fisica | 1 online resource (914 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Linear integrated circuits - Design and construction
Metal oxide semiconductors, Complementary - Design and construction |
| ISBN |
1-351-83318-9
1-315-21729-5 1-4398-5500-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Contents; Preface; List of Figures; List of Tables; 1. Mixed-Signal Integrated Systems: Limitations and Challenges; 2. MOS Transistors; Bibliography; 3. Physical Design of MOS Integrated Circuits; Bibliography; 4. Bias and Current Reference Circuits; Bibliography; 5. CMOS Amplifiers; Bibliography; 6. Nonlinear Analog Components; Bibliography; 7. Continuous-Time Circuits; Bibliography; 8. Switched-Capacitor Circuits; Bibliography; 9. Data Converter Principles; Bibliography; 10. Nyquist Digital-to-Analog Converters; Bibliography; 11. Nyquist Analog-to-Digital Converters
Bibliography12. Delta-Sigma Data Converters; Bibliography; 13. Circuits for Clock Signal Generation and Synchronization; Bibliography; Appendix A: Logic Building Blocks; Appendix B: Transistor sizing in building blocks; Appendix C: Signal-Flow Graph |
| Record Nr. | UNINA-9910819795103321 |
|
Ndjountche Tertulien
|
||
| Boca Raton, Fla. : , : CRC Press, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
CMOS circuit design for RF sensors
| CMOS circuit design for RF sensors |
| Autore | Gudnason Gunnar |
| Pubbl/distr/stampa | Boston, MA : , : Springer US, , 2002 |
| Descrizione fisica | 1 online resource (VII, 176 p.) |
| Disciplina | 621.39/732 |
| Collana | The Kluwer international series in engineering and computer science CMOS circuit design for RF sensors |
| Soggetto topico |
Detectors - Design and construction
Electronic circuit design - Power supply Metal oxide semiconductors, Complementary - Design and construction Very high speed integrated circuits Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
1-280-20015-4
9786610200153 0-306-47528-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Link Design -- Receivers -- Power Supply Management -- Reference Circuits -- Case Studies. |
| Record Nr. | UNINA-9910450618803321 |
|
Gudnason Gunnar
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| Boston, MA : , : Springer US, , 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
