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Advanced Nanoscale MOSFET Architectures : Current Trends and Future Perspectives
| Advanced Nanoscale MOSFET Architectures : Current Trends and Future Perspectives |
| Autore | Biswas Kalyan |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Newark : , : John Wiley & Sons, Incorporated, , 2024 |
| Descrizione fisica | 1 online resource (339 pages) |
| Disciplina | 621.3815/284 |
| Altri autori (Persone) | SarkarAngsuman |
| Soggetto topico |
Metal oxide semiconductor field-effect transistors
Nanotechnology |
| ISBN |
9781394188956
1394188951 9781394188970 1394188978 9781394188987 1394188986 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover -- Title Page -- Copyright -- Contents -- About the Editors -- List of Contributors -- Preface -- Acknowledgments -- Chapter 1 Emerging MOSFET Technologies -- 1.1 Introduction: Transistor Action -- 1.2 MOSFET Scaling -- 1.3 Challenges in Scaling the MOSFET -- 1.4 Emerging MOSFET Architectures -- 1.4.1 Tunnel FET -- 1.4.2 Nanowire FET -- 1.4.3 Nanosheet FET -- 1.4.4 Negative Capacitance FET -- 1.4.5 Graphene FET -- 1.4.6 III-V Material‐based MOSFETS -- 1.4.7 HEMT -- 1.4.8 Strain Engineered MOSFETs -- 1.5 Organization of this Book -- References -- Chapter 2 MOSFET: Device Physics and Operation -- 2.1 Introduction to MOSFET -- 2.2 Advantages of MOSFET -- 2.3 Applications of MOSFETs -- 2.4 Types of MOSFETs -- 2.4.1 P‐Channel and N‐Channel MOSFET -- 2.4.2 MOSFET Working Operation -- 2.5 Band Diagram of MOSFET -- 2.5.1 Accumulation Layer -- 2.5.2 Depletion Layer -- 2.5.3 Inversion Layer -- 2.6 MOSFET Regions of Operation -- 2.6.1 N‐Channel Depletion MOSFET -- 2.6.2 P‐Channel depletion MOSFET -- 2.6.3 Operating Regions of P‐Channel Depletion MOSFET -- 2.6.4 Enhancement MOSFET -- 2.6.5 N‐Channel Enhancement MOSFET -- 2.6.6 P‐Channel Enhancement MOSFET -- 2.7 Scaling of MOSFET -- 2.7.1 Types of Scaling -- 2.8 Short‐channel Effects -- 2.8.1 Drain‐induced Barrier Lowering -- 2.8.2 Gate‐induced Drain Leakage -- 2.9 Body Bias Effect -- 2.9.1 Salient Feature of Body Bias -- 2.9.2 Significance of Body Bias -- 2.9.3 Body Bias Verification -- 2.10 Advancement of MOSFET Structures -- References -- Chapter 3 High‐κ Dielectrics in Next Generation VLSI/Mixed Signal Circuits -- 3.1 Introduction to Gate Dielectrics -- 3.2 High‐κ Dielectrics in Metal-Oxide-Semiconductor Capacitors -- 3.3 High‐κ Dielectrics in Metal Insulator Metal (MIM) Capacitors -- 3.3.1 High‐κ Dielectrics for Mixed Signal Circuits.
3.3.2 High‐κ Dielectrics as Stacks for Resistive Random Access Memories -- 3.4 MOSFETs Scaling and the Need of High‐κ -- 3.5 High‐κ Dielectrics in Next Generation Transistors -- 3.5.1 Planar-Nano Scale Field Effect Transistor -- 3.5.2 Silicon on Insulator -- 3.5.3 FIN Field Effect Transistor -- 3.5.4 Tunnel Field Effect Transistor -- 3.5.5 Negative Capacitance Field Effect Transistor -- References -- Chapter 4 Consequential Effects of Trap Charges on Dielectric Defects for MU‐G FET -- 4.1 Introduction -- 4.2 TID Effects Overview -- 4.3 Application Area of Device for TID Effect Analysis -- 4.4 Near the Earth: Trapped Radiation -- 4.5 Ionizing Radiation Effect in Silicon Dioxide (SiO2) -- 4.6 TID Effects in CMOS -- 4.7 TID Effects in Bipolar Devices -- 4.8 Understanding and Modeling a‐SiO2 Physics -- 4.9 Hydrogen (H2) Reaction with Trapped Charges at Insulator -- 4.10 Pre‐Existing Trap Density and their Respective Location -- 4.11 Use of High‐K Dielectric in MU‐G FET -- 4.12 Properties of Trap in the High‐K with Interfacial Layer -- 4.13 Trap Extraction Techniques -- 4.13.1 Capacitance Inversion Technique (CIT) -- 4.13.2 Charge Pumping Technique (CPT) -- 4.14 Conclusion -- References -- Chapter 5 Strain Engineering for Highly Scaled MOSFETs -- 5.1 Introduction -- 5.2 Simulation Approach -- 5.2.1 Strain Mapping -- 5.2.2 Mechanical Strain Modeling -- 5.2.3 Piezoresistivity Effect -- 5.2.4 Strain Induced Carrier Mobility -- 5.3 Case Study -- 5.3.1 Stress/Strain Engineering in Bulk‐Si FinFETs -- 5.3.1.1 Performance Analysis of Bulk‐Si FinFET -- 5.3.1.2 Effects of Fin Geometry Variations -- 5.3.2 Nanosheet -- 5.3.2.1 Impact of Mechanical Stress -- 5.3.2.2 Strained Engineering with Embedded Source/Drain Stressor -- 5.3.3 Extremely Thin SOI MOSFETs -- 5.4 Conclusions -- References. Chapter 6 TCAD Analysis of Linearity Performance on Modified Ferroelectric Layer in FET Device with Spacer -- 6.1 Introduction -- 6.2 Simulation and Structure of Device -- 6.3 Results and Analysis -- 6.4 Conclusion -- Acknowledgment -- References -- Chapter 7 Electrically Doped Nano Devices: A First Principle Paradigm -- 7.1 Introduction -- 7.2 Electrical Doping -- 7.3 First Principle -- 7.3.1 DFT -- 7.3.2 NEGF -- 7.4 Molecular Simulation -- 7.5 Conclusion -- References -- Chapter 8 Tunnel FET: Principles and Operations -- 8.1 Introduction to Quantum Mechanics and Principles of Tunneling -- 8.2 Tunnel Field‐Effect Transistor -- 8.3 Challenges of Tunnel Field‐Effect Transistor -- 8.3.1 Low On‐state Current -- 8.3.2 Drain‐Induced Barrier Thinning Effect -- 8.3.3 Ambipolarity -- 8.3.4 Trap‐Assisted Tunneling -- 8.4 Techniques for Improving Electrical Performance of Tunnel Field‐Effect Transistor -- 8.4.1 Doping Engineering -- 8.4.2 Material Engineering -- 8.4.3 Geometry and Structure Engineering -- 8.5 Conclusion -- References -- Chapter 9 GaN Devices for Optoelectronics Applications -- 9.1 Introduction -- 9.2 Properties of GaN‐Based Material -- 9.2.1 Bandgap of GaN -- 9.2.2 Critical Electric Field of GaN -- 9.2.3 ON‐resistance of GaN -- 9.2.4 Two‐dimensional Electron Gas Formation at AlGaN/GaN Interface -- 9.3 GaN LEDs -- 9.3.1 Different Colors LEDs -- 9.3.2 μ‐LEDs -- 9.3.3 Micro‐LEDs with GaN‐based N‐doped Quantum Barriers -- 9.3.4 Blue Light Emission in GaN‐based LEDs -- 9.3.5 Characteristics -- 9.4 GaN Lasers -- 9.4.1 Blue Laser Diodes -- 9.5 GaN HEMTs for Optoelectronics -- 9.6 GaN Sensors -- References -- Chapter 10 First Principles Theoretical Design on Graphene‐Based Field‐Effect Transistors -- 10.1 Introduction -- 10.2 Graphene -- 10.2.1 Electronic Structure -- 10.2.2 Scanning Tunneling Microscopy -- 10.2.3 Electronic Transport. 10.3 Graphene/h‐BN Hybrid Structure -- 10.3.1 Atomic Structure -- 10.3.2 Structure and Energetics -- 10.3.3 Electronic Structure -- 10.3.4 Scanning Tunneling Microscopy -- 10.4 Conclusions -- Acknowledgments -- References -- Chapter 11 Performance Analysis of Nanosheet Transistors for Analog ICs -- 11.1 Introduction -- 11.2 Evolution of Nanosheet Transistors -- 11.2.1 Short‐Channel Effects and Their Mitigation -- 11.2.2 The FinFET Technology -- 11.2.3 Advent of Nanosheet Transistors -- 11.3 TCAD Modeling of Nanosheet Transistor -- 11.4 Transistor's Analog Performance Parameters -- 11.4.1 Transconductance -- 11.4.2 Output Conductance -- 11.4.3 Intrinsic Gain -- 11.4.4 Transconductance Efficiency -- 11.4.5 Discharge Time -- 11.4.6 Small Signal Capacitances and AC Model -- 11.4.7 Transit Frequency -- 11.5 Challenges and Perspectives of Modern Analog Design -- References -- Chapter 12 Low‐Power Analog Amplifier Design using MOS Transistor in the Weak Inversion Mode -- 12.1 Introduction -- 12.2 Review of the Theory of Weak Inversion Mode Operation of MOS Transistor -- 12.2.1 Drain Current Model in the Weak Inversion Mode -- 12.2.2 Concept of Inversion Coefficient -- 12.2.3 Parameter Extraction -- 12.2.3.1 Technology Current Constant Io -- 12.2.3.2 Sub‐threshold Swing Factor η -- 12.2.4 Small Signal Parameters in Weak Inversion Region -- 12.3 Design Steps for Transistor Sizing Using the IC -- 12.4 Design Examples -- 12.4.1 Design of a Common Source Amplifier -- 12.4.2 Single‐Ended Operational Transconductance Amplifier -- 12.4.2.1 Implementation and Simulation Result -- 12.5 Summary -- References -- Chapter 13 Ultra‐conductive Junctionless Tunnel Field‐effect Transistor‐based Biosensor with Negative Capacitance -- 13.1 Introduction -- 13.2 Importance of SS and ION/IOFF in Biosensing -- 13.3 Importance of Dopingless Source and Drain in High Conductivity. 13.4 Relation of Negative Capacitance with Non‐hysteresis and Effect on Biosensing -- 13.5 Variation of Source Material on Biosensing -- 13.6 Importance of Dual Gate and Ferroelectricity on Biosensing -- 13.7 Effect of Dual Material Gate on Biosensing -- References -- Chapter 14 Conclusion and Future Perspectives -- 14.1 Applications -- 14.1.1 Opportunities in Big Data -- 14.1.2 Fight Against Environment Change -- 14.1.3 Creation of Graphene -- 14.1.4 Nano Systems -- 14.1.5 Nanosensors -- 14.2 Some Recent Developments -- 14.3 Future Perspectives -- 14.4 Conclusion -- References -- Index -- EULA. |
| Record Nr. | UNINA-9911020043303321 |
Biswas Kalyan
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| Newark : , : John Wiley & Sons, Incorporated, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Advanced Ultra Low-Power Semiconductor Devices : Design and Applications
| Advanced Ultra Low-Power Semiconductor Devices : Design and Applications |
| Autore | Tayal Shubham |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Newark : , : John Wiley & Sons, Incorporated, , 2023 |
| Descrizione fisica | 1 online resource (313 pages) |
| Altri autori (Persone) |
UpadhyayAbhishek Kumar
RahiShiromani Balmukund SongYoung Suh |
| Soggetto topico |
Transistors
Metal oxide semiconductor field-effect transistors |
| ISBN |
9781394167647
1394167644 9781394167630 1394167636 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover -- Title Page -- Copyright Page -- Contents -- Preface -- Chapter 1 Subthreshold Transistors: Concept and Technology -- 1.1 Introduction -- 1.2 Major Sources of Leakage and Possible Methods of Prevention -- 1.2.1 Leakage Mechanisms in MOS Transistors -- 1.2.1.1 Current I1 -- 1.2.1.2 Current I2 -- 1.2.1.3 Current I3 -- 1.2.1.4 Current I4 -- 1.2.1.5 Current I5 -- 1.2.1.6 Current I6 -- 1.2.2 Leakage Reduction Techniques -- 1.2.2.1 Leakage Reduction by Channel Processing -- 1.2.2.2 Leakage Reduction Through Different Circuit Techniques -- 1.2.2.3 Scaling of Supply Voltage -- 1.3 Possibilities and Challenges -- 1.4 Conclusions -- References -- Chapter 2 Introduction to Conventional MOSFET and Advanced Transistor TFET -- 2.1 Introduction -- 2.2 Device Structure -- 2.3 TFET Principle of Operation -- 2.3.1 OFF State -- 2.3.2 ON State -- 2.4 Material Characterization -- 2.4.1 Group IV Materials -- 2.4.2 Group III-V Materials -- 2.4.3 Heterostructures -- 2.4.4 2D Materials -- 2.5 Characteristics of TFET -- 2.5.1 Subthreshold Swing -- 2.5.2 ION/IOFF Ratio -- 2.5.3 Ambipolar Effect -- 2.6 Comparison of OFF-State Characteristics -- 2.7 Phonon Scattering's Impact -- 2.8 ON-State Performance Comparison -- 2.9 Performance Analysis Based on Intrinsic Delay -- 2.10 Bandgap's Effect on Device Performance -- 2.11 MOSFET and TFET Scaling Behaviour -- 2.12 Surface Potential of an N-TFET and N-MOSFET -- 2.13 Professional Advantages of TFET over MOSFET -- 2.14 Conclusion -- References -- Chapter 3 Operation Principle and Fabrication of TFET -- 3.1 Introduction -- 3.2 Planar MOSFET's Limitations -- 3.2.1 Effects of Short Channels -- 3.3 Demand for Low Power Operation -- 3.4 TFET: Operation Principle of TFET -- 3.5 TFET: Recent Design Issues in TFET -- 3.5.1 TFET: Subthreshold Swing Perspective -- 3.5.2 TFET: Power Consumption Perspective.
3.6 TFET: Modeling and Application -- 3.6.1 TFET: Modeling -- 3.6.2 TFET: Application -- 3.7 TFET: Fabrication Perspective -- 3.8 TFET: Applications and Future of Low-Power Electronics -- 3.9 Expected Challenges in Replacing MOSFET with TFET -- 3.10 Conclusion -- References -- Chapter 4 Mathematical Modeling of TFET and Its Future Applications: Ultra Low.Power SRAM Circuit and III-IV TFET -- 4.1 Introduction -- 4.2 Modeling Approaches -- 4.2.1 Atomistic Modeling -- 4.2.2 Analytical Modeling -- 4.3 Structure -- 4.3.1 Effect Transistor -- 4.3.2 Compact Models -- 4.4 Applications of Tunnel Field-Effect Transistor -- 4.4.1 TFET for Biosensor Applications -- 4.4.2 TFET-Based Memory Devices -- 4.4.3 TFETs for Mixed Signal Applications -- 4.4.4 TFETs for Analog/RF Applications -- 4.4.5 TFETs for Low-Power Applications -- 4.5 Road Ahead for Tunnel Field Effect Transistors -- References -- Chapter 5 Analysis of Channel Doping Variation on Transfer Characteristics to High Frequency Performance of F-TFET -- 5.1 Introduction -- 5.2 Simulated Device Structure and Parameters -- 5.3 DC Characteristics -- 5.4 Analysis of Analog/RF FOMs -- 5.5 Conclusion -- References -- Chapter 6 Comparative Study of Gate Engineered TFETs and Optimization of Ferroelectric Heterogate TFET Structure -- 6.1 Introduction -- 6.2 Study of Different TFET Structures -- 6.2.1 Simulation Configuration -- 6.2.2 Comparison of Electrical Parameters of Different Structures of TFET -- 6.3 Proposed Structure -- 6.4 Results and Discussion -- 6.4.1 2-D Model for Surface Potential -- 6.4.2 Study of Electrical Characteristics -- 6.4.2.1 Average Subthreshold Swing and ION/IOFF -- 6.4.2.2 DIBL -- 6.4.2.3 RDF Effect -- 6.4.2.4 Temperature Dependence -- 6.4.2.5 Study of Interface Traps -- 6.4.3 Memory Window -- 6.5 Conclusion -- 6.6 Future Scope -- References. Chapter 7 State of the Art Tunnel FETs for Low Power Memory Applications -- 7.1 Static Random Access Memory -- 7.1.1 Working of 6T-SRAM Cell -- 7.1.1.1 Read Operation -- 7.1.1.2 Write Operation -- 7.2 Performance Parameters of SRAM Cell -- 7.3 TFET-Based SRAM Cell Design -- 7.3.1 6T SRAM Designs -- 7.3.2 7T- SRAM Cell Design -- 7.3.3 8T- SRAM Cell -- 7.3.4 10 T- SRAM Cell -- 7.3.5 SRAM Cell Design Based on Negative Differential Resistance Property -- 7.4 Conclusion -- References -- Chapter 8 Epitaxial Layer-Based Si/SiGe Hetero-Junction Line Tunnel FETs: A Physical Insight -- 8.1 Fundamental Limitation of CMOS: Tunnel FETs -- 8.2 Working Principle of Tunnel FET -- 8.3 Point and Line TFETs: Tunneling Direction -- 8.4 Perspective of Line TFETs -- 8.4.1 Planar Line Tunnel FETs -- 8.4.2 3D Line TFETs -- 8.5 Analytical Models of Line TFETs -- 8.6 Line TFETs for Analog & -- Digital Circuits Design -- 8.7 Other Steep Slope Devices -- 8.8 Conclusion -- References -- Chapter 9 Investigation of Thermal Performance on Conventional and Junctionless Nanosheet Field Effect Transistors -- 9.1 Introduction -- 9.2 Device Simulation Details -- 9.3 Results and Discussion -- 9.3.1 Comparison of Thermal Characteristics of Conventional (CL) and Junctionless (JL) NSFET -- 9.3.2 Comparison of Thermal Performance of High-k Gate Dielectrics for CL NSFET and JL NSFET -- 9.3.3 Comparison of Thermal Performance of Spacer Dielectrics for CL NSFET and JL NSFET -- 9.4 Conclusion -- Acknowledgement -- References -- Chapter 10 Introduction to Newly Adopted NCFET and Ferroelectrics for Low-Power Application -- 10.1 Introduction -- 10.2 NCFET and Its Design Constraints -- 10.2.1 Ferroelectric Materials -- 10.2.2 NCFET Structure -- 10.2.3 Capacitance Matching and Ferroelectric Parameters -- 10.3 NCFET for Low-Power Applications -- 10.3.1 NCFET for Circuit and System Design. 10.3.2 Impact of Process Variations on NCFET -- 10.3.3 Analytical Models for NCFET -- 10.4 Summary -- References -- Chapter 11 Application of Ferroelectrics: Monolithic-3D Inference Engine with IGZO Based Ferroelectric Thin Film Transistor Synapses -- 11.1 Introduction -- 11.2 Ferroelectricity in Hafnium Oxide -- 11.2.1 Thermodynamic and Kinetic Origin of the Ferroelectric Phase -- 11.2.2 Microstructure-Based Variability in Ferroelectric Response -- 11.3 IGZO Based Ferroelectric Thin Film Transistor -- 11.3.1 Integration and Performance of FeTFT Devices -- 11.3.2 Characterization of FeTFT-Based Neuromorphic Devices -- 11.4 Applications in Neural Networks -- 11.4.1 Monolithic 3D Inference Engine -- 11.5 Conclusion -- References -- Chapter 12 Radiation Effects and Their Impact on SRAM Design: A Comprehensive Survey with Contemporary Challenges -- 12.1 Introduction -- 12.2 Literature Survey -- 12.3 Impact of Radiation Effects on Sram Cells -- 12.4 Results and Discussion -- 12.5 Conclusion -- Declarations -- Data Availability -- References -- Chapter 13 Final Summary and Future of Advanced Ultra Low Power Metal Oxide Semiconductor Field Effect Transistors -- 13.1 Introduction -- 13.2 Challenges in Future Ultra-Low Power Semiconductors -- 13.3 Conclusion -- References -- Index -- EULA. |
| Record Nr. | UNINA-9911019744103321 |
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Tayal Shubham
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| Newark : , : John Wiley & Sons, Incorporated, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Bias temperature instability for devices and circuits / / Tibor Grasser, editor
| Bias temperature instability for devices and circuits / / Tibor Grasser, editor |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | New York : , : Springer, , 2014 |
| Descrizione fisica | 1 online resource (xi, 810 pages) : illustrations (some color) |
| Disciplina | 621.3192 |
| Collana | Gale eBooks |
| Soggetto topico | Metal oxide semiconductor field-effect transistors |
| ISBN | 1-4614-7909-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Characterization, Experimental Challenges -- Advanced Characterization -- Characterization of Nanoscale Devices -- Statistical Properties/Variability -- Theoretical Understanding -- Possible Defects: Experimental -- Possible Defects: First Principles -- Modeling -- Technological Impact -- Silicon dioxides/SiON -- High-k oxides -- Alternative technologies -- Circuits. |
| Record Nr. | UNINA-9910299747703321 |
| New York : , : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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CMOS : circuit design, layout, and simulation / / R. Jacob Baker
| CMOS : circuit design, layout, and simulation / / R. Jacob Baker |
| Autore | Baker R. Jacob <1964-> |
| Edizione | [Third edition] |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley & Sons, Inc., [2010] |
| Descrizione fisica | 1 online resource (1214 pages) |
| Disciplina |
621.3815
621.39/732 |
| Collana | IEEE Press series on microelectronic systems |
| Soggetto topico |
Metal oxide semiconductors, Complementary - Design and construction
Integrated circuits - Design and construction Metal oxide semiconductor field-effect transistors Metall-òxid-semiconductors complementaris - Disseny i construcció Circuits integrats Transistors MOSFET |
| ISBN |
9780470891179
1-118-03823-1 1-283-37262-2 9786613372628 0-470-89117-3 0-470-89116-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
CMOS Circuit Design, Layout, and Simulation; Contents; Preface; Chapter 1 Introduction to CMOS Design; Chapter 2 The Well; Chapter 3 The Metal Layers; Chapter 4 The Active and Poly Layers; Chapter 5 Resistors, Capacitors, MOSFETs; Chapter 6 MOSFET Operation; Chapter 7 CMOS Fabrication; Chapter 8 Electrical Noise: An Overview; Chapter 9 Models for Analog Design; Chapter 10 Models for Digital Design; Chapter 11 The Inverter; Chapter 12 Static Logic Gates; Chapter 13 Clocked Circuits; Chapter 14 Dynamic Logic Gates; Chapter 15 VLSI Layout Examples; Chapter 16 Memory Circuits
Chapter 17 Sensing Using ?S ModulationChapter 18 Special Purpose CMOS Circuits; Chapter 19 Digital Phase-Locked Loops; Chapter 20 Current Mirrors; Chapter 21 Amplifiers; Chapter 22 Differential Amplifiers; Chapter 23 Voltage References; Chapter 24 Operational Amplifiers I; Chapter 25 Dynamic Analog Circuits; Chapter 26 Operational Amplifiers II; Chapter 27 Nonlinear Analog Circuits; Chapter 28 Data Converter Fundamentals; Chapter 29 Data Converter Architectures; Chapter 30 Implementing Data Converters; Chapter 31 Feedback Amplifiers; Index; About the Author |
| Record Nr. | UNINA-9910140906703321 |
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Baker R. Jacob <1964->
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| Hoboken, NJ, : John Wiley & Sons, Inc., [2010] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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CMOS circuit design, layout, and simulation / R. Jacob Baker
| CMOS circuit design, layout, and simulation / R. Jacob Baker |
| Autore | Baker Russel Jacob 1964- |
| Edizione | [4th ed.] |
| Descrizione fisica | XXXV, 1235 p. : ill. ; 29 cm |
| Disciplina | 621.3815 |
| Collana | IEEE press series on microelectronic systems |
| Soggetto topico |
Metal oxide semiconductors, Complementary - Design and construction
Integrated circuits - Design and construction Metal oxide semiconductor field-effect transistors |
| ISBN | 9781119481515 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISALENTO-991004297734907536 |
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Baker Russel Jacob 1964-
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| Materiale a stampa | ||
| Lo trovi qui: Univ. del Salento | ||
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CMOS circuit design, layout, and simulation / R. Jacob Baker, Harry W. Li, and David E. Boyce
| CMOS circuit design, layout, and simulation / R. Jacob Baker, Harry W. Li, and David E. Boyce |
| Autore | Baker, R. Jacob, 1964- |
| Pubbl/distr/stampa | New York : IEEE |
| Descrizione fisica | xxiv, 902 p. : ill. ; 24 cm |
| Disciplina | 621.3815 |
| Altri autori (Persone) |
Li, Harry W., 1960-
Boyce, David E., 1940- |
| Altri autori (Enti) | Institute of Electrical and Electronics Engineers |
| Collana | IEEE Press series on microelectronic systems |
| Soggetto topico |
Metal oxide semiconductors, Complementary - Design and construction
Integrated circuits - Design and construction Metal oxide semiconductor field-effect transistors |
| ISBN | 0780334167 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISALENTO-991001039109707536 |
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Baker, R. Jacob, 1964-
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| New York : IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Salento | ||
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Complementary Metal Oxide Semiconductor / / edited by Kim Ho Yeap and Humaira Nisar
| Complementary Metal Oxide Semiconductor / / edited by Kim Ho Yeap and Humaira Nisar |
| Pubbl/distr/stampa | Croatia : , : IntechOpen, , 2018 |
| Descrizione fisica | 1 online resource (162 pages) : illustrations |
| Disciplina | 621.3815284 |
| Soggetto topico | Metal oxide semiconductor field-effect transistors |
| ISBN |
1-83881-512-0
1-78923-497-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910317801903321 |
| Croatia : , : IntechOpen, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Leakage current and defect characterization of short channel MOSFETs / / Guntrade Roll
| Leakage current and defect characterization of short channel MOSFETs / / Guntrade Roll |
| Autore | Roll Guntrade |
| Pubbl/distr/stampa | Berlin : , : Logos Verlag Berlin, , [2014] |
| Descrizione fisica | 1 online resource (242 pages) |
| Disciplina | 621.3815284 |
| Collana | Research at NaMLab |
| Soggetto topico | Metal oxide semiconductor field-effect transistors |
| Soggetto genere / forma | Electronic books. |
| ISBN | 3-8325-9666-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910466968503321 |
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Roll Guntrade
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| Berlin : , : Logos Verlag Berlin, , [2014] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Leakage current and defect characterization of short channel MOSFETs / / Guntrade Roll
| Leakage current and defect characterization of short channel MOSFETs / / Guntrade Roll |
| Autore | Roll Guntrade |
| Pubbl/distr/stampa | Berlin : , : Logos Verlag Berlin, , [2014] |
| Descrizione fisica | 1 online resource (242 pages) |
| Disciplina | 621.3815284 |
| Collana | Research at NaMLab |
| Soggetto topico | Metal oxide semiconductor field-effect transistors |
| ISBN | 3-8325-9666-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910795584703321 |
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Roll Guntrade
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| Berlin : , : Logos Verlag Berlin, , [2014] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Leakage current and defect characterization of short channel MOSFETs / / Guntrade Roll
| Leakage current and defect characterization of short channel MOSFETs / / Guntrade Roll |
| Autore | Roll Guntrade |
| Pubbl/distr/stampa | Berlin : , : Logos Verlag Berlin, , [2014] |
| Descrizione fisica | 1 online resource (242 pages) |
| Disciplina | 621.3815284 |
| Collana | Research at NaMLab |
| Soggetto topico | Metal oxide semiconductor field-effect transistors |
| ISBN | 3-8325-9666-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910822454603321 |
|
Roll Guntrade
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| Berlin : , : Logos Verlag Berlin, , [2014] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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