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Digital design techniques and exercises : a practice book for digital logic design / / Vaibbhav Taraate
| Digital design techniques and exercises : a practice book for digital logic design / / Vaibbhav Taraate |
| Autore | Taraate Vaibbhav |
| Pubbl/distr/stampa | Gateway East, Singapore : , : Springer, , [2022] |
| Descrizione fisica | 1 online resource (204 pages) |
| Disciplina | 621.395 |
| Soggetto topico |
Logic design - Data processing
Logic design |
| ISBN |
981-16-5955-9
981-16-5954-0 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Acknowledgements -- Contents -- About the Author -- 1 Basics of Digital Design -- 1.1 Digital Logic and the Evolution -- 1.2 The Important Considerations -- 1.2.1 Area of the Design -- 1.2.2 Speed of the Design -- 1.2.3 Power -- 1.3 Logic Gates -- 1.4 De Morgan's Theorems -- 1.4.1 NAND is Equal to Bubbled OR -- 1.4.2 NOR is Equal to Bubbled AND -- 1.5 Multiplexer as Universal Logic -- 1.6 Optimization Goals and Applications in VLSI Context -- 1.7 Exercises -- 1.7.1 Exercise 1: Use of the Logical Expressions to Get the Logic Equivalent -- 1.7.2 Exercise 2: Cascade Logic and How to Get Logic Expression? -- 1.7.3 Exercise 3: Complement Logic -- 1.7.4 Exercise 4: Logic Expression for the Cascade Logic -- 1.7.5 Exercise 5: Output Expression for the Cascade Logic -- 1.7.6 Exercise 6: Propagation Delay for the Cascade Logic -- 1.7.7 Exercise 7: Logic Gate Output Expression -- 1.7.8 Exercise 8: Propagation Delay for the Cascade Logic -- 1.7.9 Exercise 9: The Equivalent Logic Expression -- 1.7.10 Exercise 10: The Equivalent Logic Gate -- 1.8 Important Takeaways -- 2 Design Using Universal Logic -- 2.1 What Is Universal Logic? -- 2.2 Universal Gates -- 2.2.1 NAND -- 2.2.2 NOR -- 2.2.3 Other Application-Specific Universal Gates -- 2.3 Multiplexers -- 2.3.1 Design Using 2:1 Mux -- 2.3.2 4:1 MUX Using 2:1 Mux -- 2.3.3 Design Using Multiplexers -- 2.4 Exercises -- 2.4.1 Exercise 1: Design Using Universal Gates -- 2.4.2 Exercise 2: Design Using the MUX -- 2.4.3 Exercise 3: Design Using MUX -- 2.4.4 Exercise 4: Design Using Custom Gates -- 2.4.5 Exercise 5: Optimization Exercise -- 2.4.6 Exercise 7: Design Using the MUX -- 2.4.7 Exercise 8: Design Using MUX -- 2.4.8 Exercise 9: Design Using Custom Gates -- 2.5 Applications and Use in VLSI Context -- 2.6 Important Takeaways -- 3 Combinational Design Resources -- 3.1 Code Converters.
3.1.1 Three-Bit Binary-to-Gray Code Converter -- 3.1.2 3-Bit Gray-to-Binary Code Converter -- 3.2 Arithmetic Resources -- 3.2.1 Half-Adder -- 3.2.2 Half-Subtractor -- 3.2.3 Full-Adder -- 3.3 Use of Arithmetic Resources in the Design -- 3.4 Design Using Arithmetic Resources and Control Elements -- 3.5 Optimization Goals -- 3.6 Processor Logic and Need of Arithmetic Resources -- 3.7 Exercises -- 3.7.1 Exercise 1: Cascade Versus Parallel Logic -- 3.7.2 Exercise 2: Delay of the Design -- 3.7.3 Exercise 3: Speed -- 3.7.4 Exercise 4: Design to perform the Addition and Subtraction -- 3.7.5 Exercise 4: Design with the Goal to Use Resource Sharing -- 3.8 Important Takeaways -- 4 Case Study: ALU Design -- 4.1 Design Specifications and Their Role -- 4.2 What Is ALU? -- 4.3 Arithmetic Unit Design -- 4.3.1 Resources Required -- 4.3.2 How to Start Design of ALU? -- 4.3.3 How to Design the Logic -- 4.3.4 Exercise 1: Optimization of the Arithmetic Unit -- 4.3.5 Logic Unit Design -- 4.3.6 Resources Required -- 4.3.7 How to Design the Logic Unit to have Better Area? -- 4.4 ALU Design -- 4.4.1 Resource Requirement and How to Design Efficient ALU? -- 4.4.2 ALU Design to have Better Area -- 4.4.3 Exercise 2: Optimization of ALU -- 4.5 Few Important Design Guidelines -- 4.6 Important Takeaways -- 5 Practical Scenarios and the Design Techniques -- 5.1 Parallel Logic -- 5.1.1 Decoder 2 to 4 -- 5.2 Encoder -- 5.3 Encoder with Invalid Output Detection Logic -- 5.4 Exercises -- 5.4.1 Exercise 1: Design of Decoder Having Active-Low Output -- 5.4.2 Exercise 2: Design the Function Using Decoder -- 5.4.3 Exercise 3: Design Using Decoders -- 5.4.4 Exercise 4: Design Using Decoder and NAND Gates -- 5.4.5 Exercise 5: Design Using Decoders -- 5.4.6 Exercise 6: Priority Encoder Design -- 5.5 Important Takeaways -- 6 Basics of the Sequential Design. 6.1 What Is Sequential Logic Design? -- 6.2 Sequential Design Elements -- 6.3 Level Versus Edge-Triggered Logic -- 6.4 Latches and Their Use in the Design -- 6.4.1 Positive-Level-Sensitive D Latch -- 6.4.2 Negative-Level-Sensitive D Latch -- 6.5 Edge-Sensitive Elements and Their Role -- 6.5.1 Positive Edge-Sensitive D Flip-Flop -- 6.5.2 Negative Edge-Sensitive D Flip-Flop -- 6.6 Applications -- 6.6.1 Applications of the Latches -- 6.6.2 Applications of the Flip-Flop -- 6.7 Exercises -- 6.7.1 Exercise 1: Design Positive-Level-Sensitive Latch Using Multiplexers -- 6.7.2 Exercise 2: Design Negative-Level-Sensitive Latch Using Multiplexers -- 6.7.3 Exercise 3: What Is the Functionality of the Following Design? -- 6.7.4 Exercise 4: Design the Positive Edge-Sensitive Flip-Flop Using Latches -- 6.7.5 Exercise 5: Design the Negative Edge-Sensitive Flip-Flop Using Latches -- 6.7.6 Exercise 6: What Is the Operating Frequency of the Following Circuit? -- 6.7.7 Exercise 7: The Asynchronous Clear -- 6.7.8 Exercise 8: The Synchronous Clear -- 6.8 Important Takeaways -- 7 Sequential Design Techniques -- 7.1 Synchronous Design -- 7.2 Asynchronous Design -- 7.3 Why to Use Synchronous Design? -- 7.3.1 Which Elements We Should Use During Design? -- 7.4 D Flip-Flop and Use in the Design -- 7.5 Design for the given specifications -- 7.6 Design of the Synchronous Counters -- 7.7 Exercise 1: Design of the Synchronous Down-Counters -- 7.8 Exercise 2: Design of the Synchronous Gray Counter -- 7.9 Few Important Guidelines -- 7.10 Important Takeaways -- 8 Important Design Scenarios -- 8.1 MOD-3 Counter -- 8.2 The Design of MOD-3 Counter with 50% Duty Cycle -- 8.3 Applications and Use of Counters -- 8.3.1 Ring Counter -- 8.3.2 Johnson Counter -- 8.4 Exercises -- 8.4.1 Exercise 1: The Counter Output -- 8.4.2 Exercise 2: Find the Output Sequence. 8.4.3 Exercise 3: Operating Frequency of Design -- 8.4.4 Exercise 4: Output on 1024th Clock Cycle -- 8.4.5 Exercise 5: Output on the 4th Clock Cycle -- 8.4.6 Exercise 6: Output at 10th Clock Pulse -- 8.4.7 Exercise 7: Design the Serial Input Serial Output Shift Register -- 8.5 Important Takeaways -- 9 FSM Design Techniques -- 9.1 What Is FSM? -- 9.1.1 Moore FSM -- 9.1.2 Mealy FSM -- 9.1.3 Moore Versus Mealy FSM -- 9.2 State Encoding Methods -- 9.3 Moore FSM Design -- 9.4 Mealy FSM Design -- 9.5 Applications and Design Strategies -- 9.6 Exercises -- 9.6.1 Exercise 1: Moore Machine State Diagram -- 9.6.2 Exercise 2: Mealy Machine -- 9.6.3 Exercise 3: One-Hot Encoding -- 9.6.4 Exercise 4: FSM Area and Power Optimization -- 9.7 Important Takeaways -- 10 Advanced Design Techniques-1 -- 10.1 Various Paths in the Design -- 10.2 Data and Control Paths -- 10.3 Mealy Sequence Detector Design -- 10.4 Data and Control Path Design Techniques -- 10.5 Flip-Flop Timing Parameters -- 10.6 Example on Performance Improvement of the Design -- 10.7 Exercises -- 10.7.1 Exercise 1: Maximum Operating Frequency -- 10.7.2 Exercise 2: Timing Paths -- 10.7.3 Exercise 3: Maximum Operating Frequency -- 10.7.4 Exercise 4: Positive Clock Skew and Maximum Operating Frequency for the Design -- 10.7.5 Exercise 5: Negative Clock Skew and Maximum Operating Frequency for the Design -- 10.8 Important Takeaways -- 11 Advanced Design Techniques-2 -- 11.1 Multiple Clock Domain Designs -- 11.2 Metastability -- 11.3 Control Path Synchronizer -- 11.4 Data Path Synchronizer -- 11.5 Multiple Power Domain Designs -- 11.6 Architecture-Level Designs -- 11.7 How We Can Improve the Design Performance -- 11.8 The Digital Systems and Design -- 11.9 Exercises -- 11.9.1 Exercise 1: FIFO Depth Calculation -- 11.9.2 Exercise 2: FIFO Depth Calculation -- 11.9.3 Exercise 3: FIFO Depth Calculation. 11.9.4 Exercise 4: FIFO Depth Calculation -- 11.9.5 Exercise 5: FIFO Depth Calculation -- 11.10 Important Takeaways -- 12 System Design and Considerations -- 12.1 System Design -- 12.2 What We Need to Think About? -- 12.3 Important Considerations -- 12.4 Let Us Understand the Microprocessor Capabilities -- 12.5 Control Signal Generation Logic -- 12.6 IO Devices and Communication with the Processor -- 12.7 Memory Devices and Communication with the Processor -- 12.8 Design Scenarios and Optimization -- 12.9 Concluding Comments -- Index. |
| Record Nr. | UNINA-9910743257703321 |
Taraate Vaibbhav
|
||
| Gateway East, Singapore : , : Springer, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital design using QuarkXPress 4 [[electronic resource] /] / Paul Honeywill and Tony Lockhart
| Digital design using QuarkXPress 4 [[electronic resource] /] / Paul Honeywill and Tony Lockhart |
| Autore | Honeywill Paul |
| Pubbl/distr/stampa | Exeter [England], : Intellect Books, 2002 |
| Descrizione fisica | 1 online resource (194 p.) |
| Disciplina | 686.225445369 |
| Altri autori (Persone) | LockhartTony |
| Soggetto topico |
Programmable logic devices - Design - Data processing
Logic design - Data processing |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-47741-5
9786610477418 1-84150-852-7 0-585-21889-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Front Cover; Preliminaries; Table of Contents; Preface; Chapter 1: You, Intuition and the QuarkXPress Interface; Chapter 2: Using Quark XPress; Chapter 3: You, Design and Working with QuarkXPress; Chapter 4: Structuring a Document; Chapter 5: Using Elements (Items) within a Document; Chapter 6: Using Digital Type within Quark XPress; Chapter 7: When your Document leaves the Desktop; Index; Back Cover |
| Record Nr. | UNINA-9910455519203321 |
|
Honeywill Paul
|
||
| Exeter [England], : Intellect Books, 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital design using QuarkXPress 4 [[electronic resource] /] / Paul Honeywill and Tony Lockhart
| Digital design using QuarkXPress 4 [[electronic resource] /] / Paul Honeywill and Tony Lockhart |
| Autore | Honeywill Paul |
| Pubbl/distr/stampa | Exeter [England], : Intellect Books, 2002 |
| Descrizione fisica | 1 online resource (194 p.) |
| Disciplina | 686.225445369 |
| Altri autori (Persone) | LockhartTony |
| Soggetto topico |
Programmable logic devices - Design - Data processing
Logic design - Data processing |
| ISBN |
1-280-47741-5
9786610477418 1-84150-852-7 0-585-21889-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Front Cover; Preliminaries; Table of Contents; Preface; Chapter 1: You, Intuition and the QuarkXPress Interface; Chapter 2: Using Quark XPress; Chapter 3: You, Design and Working with QuarkXPress; Chapter 4: Structuring a Document; Chapter 5: Using Elements (Items) within a Document; Chapter 6: Using Digital Type within Quark XPress; Chapter 7: When your Document leaves the Desktop; Index; Back Cover |
| Record Nr. | UNINA-9910778897503321 |
|
Honeywill Paul
|
||
| Exeter [England], : Intellect Books, 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital logic design using Verilog : coding and RTL synthesis / / Vaibbhav Taraate
| Digital logic design using Verilog : coding and RTL synthesis / / Vaibbhav Taraate |
| Autore | Taraate Vaibbhav |
| Edizione | [2nd ed.] |
| Pubbl/distr/stampa | Singapore : , : Springer, , [2022] |
| Descrizione fisica | 1 online resource (607 pages) |
| Disciplina | 371.320973 |
| Soggetto topico |
Logic design - Data processing
Verilog (Computer hardware description language) |
| ISBN |
981-16-3199-9
981-16-3198-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Acknowledgements -- Contents -- About the Author -- 1 Introduction -- 1.1 Evolution of Logic Design -- 1.2 System and Logic Design Abstractions -- 1.2.1 Architecture Design -- 1.2.2 Micro-architecture Design -- 1.2.3 RTL Design and Synthesis -- 1.2.4 Switch Level Design -- 1.3 Integrated Circuit Design and Methodologies -- 1.3.1 RTL Design -- 1.3.2 Functional Verification -- 1.3.3 Synthesis -- 1.3.4 Physical Design -- 1.4 Verilog as Hardware Description Language -- 1.5 Verilog Design Description -- 1.5.1 Structural Design -- 1.5.2 Behavior Design -- 1.5.3 Synthesizable Design -- 1.6 Few Important Verilog Terminologies -- 1.7 Exercises -- 1.8 Summary -- 2 Concept of Concurrency and Verilog Operators -- 2.1 Use of Continuous Assignment to Model Design -- 2.2 Use of always Procedural Block to Implement Combinational Design -- 2.3 Concept of Concurrency -- 2.4 Verilog Arithmetic Operators -- 2.5 Verilog Logical Operators -- 2.6 Verilog Equality and Inequality Operators -- 2.7 Verilog Sign Operators -- 2.8 Verilog Bitwise Operators -- 2.9 Verilog Relational Operators -- 2.10 Verilog Concatenation and Replication Operators -- 2.11 Verilog Reduction Operators -- 2.12 Verilog Shift Operators -- 2.13 Exercises -- 2.14 Summary -- 3 Verilog Constructs and Combinational Design-I -- 3.1 The Role of Constructs -- 3.2 Logic Gates and Synthesizable RTL -- 3.2.1 NOT or Invert Logic -- 3.2.2 OR Logic -- 3.2.3 NOR Logic -- 3.2.4 AND Logic -- 3.2.5 NAND Logic -- 3.2.6 Two Input XOR Logic -- 3.2.7 Two Input XNOR Logic -- 3.3 Tristate Logic -- 3.4 Arithmetic Circuits -- 3.4.1 Adder -- 3.4.1.1 Half Adder -- 3.4.1.2 Full Adder -- 3.4.2 Subtractor -- 3.4.2.1 Half Subtractor -- 3.4.2.2 Full Subtractor -- 3.5 Exercises -- 3.6 Summary -- 4 Verilog Constructs and Combinational Design-II -- 4.1 Procedural Block always @*.
4.2 Multi-bit Adders and Subtractors -- 4.2.1 Four-Bit Full Adder -- 4.2.2 4-Bit Full Subtractor -- 4.2.3 4-Bit Adder and Subtractor -- 4.3 Optimization of Resources -- 4.3.1 Optimization Using Only Adders -- 4.3.2 Optimization by Tweaking the Logic to Have Better Data and Control Path -- 4.4 Procedural Block initial -- 4.5 Simulation Concepts: Basic Testbench -- 4.6 Comparators and Parity Detectors -- 4.6.1 Binary Comparators -- 4.6.2 Parity Detector -- 4.7 Code Converters -- 4.7.1 Binary to Gray Code Converter -- 4.7.2 Gray to Binary Code Converter -- 4.8 Let Us Think About the Design from Specifications -- 4.9 Exercises -- 4.10 Summary -- 5 Multiplexers as Universal Logic -- 5.1 Multiplexers -- 5.2 Multiplexer as Universal logic -- 5.2.1 2:1 MUX -- 5.3 The if...else Versus case Construct -- 5.4 The 4:1 MUX Using if...else -- 5.5 The 4:1 MUX Using case Construct -- 5.6 The 4:1 Mux Using 2:1 MUX -- 5.7 Let Us Design Combinational Logic Using Multiplexers -- 5.8 Optimization Strategies Using RTL Tweaks -- 5.9 Exercises -- 5.10 Summary -- 6 Decoders and Encoders -- 6.1 Decoders -- 6.1.1 1 Line to 2 Decoder Using case construct -- 6.1.2 1 Line to 2 Decoder Having Enable Using case -- 6.1.3 2 Line to 4 Decoder with Enable Using case -- 6.1.4 2 Line to 4 Decoder with Active Low Enable Using case -- 6.1.5 2 to 4 Decoder Using Continuous Assignments -- 6.1.6 Decoder Using Shift Operator -- 6.1.7 Testbench of 2:4 Decoder -- 6.1.8 4 Line to 16 Decoder Using 2:4 Decoder -- 6.2 Testbench for 4:16 Decoder -- 6.3 Encoders -- 6.3.1 Priority Encoders -- 6.4 Testbench of 4:2 Priority encoder -- 6.5 Exercises -- 6.6 Summary -- 7 Event Queue and Design Guidelines -- 7.1 Verilog Stratified Event Queue -- 7.2 Verilog Blocking Assignments -- 7.3 Incomplete Sensitivity List -- 7.4 Continuous Versus Procedural Assignments -- 7.5 Combinational Loops in Design. 7.6 Unintentional Latches in the Design -- 7.7 Use of Blocking Assignments -- 7.8 Use of if...else Versus case constructs -- 7.9 Nested Multiplexer or Priority Logic -- 7.10 Parallel Logic or Decoding Logic -- 7.11 Priority Encoding Structure -- 7.12 Missing default Condition in case construct -- 7.13 Nested if...else with Missing else Condition -- 7.14 Logical Equality Versus Case Equality -- 7.14.1 Logical Equality and Logical Inequality Operators -- 7.14.2 Case Equality and Case Inequality Operators -- 7.15 Multiple Driver Assignments -- 7.16 Exercises -- 7.17 Summary -- 8 Basics of Sequential Design Using Verilog -- 8.1 Sequential Logic -- 8.1.1 Positive-Level Sensitive D Latch -- 8.1.2 Negative-Level Sensitive D Latch -- 8.2 Flip-Flop -- 8.2.1 Positive Edge-Triggered D Flip-Flop -- 8.2.2 Negative Edge-Triggered D Flip-Flop -- 8.2.3 Synchronous and Asynchronous Reset -- 8.2.3.1 D Flip-Flop Having Asynchronous Reset -- 8.2.4 D Flip-Flop Having Synchronous Reset -- 8.2.5 Flip-Flop Having Synchronous Load Enable and Asynchronous Reset -- 8.2.6 Flip-Flop with Synchronous Load and Synchronous Reset -- 8.3 Exercises -- 8.4 Summary -- 9 Synchronous Counter Design Using Synthesizable Constructs -- 9.1 Synchronous Counters -- 9.1.1 Three-Bit Up Counter -- 9.1.2 Three-Bit Down Counter -- 9.1.3 Three-Bit Up-Down Counter -- 9.2 Gray Counters -- 9.2.1 Gray and Binary Counter -- 9.2.2 Ring Counters -- 9.2.3 Johnson Counters -- 9.3 BCD Up-Down Counter -- 9.4 Exercises -- 9.5 Summary -- 10 RTL Design of Registers and Memories -- 10.1 Parallel Input and Parallel Output (PIPO) Register -- 10.2 Shift Register -- 10.3 Right and Left Shift Operation -- 10.4 Timing and Performance Evaluation -- 10.5 Asynchronous Counter Design -- 10.5.1 Ripple Counters -- 10.6 RTL Design of Memories -- 10.7 Parameterized Read-Write Memory -- 10.8 Exercises -- 10.9 Summary. 11 Sequential Circuit Design Guidelines -- 11.1 What Happens If Blocking Assignments Are Used to Code Sequential Logic? -- 11.1.1 Blocking Assignments and Multiple always Blocks -- 11.1.2 Multiple Blocking Assignments Used in the Single always Block -- 11.1.3 Example Blocking Assignment -- 11.2 Non-blocking Assignments -- 11.2.1 Example Non-blocking Assignments -- 11.2.2 Example Non-blocking Assignment -- 11.2.3 Example Using Non-blocking Assignments -- 11.3 Latch Versus Flip-Flop -- 11.3.1 D Flip-Flop -- 11.3.2 Latch -- 11.4 Use of Synchronous Versus Asynchronous Reset -- 11.4.1 D Flip-Flop Having Asynchronous Reset -- 11.4.2 Synchronous Reset D Flip-Flop -- 11.5 Use of if...else Versus case constructs -- 11.6 Internally Generated Clocks -- 11.7 Guidelines for Modeling Synchronous Designs -- 11.8 Multiple Clocks in the Same module -- 11.9 Multi-phase Clocks in the Design -- 11.10 Guidelines for Modeling Asynchronous Designs -- 11.11 Exercises -- 11.12 Summary -- 12 RTL Design Strategies for Complex Designs -- 12.1 ALU Design -- 12.1.1 Logic Unit Design -- 12.1.1.1 Logic Unit to Infer Parallel Logic -- 12.1.1.2 Logic Unit Having Registered Inputs and Outputs -- 12.1.2 Arithmetic Unit -- 12.1.3 Arithmetic and Logic Unit -- 12.2 Functions and Tasks -- 12.2.1 Counting Number of 1's from the Given String -- 12.2.2 RTL Design Using function to Count Number of 1'S -- 12.3 Synthesis Result of RTL Using function -- 12.4 Synthesis Result of RTL Using task -- 12.5 Exercises -- 12.6 Summary -- 13 RTL Tweaks and Performance Improvement Techniques -- 13.1 Arithmetic Resource Sharing -- 13.1.1 RTL Design Using Resource Sharing to Have Area Optimization -- 13.2 Gated Clocks and Dynamic Power Reduction -- 13.3 Use of Pipelining in Design -- 13.3.1 Design Without Pipelining -- 13.3.2 Speed Improvement Using Register Balancing or Pipelining. 13.4 Counter Design and Duty Cycle Control -- 13.5 MOD-3 Counter RTL Design to Have 50% Duty Cycle -- 13.6 Exercise -- 13.7 Summary -- 14 Finite State Machines Using Verilog -- 14.1 Moore Versus Mealy Machines -- 14.1.1 Level to Pulse Converter -- 14.2 FSM Encoding Styles -- 14.2.1 Binary Encoding -- 14.2.1.1 Two-Bit Binary Counter FSM -- 14.2.2 Gray Encoding -- 14.2.2.1 Two-Bit Gray Counter FSM -- 14.3 One-Hot Encoding -- 14.4 Sequence Detectors Using FSMs -- 14.4.1 Mealy Sequence Detector Using Two always Procedural Blocks -- 14.4.2 Mealy Machine: Sequence Detector to Detect 101 Overlapping Sequence -- 14.5 Improving the Design Performance for FSMs -- 14.6 Exercises -- 14.7 Summary -- 15 Non-synthesizable Verilog Constructs and Testbenches -- 15.1 Intra-delay and Inter-delay Assignments -- 15.1.1 Simulation for Blocking Assignments -- 15.1.2 Simulation of Non-blocking Assignments -- 15.2 The always and initial Procedural Block -- 15.2.1 Blocking Assignments with Inter-assignment Delays -- 15.2.2 Blocking Assignments with Intra-assignment Delays -- 15.2.3 Non-blocking Assignments with Inter-assignment Delays -- 15.2.4 Non-blocking Assignments with Intra-assignment Delays -- 15.3 Role of Testbenches -- 15.4 Multiple Assignments Within the begin-end -- 15.5 Multiple Assignments Within the fork-join -- 15.6 Display Tasks -- 15.7 Exercises -- 15.8 Summary -- 16 FPGA Architecture and Design Flow -- 16.1 Introduction to PLD -- 16.2 FPGA as Programmable ASIC -- 16.2.1 SRAM Based FPGA -- 16.2.2 Flash Based FPGA -- 16.2.3 Antifuse FPGAS -- 16.2.4 Important FPGA Blocks -- 16.3 FPGA Design Flow -- 16.3.1 Design Entry -- 16.3.2 Design Simulation and Synthesis -- 16.3.3 Design Implementation -- 16.3.4 Device Programming -- 16.4 Logic Realization Using FPGA -- 16.4.1 Configurable Logic Block -- 16.4.2 Input Output Block (IOB) -- 16.4.3 Block RAM. 16.4.4 Digital Clock Manager (DCM) Block. |
| Record Nr. | UNINA-9910743250303321 |
|
Taraate Vaibbhav
|
||
| Singapore : , : Springer, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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OpenMP : enabling massive node-level parallelism : 17th international workshop on OpenMP, IWOMP 2021, Bristol, UK, September 14-16, 2021 : proceedings / / Simon McIntosh-Smith, Bronis R. de Supinski, Jannis Klinkenberg
| OpenMP : enabling massive node-level parallelism : 17th international workshop on OpenMP, IWOMP 2021, Bristol, UK, September 14-16, 2021 : proceedings / / Simon McIntosh-Smith, Bronis R. de Supinski, Jannis Klinkenberg |
| Autore | McIntosh-Smith Simon |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer International Publishing, , [2021] |
| Descrizione fisica | 1 online resource (231 pages) |
| Disciplina | 621.3916 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Microprocessors - Computer-aided design
Logic design - Data processing |
| ISBN | 3-030-85262-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Organization -- Contents -- Synchronization and Data -- Improving Speculative taskloop in Hardware Transactional Memory -- 1 Introduction -- 2 Background and Related Work -- 2.1 Task-Based Parallelism -- 2.2 TLS on Hardware Transactional Memories -- 2.3 Speculative taskloop (STL) -- 2.4 Lost-Thread Effect -- 2.5 LLVM OpenMP Runtime Library -- 3 Implementation -- 3.1 First Attempt: Use priority Clause -- 3.2 Recursive Partition of Iterations -- 3.3 Immediate Execution When Deque is Full -- 3.4 Removal from Tail of Thread's Deque -- 4 Benchmarks, Methodology and Experimental Setup -- 5 Experimental Results and Analysis -- 6 Conclusions -- References -- Vectorized Barrier and Reduction in LLVM OpenMP Runtime -- 1 Introduction -- 2 Background and Related Work -- 2.1 Types of Barriers in Literature -- 2.2 Barriers and Reductions in OpenMP -- 3 Low Overhead Barrier and Reduction in OpenMP -- 3.1 Vectorized Barrier -- 3.2 Vectorized Reduction -- 4 Performance Results -- 4.1 Intel KNL -- 4.2 Fujitsu A64FX -- 5 Conclusions -- References -- Tasking Extensions I -- Enhancing OpenMP Tasking Model: Performance and Portability -- 1 Introduction -- 2 Motivation -- 3 The Taskgraph Model -- 3.1 The taskgraph Mechanism -- 3.2 Syntax of the taskgraph Clause -- 3.3 Semantics of the taskgraph Clause -- 3.4 Requirements of the taskgraph Region -- 4 Projected Results -- 4.1 Potential Performance Gain -- 4.2 The TDG: A Door for Expanding Portability -- 5 Related Work -- 6 Conclusion -- References -- OpenMP Taskloop Dependences -- 1 Introduction -- 2 Tasking Programmability Challenges -- 3 Related Work -- 4 Taskloop with Dependences -- 5 Implementation -- 6 Experiment Results -- 7 Conclusions and Future Work -- References -- Applications -- Outcomes of OpenMP Hackathon: OpenMP Application Experiences with the Offloading Model (Part I).
1 Introduction -- 2 Platforms Used -- 3 Application Experiences -- 3.1 BerkeleyGW -- 3.2 WDMApp -- References -- Outcomes of OpenMP Hackathon: OpenMP Application Experiences with the Offloading Model (Part II) -- 1 Introduction -- 2 Application Experiences -- 2.1 GAMESS -- 2.2 GESTS -- 2.3 GridMini -- 3 Conclusions -- References -- An Empirical Investigation of OpenMP Based Implementation of Simplex Algorithm -- 1 Introduction -- 2 Serial Algorithm -- 3 Parallel Algorithm -- 3.1 Implementation -- 3.2 Optimization Strategies -- 3.3 Algorithm Analysis -- 4 Experimental Results and Observations -- 4.1 NETLIB Dataset -- 4.2 Variation of the Number of Variables -- 4.3 Variation of the Number of Constraints -- 4.4 Variation in Matrix Density -- 4.5 Discussion -- 5 Conclusion -- A Appendix: Serial Algorithm - Working Example -- References -- Task Inefficiency Patterns for a Wave Equation Solver -- 1 Introduction -- 2 Case Studies -- 3 Test Environment -- 4 Benchmarking and Task Runtime Modifications -- 4.1 Direct Translation of Enclave Tasking to OpenMP (native) -- 4.2 Manual Task Postponing (Hold-Back) -- 4.3 Manual Backfilling (Backfill) -- 5 Evaluation and Conclusion -- References -- Case Studies -- Comparing OpenMP Implementations with Applications Across A64FX Platforms -- 1 Introduction -- 1.1 The A64FX Processor -- 1.2 Paper's Contribution and Organization -- 2 List of Applications and Experimental Setup -- 2.1 List of Applications -- 2.2 Systems and Compilers -- 2.3 Runtime Environment -- 2.4 Compiler Options -- 3 Experimental Results -- 3.1 Ookami -- 3.2 Fugaku -- 4 Related Work -- 5 Conclusions and Future Work -- References -- A Case Study of LLVM-Based Analysis for Optimizing SIMD Code Generation -- 1 Introduction -- 2 Case Study: Porting DCA++ to Wombat -- 2.1 Evaluation Environment -- 2.2 DCA++ -- 2.3 Baseline Performance. 3 An LLVM Tool Methodology to Generate Efficient Vectorization -- 3.1 OpenMP SIMD -- 3.2 Using the Correct Compiler Flags -- 3.3 Loop Transformations -- 3.4 Results -- 4 Automating the Process: The OpenMP Advisor -- 5 Related Work -- 6 Conclusion -- References -- Heterogenous Computing and Memory -- Experience Report: Writing a Portable GPU Runtime with OpenMP 5.1 -- 1 Introduction -- 2 Background -- 2.1 Device Runtime Library -- 2.2 Compilation Flow of OpenMP Target Offloading in LLVM/Clang -- 2.3 Motivation -- 3 Implementation -- 3.1 Common Part -- 3.2 Target Specific Part -- 4 Evaluation -- 4.1 Code Comparison -- 4.2 Functional Testing -- 4.3 Performance Evaluation -- 5 Conclusions and Future Work -- References -- FOTV: A Generic Device Offloading Framework for OpenMP -- 1 Introduction -- 2 Background: OpenMP Offloading Infrastructure -- 2.1 Offloading Strategy -- 2.2 Advantages and Limitations -- 3 Architecture of the FOTV Generic Device Framework -- 3.1 The Runtime Library Components -- 3.2 The Code Extraction Tool -- 4 Device Management API Description -- 4.1 DeviceManagement Component -- 4.2 TgtRegionBase Component -- 5 Case Study: Running OpenCL Kernels as OpenMP Regions -- 5.1 The OpenCL Device Requirements -- 6 Results -- 7 Related Works -- 8 Conclusions and Future Works -- References -- Beyond Explicit Transfers: Shared and Managed Memory in OpenMP -- 1 Introduction -- 2 Current Support in OpenMP -- 2.1 Allocators -- 2.2 Host Memory -- 2.3 Device Memory -- 3 Survey -- 3.1 OpenCL -- 3.2 Level Zero -- 3.3 CUDA -- 3.4 HIP -- 4 Proposed OpenMP Extension -- 4.1 Memory Space Accessibility -- 4.2 Shared and Managed Memory -- 4.3 Memory Location Control -- 5 Evaluation -- 6 Conclusion -- References -- Tasking Extensions II -- Communication-Aware Task Scheduling Strategy in Hybrid MPI+OpenMP Applications -- 1 Introduction -- 2 Related Work. 3 Task Scheduling Strategy -- 3.1 Interoperation Between MPI and OpenMP Runtimes -- 3.2 Manual Policies -- 3.3 (Semi-)Automatic Policies -- 3.4 Summary -- 4 Implementation and Evaluation -- 4.1 Implementation -- 4.2 Evaluation Environment -- 4.3 Experimental Results -- 5 Conclusion and Future Work -- References -- An OpenMP Free Agent Threads Implementation -- 1 Introduction -- 2 Related Work -- 3 Proposal -- 3.1 Considered Aspects in the Design -- 3.2 The free_agent Task Clause -- 3.3 Proposed Mechanisms to Manage Free Agent Threads -- 4 Implementation -- 5 Evaluation -- 5.1 Use Case: Fixing Load Imbalance Between Parallel Regions -- 5.2 Use Case: Solving Load Imbalance in a Hybrid Application with DLB as an OMPT Tool -- 6 Conclusions and Future Work -- References -- Author Index. |
| Record Nr. | UNISA-996464509003316 |
|
McIntosh-Smith Simon
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| Cham, Switzerland : , : Springer International Publishing, , [2021] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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VHDL for logic synthesis [[electronic resource] /] / Andrew Rushton
| VHDL for logic synthesis [[electronic resource] /] / Andrew Rushton |
| Autore | Rushton Andrew |
| Edizione | [3rd ed.] |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K., : Wiley, 2011 |
| Descrizione fisica | 1 online resource (486 p.) |
| Disciplina | 621.39/5 |
| Soggetto topico |
VHDL (Computer hardware description language)
Logic design - Data processing Computer-aided design |
| ISBN |
1-119-99573-6
0-470-97797-3 1-283-37389-0 9786613373892 0-470-97792-2 1-119-99585-X |
| Classificazione | COM059000 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
VHDL FOR LOGIC SYNTHESIS; Contents; Preface; List of Figures; List of Tables; 1 Introduction; 1.1 The VHDL Design Cycle; 1.2 The Origins of VHDL; 1.3 The Standardisation Process; 1.4 Unification of VHDL Standards; 1.5 Portability; 2 Register-Transfer Level Design; 2.1 The RTL Design Stages; 2.2 Example Circuit; 2.3 Identify the Data Operations; 2.4 Determine the Data Precision; 2.5 Choose Resources to Provide; 2.6 Allocate Operations to Resources; 2.7 Design the Controller; 2.8 Design the Reset Mechanism; 2.9 VHDL Description of the RTL Design; 2.10 Synthesis Results; 3 Combinational Logic
3.1 Design Units 3.2 Entities and Architectures; 3.3 Simulation Model; 3.4 Synthesis Templates; 3.5 Signals and Ports; 3.6 Initial Values; 3.7 Simple Signal Assignments; 3.8 Conditional Signal Assignments; 3.9 Selected Signal Assignment; 3.10 Worked Example; 4 Basic Types; 4.1 Synthesisable Types; 4.2 Standard Types; 4.3 Standard Operators; 4.4 Type Bit; 4.5 Type Boolean; 4.6 Integer Types; 4.7 Enumeration Types; 4.8 Multi-Valued Logic Types; 4.9 Records; 4.10 Arrays; 4.11 Aggregates, Strings and Bit-Strings; 4.12 Attributes; 4.13 More on Selected Signal Assignments; 5 Operators 5.1 The Standard Operators 5.2 Operator Precedence; 5.3 Boolean Operators; 5.4 Comparison Operators; 5.5 Shifting Operators; 5.6 Arithmetic Operators; 5.7 Concatenation Operator; 6 Synthesis Types; 6.1 Synthesis Type System; 6.2 Making the Packages Visible; 6.3 Logic Types - Std_Logic_1164; 6.4 Numeric Types - Numeric_Std; 6.5 Fixed-Point Types - Fixed_Pkg; 6.6 Floating-Point Types - Float_Pkg; 6.7 Type Conversions; 6.8 Constant Values; 6.9 Mixing Types in Expressions; 6.10 Top-Level Interface; 7 Std_Logic_Arith; 7.1 The Std_Logic_Arith Package; 7.2 Contents of Std_Logic_Arith 7.3 Type Conversions 7.4 Constant Values; 7.5 Mixing Types in Expressions; 8 Sequential VHDL; 8.1 Processes; 8.2 Signal Assignments; 8.3 Variables; 8.4 If Statements; 8.5 Case Statements; 8.6 Latch Inference; 8.7 Loops; 8.8 Worked Example; 9 Registers; 9.1 Basic D-Type Register; 9.2 Simulation Model; 9.3 Synthesis Model; 9.4 Register Templates; 9.5 Register Types; 9.6 Clock Types; 9.7 Clock Gating; 9.8 Data Gating; 9.9 Asynchronous Reset; 9.10 Synchronous Reset; 9.11 Registered Variables; 9.12 Initial Values; 10 Hierarchy; 10.1 The Role of Components; 10.2 Indirect Binding; 10.3 Direct Binding 10.4 Component Packages 10.5 Parameterised Components; 10.6 Generate Statements; 10.7 Worked Examples; 11 Subprograms; 11.1 The Role of Subprograms; 11.2 Functions; 11.3 Operators; 11.4 Type Conversions; 11.5 Procedures; 11.6 Declaring Subprograms; 11.7 Worked Example; 12 Special Structures; 12.1 Tristates; 12.2 Finite State Machines; 12.3 RAMs and Register Banks; 12.4 Decoders and ROMs; 13 Test Benches; 13.1 Test Benches; 13.2 Combinational Test Bench; 13.3 Verifying Responses; 13.4 Clocks and Resets; 13.5 Other Standard Types; 13.6 Don't Care Outputs; 13.7 Printing Response Values 13.8 Using TextIO to Read Data Files |
| Record Nr. | UNINA-9910131027603321 |
|
Rushton Andrew
|
||
| Chichester, West Sussex, U.K., : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
VHDL for logic synthesis / / Andrew Rushton
| VHDL for logic synthesis / / Andrew Rushton |
| Autore | Rushton Andrew |
| Edizione | [3rd ed.] |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K., : Wiley, 2011 |
| Descrizione fisica | 1 online resource (486 p.) |
| Disciplina | 621.39/5 |
| Soggetto topico |
VHDL (Computer hardware description language)
Logic design - Data processing Computer-aided design |
| ISBN |
9786613373892
9781119995739 1119995736 9780470977972 0470977973 9781283373890 1283373890 9780470977927 0470977922 9781119995852 111999585X |
| Classificazione | COM059000 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
VHDL FOR LOGIC SYNTHESIS; Contents; Preface; List of Figures; List of Tables; 1 Introduction; 1.1 The VHDL Design Cycle; 1.2 The Origins of VHDL; 1.3 The Standardisation Process; 1.4 Unification of VHDL Standards; 1.5 Portability; 2 Register-Transfer Level Design; 2.1 The RTL Design Stages; 2.2 Example Circuit; 2.3 Identify the Data Operations; 2.4 Determine the Data Precision; 2.5 Choose Resources to Provide; 2.6 Allocate Operations to Resources; 2.7 Design the Controller; 2.8 Design the Reset Mechanism; 2.9 VHDL Description of the RTL Design; 2.10 Synthesis Results; 3 Combinational Logic
3.1 Design Units 3.2 Entities and Architectures; 3.3 Simulation Model; 3.4 Synthesis Templates; 3.5 Signals and Ports; 3.6 Initial Values; 3.7 Simple Signal Assignments; 3.8 Conditional Signal Assignments; 3.9 Selected Signal Assignment; 3.10 Worked Example; 4 Basic Types; 4.1 Synthesisable Types; 4.2 Standard Types; 4.3 Standard Operators; 4.4 Type Bit; 4.5 Type Boolean; 4.6 Integer Types; 4.7 Enumeration Types; 4.8 Multi-Valued Logic Types; 4.9 Records; 4.10 Arrays; 4.11 Aggregates, Strings and Bit-Strings; 4.12 Attributes; 4.13 More on Selected Signal Assignments; 5 Operators 5.1 The Standard Operators 5.2 Operator Precedence; 5.3 Boolean Operators; 5.4 Comparison Operators; 5.5 Shifting Operators; 5.6 Arithmetic Operators; 5.7 Concatenation Operator; 6 Synthesis Types; 6.1 Synthesis Type System; 6.2 Making the Packages Visible; 6.3 Logic Types - Std_Logic_1164; 6.4 Numeric Types - Numeric_Std; 6.5 Fixed-Point Types - Fixed_Pkg; 6.6 Floating-Point Types - Float_Pkg; 6.7 Type Conversions; 6.8 Constant Values; 6.9 Mixing Types in Expressions; 6.10 Top-Level Interface; 7 Std_Logic_Arith; 7.1 The Std_Logic_Arith Package; 7.2 Contents of Std_Logic_Arith 7.3 Type Conversions 7.4 Constant Values; 7.5 Mixing Types in Expressions; 8 Sequential VHDL; 8.1 Processes; 8.2 Signal Assignments; 8.3 Variables; 8.4 If Statements; 8.5 Case Statements; 8.6 Latch Inference; 8.7 Loops; 8.8 Worked Example; 9 Registers; 9.1 Basic D-Type Register; 9.2 Simulation Model; 9.3 Synthesis Model; 9.4 Register Templates; 9.5 Register Types; 9.6 Clock Types; 9.7 Clock Gating; 9.8 Data Gating; 9.9 Asynchronous Reset; 9.10 Synchronous Reset; 9.11 Registered Variables; 9.12 Initial Values; 10 Hierarchy; 10.1 The Role of Components; 10.2 Indirect Binding; 10.3 Direct Binding 10.4 Component Packages 10.5 Parameterised Components; 10.6 Generate Statements; 10.7 Worked Examples; 11 Subprograms; 11.1 The Role of Subprograms; 11.2 Functions; 11.3 Operators; 11.4 Type Conversions; 11.5 Procedures; 11.6 Declaring Subprograms; 11.7 Worked Example; 12 Special Structures; 12.1 Tristates; 12.2 Finite State Machines; 12.3 RAMs and Register Banks; 12.4 Decoders and ROMs; 13 Test Benches; 13.1 Test Benches; 13.2 Combinational Test Bench; 13.3 Verifying Responses; 13.4 Clocks and Resets; 13.5 Other Standard Types; 13.6 Don't Care Outputs; 13.7 Printing Response Values 13.8 Using TextIO to Read Data Files |
| Altri titoli varianti | VHSIC Hardware Description Language for logic synthesis |
| Record Nr. | UNINA-9910809174903321 |
|
Rushton Andrew
|
||
| Chichester, West Sussex, U.K., : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
