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Accelerator Programming Using Directives [[electronic resource] ] : 6th International Workshop, WACCPD 2019, Denver, CO, USA, November 18, 2019, Revised Selected Papers / / edited by Sandra Wienke, Sridutt Bhalachandra
Accelerator Programming Using Directives [[electronic resource] ] : 6th International Workshop, WACCPD 2019, Denver, CO, USA, November 18, 2019, Revised Selected Papers / / edited by Sandra Wienke, Sridutt Bhalachandra
Edizione [1st ed. 2020.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020
Descrizione fisica 1 online resource (170 pages)
Disciplina 005.1
Collana Programming and Software Engineering
Soggetto topico Programming languages (Electronic computers)
Computer organization
Microprogramming 
Input-output equipment (Computers)
Logic design
Programming Languages, Compilers, Interpreters
Computer Systems Organization and Communication Networks
Control Structures and Microprogramming
Input/Output and Data Communications
Logic Design
ISBN 3-030-49943-X
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNISA-996418304403316
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Accelerator Programming Using Directives : 6th International Workshop, WACCPD 2019, Denver, CO, USA, November 18, 2019, Revised Selected Papers / / edited by Sandra Wienke, Sridutt Bhalachandra
Accelerator Programming Using Directives : 6th International Workshop, WACCPD 2019, Denver, CO, USA, November 18, 2019, Revised Selected Papers / / edited by Sandra Wienke, Sridutt Bhalachandra
Edizione [1st ed. 2020.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020
Descrizione fisica 1 online resource (170 pages)
Disciplina 005.1
005.13
Collana Programming and Software Engineering
Soggetto topico Programming languages (Electronic computers)
Computer organization
Microprogramming 
Input-output equipment (Computers)
Logic design
Programming Languages, Compilers, Interpreters
Computer Systems Organization and Communication Networks
Control Structures and Microprogramming
Input/Output and Data Communications
Logic Design
ISBN 3-030-49943-X
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9910409662003321
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Accelerator Programming Using Directives [[electronic resource] ] : 5th International Workshop, WACCPD 2018, Dallas, TX, USA, November 11-17, 2018, Proceedings / / edited by Sunita Chandrasekaran, Guido Juckeland, Sandra Wienke
Accelerator Programming Using Directives [[electronic resource] ] : 5th International Workshop, WACCPD 2018, Dallas, TX, USA, November 11-17, 2018, Proceedings / / edited by Sunita Chandrasekaran, Guido Juckeland, Sandra Wienke
Edizione [1st ed. 2019.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019
Descrizione fisica 1 online resource (IX, 137 p. 61 illus., 43 illus. in color.)
Disciplina 001.642
Collana Programming and Software Engineering
Soggetto topico Programming languages (Electronic computers)
Logic design
Input-output equipment (Computers)
Microprogramming 
Computer organization
Programming Languages, Compilers, Interpreters
Logic Design
Input/Output and Data Communications
Control Structures and Microprogramming
Computer Systems Organization and Communication Networks
ISBN 3-030-12274-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNISA-996466464703316
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Accelerator Programming Using Directives : 5th International Workshop, WACCPD 2018, Dallas, TX, USA, November 11-17, 2018, Proceedings / / edited by Sunita Chandrasekaran, Guido Juckeland, Sandra Wienke
Accelerator Programming Using Directives : 5th International Workshop, WACCPD 2018, Dallas, TX, USA, November 11-17, 2018, Proceedings / / edited by Sunita Chandrasekaran, Guido Juckeland, Sandra Wienke
Edizione [1st ed. 2019.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019
Descrizione fisica 1 online resource (IX, 137 p. 61 illus., 43 illus. in color.)
Disciplina 001.642
005.13
Collana Programming and Software Engineering
Soggetto topico Programming languages (Electronic computers)
Logic design
Input-output equipment (Computers)
Microprogramming 
Computer organization
Programming Languages, Compilers, Interpreters
Logic Design
Input/Output and Data Communications
Control Structures and Microprogramming
Computer Systems Organization and Communication Networks
ISBN 3-030-12274-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9910337577103321
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Accelerator Programming Using Directives [[electronic resource] ] : 4th International Workshop, WACCPD 2017, Held in Conjunction with the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2017, Denver, CO, USA, November 13, 2017, Proceedings / / edited by Sunita Chandrasekaran, Guido Juckeland
Accelerator Programming Using Directives [[electronic resource] ] : 4th International Workshop, WACCPD 2017, Held in Conjunction with the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2017, Denver, CO, USA, November 13, 2017, Proceedings / / edited by Sunita Chandrasekaran, Guido Juckeland
Edizione [1st ed. 2018.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018
Descrizione fisica 1 online resource (IX, 183 p. 59 illus.)
Disciplina 004.3
Collana Programming and Software Engineering
Soggetto topico Programming languages (Electronic computers)
Logic design
Operating systems (Computers)
Computer programming
Computer organization
Computers
Programming Languages, Compilers, Interpreters
Logic Design
Operating Systems
Programming Techniques
Computer Systems Organization and Communication Networks
Models and Principles
ISBN 3-319-74896-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Intro -- Preface -- Organization -- Contents -- Applications -- An Example of Porting PETSc Applications to Heterogeneous Platforms with OpenACC -- Abstract -- 1 Introduction -- 2 Workflow and System Description -- 2.1 Workflow -- 2.2 System -- 3 Results and Discussion -- 3.1 Profiling with Score-P -- 3.2 The Most Expensive Kernel: MatMult_SeqAIJ -- 3.3 Four Steps Toward the Final Version of OpenACC Kernel -- 4 Speedups and Strong Scaling -- 5 Conclusion -- Acknowledgement -- References -- Hybrid Fortran: High Productivity GPU Porting Framework Applied to Japanese Weather Prediction Model -- 1 Introduction -- 1.1 ASUCA on GPU -- 1.2 Parallelization Granularity -- 1.3 Memory Layout -- 1.4 Related Work -- 1.5 Problem Summary -- 2 Hybrid Fortran Language Extension and Code Transformation -- 2.1 Parallel Loop Abstraction -- 2.2 Compile-Time Defined Memory Layout and Device Data Region -- 2.3 Transformed Code -- 3 Code Transformation Method -- 4 Productivity- and Performance Results -- 5 Conclusion and Future Work -- References -- Implicit Low-Order Unstructured Finite-Element Multiple Simulation Enhanced by Dense Computation Using OpenACC -- 1 Introduction -- 2 Finite-Element Earthquake Simulation Designed for the K Computer -- 3 Proposed Solver for GPUs Using OpenACC -- 3.1 Modification of Algorithm for GPUs -- 3.2 Introduction of OpenACC -- 4 Performance Measurements -- 5 Application Example -- 6 Concluding Remarks -- References -- Runtime Environments -- The Design and Implementation of OpenMP 4.5 and OpenACC Backends for the RAJA C++ Performance Portability Layer -- 1 Introduction -- 2 RAJA -- 2.1 Basic Execution Policies -- 2.2 RAJA::NestedPolicy and Loop Transformations -- 3 Embedding Directives in the C++ Type System -- 3.1 Defining Policy Tags for a Backend -- 3.2 Constructing Explicit Execution Policy Types.
3.3 Implement forall Specializations -- 4 Case Study: OpenMP 4.5 -- 5 Case Study: OpenACC -- 6 Evaluation -- 6.1 Test Set -- 6.2 Goals and Non-Goals -- 6.3 Compilation Overhead -- 6.4 Runtime Overhead -- 7 Future Work and Conclusion -- References -- Enabling GPU Support for the COMPSs-Mobile Framework -- 1 Introduction -- 2 Related Work -- 3 Programming Model -- 3.1 Extension for GPU Support -- 4 Runtime Support Implementation -- 4.1 COMPSs-Mobile Runtime Architecture -- 4.2 OpenCL Platform -- 5 Performance Evaluation -- 5.1 OpenCL Platform Performance -- 5.2 Load Balancing Policies -- 6 Conclusions and Future Work -- References -- Concurrent Parallel Processing on Graphics and Multicore Processors with OpenACC and OpenMP -- Abstract -- 1 Introduction -- 2 MBFLO3 Application -- 2.1 Mathematical Formulation -- 2.2 Numerical Method -- 3 Heterogeneous Multiblock Computing Strategy -- 3.1 Multicore Host Parallelism -- 3.2 Manycore Accelerator Parallelism -- 3.3 Heterogeneous Host-Device Parallelism -- 4 Performance Results and Analysis -- 5 Conclusions -- Acknowledgements -- References -- Program Evaluation -- Exploration of Supervised Machine Learning Techniques for Runtime Selection of CPU vs. GPU Execution in Java Programs -- 1 Introduction -- 2 Motivation -- 3 Compiling Java to GPUs -- 3.1 Java Parallel Stream API -- 3.2 JIT Compilation for GPUs -- 4 Exploring Supervised Machine Learning Algorithms -- 4.1 Supervised Machine Learning -- 4.2 Generating Subsets of Features -- 4.3 Constructing Prediction Models -- 4.4 Integrating Prediction Models -- 5 Experimental Results -- 5.1 Experimental Protocol -- 5.2 Overall Summary -- 5.3 Accuracies on the Full Set of Features -- 5.4 Exploring ML Algorithms by Feature Subsetting -- 5.5 Lessons Learned -- 6 Related Work -- 6.1 GPU Code Generation from High-Level Languages -- 6.2 Offline Model Construction.
7 Conclusions -- A Appendix -- References -- Automatic Testing of OpenACC Applications -- 1 Introduction -- 2 Testing a GPU Port of a Numerical Application -- 3 Autocompare with OpenACC -- 4 Autocompare Implementation -- 5 Experiments -- 6 Related Work -- 7 Future Work -- 8 Conclusion -- References -- Evaluation of Asynchronous Offloading Capabilities of Accelerator Programming Models for Multiple Devices -- 1 Introduction -- 2 Related Work -- 3 Accelerator Programming Models -- 3.1 CUDA -- 3.2 OpenCL -- 3.3 OpenACC -- 3.4 OpenMP -- 4 Implementing the Conjugate Gradient Method -- 5 Performance Results on NVIDIA GPUs -- 5.1 Data Transfers with the Host -- 5.2 Single Device -- 5.3 Two Devices -- 6 Performance Results on Intel Xeon Phi Coprocessors -- 6.1 Single Device -- 6.2 Two Devices -- 7 Summary -- References -- Author Index.
Record Nr. UNISA-996465474703316
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Accelerator Programming Using Directives : 4th International Workshop, WACCPD 2017, Held in Conjunction with the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2017, Denver, CO, USA, November 13, 2017, Proceedings / / edited by Sunita Chandrasekaran, Guido Juckeland
Accelerator Programming Using Directives : 4th International Workshop, WACCPD 2017, Held in Conjunction with the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2017, Denver, CO, USA, November 13, 2017, Proceedings / / edited by Sunita Chandrasekaran, Guido Juckeland
Edizione [1st ed. 2018.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018
Descrizione fisica 1 online resource (IX, 183 p. 59 illus.)
Disciplina 004.3
Collana Programming and Software Engineering
Soggetto topico Programming languages (Electronic computers)
Logic design
Operating systems (Computers)
Computer programming
Computer organization
Computers
Programming Languages, Compilers, Interpreters
Logic Design
Operating Systems
Programming Techniques
Computer Systems Organization and Communication Networks
Models and Principles
ISBN 3-319-74896-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Intro -- Preface -- Organization -- Contents -- Applications -- An Example of Porting PETSc Applications to Heterogeneous Platforms with OpenACC -- Abstract -- 1 Introduction -- 2 Workflow and System Description -- 2.1 Workflow -- 2.2 System -- 3 Results and Discussion -- 3.1 Profiling with Score-P -- 3.2 The Most Expensive Kernel: MatMult_SeqAIJ -- 3.3 Four Steps Toward the Final Version of OpenACC Kernel -- 4 Speedups and Strong Scaling -- 5 Conclusion -- Acknowledgement -- References -- Hybrid Fortran: High Productivity GPU Porting Framework Applied to Japanese Weather Prediction Model -- 1 Introduction -- 1.1 ASUCA on GPU -- 1.2 Parallelization Granularity -- 1.3 Memory Layout -- 1.4 Related Work -- 1.5 Problem Summary -- 2 Hybrid Fortran Language Extension and Code Transformation -- 2.1 Parallel Loop Abstraction -- 2.2 Compile-Time Defined Memory Layout and Device Data Region -- 2.3 Transformed Code -- 3 Code Transformation Method -- 4 Productivity- and Performance Results -- 5 Conclusion and Future Work -- References -- Implicit Low-Order Unstructured Finite-Element Multiple Simulation Enhanced by Dense Computation Using OpenACC -- 1 Introduction -- 2 Finite-Element Earthquake Simulation Designed for the K Computer -- 3 Proposed Solver for GPUs Using OpenACC -- 3.1 Modification of Algorithm for GPUs -- 3.2 Introduction of OpenACC -- 4 Performance Measurements -- 5 Application Example -- 6 Concluding Remarks -- References -- Runtime Environments -- The Design and Implementation of OpenMP 4.5 and OpenACC Backends for the RAJA C++ Performance Portability Layer -- 1 Introduction -- 2 RAJA -- 2.1 Basic Execution Policies -- 2.2 RAJA::NestedPolicy and Loop Transformations -- 3 Embedding Directives in the C++ Type System -- 3.1 Defining Policy Tags for a Backend -- 3.2 Constructing Explicit Execution Policy Types.
3.3 Implement forall Specializations -- 4 Case Study: OpenMP 4.5 -- 5 Case Study: OpenACC -- 6 Evaluation -- 6.1 Test Set -- 6.2 Goals and Non-Goals -- 6.3 Compilation Overhead -- 6.4 Runtime Overhead -- 7 Future Work and Conclusion -- References -- Enabling GPU Support for the COMPSs-Mobile Framework -- 1 Introduction -- 2 Related Work -- 3 Programming Model -- 3.1 Extension for GPU Support -- 4 Runtime Support Implementation -- 4.1 COMPSs-Mobile Runtime Architecture -- 4.2 OpenCL Platform -- 5 Performance Evaluation -- 5.1 OpenCL Platform Performance -- 5.2 Load Balancing Policies -- 6 Conclusions and Future Work -- References -- Concurrent Parallel Processing on Graphics and Multicore Processors with OpenACC and OpenMP -- Abstract -- 1 Introduction -- 2 MBFLO3 Application -- 2.1 Mathematical Formulation -- 2.2 Numerical Method -- 3 Heterogeneous Multiblock Computing Strategy -- 3.1 Multicore Host Parallelism -- 3.2 Manycore Accelerator Parallelism -- 3.3 Heterogeneous Host-Device Parallelism -- 4 Performance Results and Analysis -- 5 Conclusions -- Acknowledgements -- References -- Program Evaluation -- Exploration of Supervised Machine Learning Techniques for Runtime Selection of CPU vs. GPU Execution in Java Programs -- 1 Introduction -- 2 Motivation -- 3 Compiling Java to GPUs -- 3.1 Java Parallel Stream API -- 3.2 JIT Compilation for GPUs -- 4 Exploring Supervised Machine Learning Algorithms -- 4.1 Supervised Machine Learning -- 4.2 Generating Subsets of Features -- 4.3 Constructing Prediction Models -- 4.4 Integrating Prediction Models -- 5 Experimental Results -- 5.1 Experimental Protocol -- 5.2 Overall Summary -- 5.3 Accuracies on the Full Set of Features -- 5.4 Exploring ML Algorithms by Feature Subsetting -- 5.5 Lessons Learned -- 6 Related Work -- 6.1 GPU Code Generation from High-Level Languages -- 6.2 Offline Model Construction.
7 Conclusions -- A Appendix -- References -- Automatic Testing of OpenACC Applications -- 1 Introduction -- 2 Testing a GPU Port of a Numerical Application -- 3 Autocompare with OpenACC -- 4 Autocompare Implementation -- 5 Experiments -- 6 Related Work -- 7 Future Work -- 8 Conclusion -- References -- Evaluation of Asynchronous Offloading Capabilities of Accelerator Programming Models for Multiple Devices -- 1 Introduction -- 2 Related Work -- 3 Accelerator Programming Models -- 3.1 CUDA -- 3.2 OpenCL -- 3.3 OpenACC -- 3.4 OpenMP -- 4 Implementing the Conjugate Gradient Method -- 5 Performance Results on NVIDIA GPUs -- 5.1 Data Transfers with the Host -- 5.2 Single Device -- 5.3 Two Devices -- 6 Performance Results on Intel Xeon Phi Coprocessors -- 6.1 Single Device -- 6.2 Two Devices -- 7 Summary -- References -- Author Index.
Record Nr. UNINA-9910349261003321
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Active Object Languages: Current Research Trends / / edited by Frank de Boer, Ferruccio Damiani, Reiner Hähnle, Einar Broch Johnsen, Eduard Kamburjan
Active Object Languages: Current Research Trends / / edited by Frank de Boer, Ferruccio Damiani, Reiner Hähnle, Einar Broch Johnsen, Eduard Kamburjan
Edizione [1st ed. 2024.]
Pubbl/distr/stampa Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024
Descrizione fisica 1 online resource (382 pages)
Disciplina 005.4
Collana Lecture Notes in Computer Science
Soggetto topico Computer programming
Microprogramming
Computer input-output equipment
Logic design
Computer networks
Microprocessors
Computer architecture
Programming Techniques
Control Structures and Microprogramming
Input/Output and Data Communications
Logic Design
Computer Communication Networks
Processor Architectures
ISBN 3-031-51060-7
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Active Objects based on Algebraic Effects -- Actor-based Designs for Distributed Self-organisation Programming -- Encore: Coda -- Bridging Between Active Objects: Multitier Programming for Distributed, Concurrent Systems -- A Survey of Actor-Like Programming Models for Serverless Computing -- Programming Language Implementations with Multiparty Session Types -- Modelling -- Integrated Timed Architectural Modeling/Execution Language -- Simulating User Journeys with Active Objects -- Actors Upgraded for Variability, Adaptability, and Determinism -- Analysis -- Integrating Data Privacy Compliance in Active Object Languages -- Context-aware Trace Contracts -- Type-Based Verification of Delegated Control in Hybrid Systems -- Enforced Dependencies for Active Objects.
Record Nr. UNINA-9910806197803321
Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Advanced Boolean Techniques : Selected Papers from the 13th International Workshop on Boolean Problems / / edited by Rolf Drechsler, Mathias Soeken
Advanced Boolean Techniques : Selected Papers from the 13th International Workshop on Boolean Problems / / edited by Rolf Drechsler, Mathias Soeken
Edizione [1st ed. 2020.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020
Descrizione fisica 1 online resource (268 pages)
Disciplina 511.324
Soggetto topico Electronic circuits
Logic design
Electronics
Microelectronics
Circuits and Systems
Logic Design
Electronics and Microelectronics, Instrumentation
ISBN 3-030-20323-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Chapter 1. Self-Explaining Digital Systems: Technical View, Implementation Aspects, and Completeness -- Chapter 2.Secure Implementation of Lattice-Based Encryption Schemes -- Chapter 3. Derivative Operations for Classes CN of Boolean Functions -- Chapter 4.Towards the Structure of a Class of Permutation Matrices Associated With Bent Functions -- Chapter 5. Improving SAT Solving Using
Monte Carlo Tree Search-based Clause Learning -- Chapter 6.Synthesis of Majority Expressions through Primitive Function Manipulation -- Chapter 7. Literal Selection in Switching Lattice Design -- Chapter 8. Exact Synthesis of ESOP Forms -- Chapter 9.An Algorithm for Linear, Affine and Spectral Classification of Boolean Functions -- Chapter 10.New Results on Reversible Boolean Functions Having Component Functions with Specified Properties -- Chapter 11. Efficient hardware operations for the residue number system by Boolean minimization.
Record Nr. UNINA-9910366584903321
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Advanced Computer Architecture : 12th Conference, ACA 2018, Yingkou, China, August 10-11, 2018, Proceedings / / edited by Chao Li, Junjie Wu
Advanced Computer Architecture : 12th Conference, ACA 2018, Yingkou, China, August 10-11, 2018, Proceedings / / edited by Chao Li, Junjie Wu
Edizione [1st ed. 2018.]
Pubbl/distr/stampa Singapore : , : Springer Singapore : , : Imprint : Springer, , 2018
Descrizione fisica 1 online resource (X, 233 p. 126 illus.)
Disciplina 004
Collana Communications in Computer and Information Science
Soggetto topico Microprocessors
Special purpose computers
Architecture, Computer
Operating systems (Computers)
Logic design
Processor Architectures
Special Purpose and Application-Based Systems
Computer System Implementation
Operating Systems
Logic Design
ISBN 981-13-2423-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9910299298003321
Singapore : , : Springer Singapore : , : Imprint : Springer, , 2018
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog / / by Vaibbhav Taraate
Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog / / by Vaibbhav Taraate
Autore Taraate Vaibbhav
Edizione [1st ed. 2019.]
Pubbl/distr/stampa Singapore : , : Springer Singapore : , : Imprint : Springer, , 2019
Descrizione fisica 1 online resource (xxi, 307 pages)
Disciplina 621.3815
Soggetto topico Electronic circuits
Microprogramming 
Logic design
Circuits and Systems
Control Structures and Microprogramming
Logic Design
ISBN 981-10-8776-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level.
Record Nr. UNINA-9910337620903321
Taraate Vaibbhav  
Singapore : , : Springer Singapore : , : Imprint : Springer, , 2019
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui