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Demystifying chipmaking [[electronic resource] /] / by Richard F. Yanda, Michael Heynes and Anne K. Miller
| Demystifying chipmaking [[electronic resource] /] / by Richard F. Yanda, Michael Heynes and Anne K. Miller |
| Autore | Yanda Richard F |
| Pubbl/distr/stampa | Oxford, : Newnes |
| Descrizione fisica | 1 online resource (276 p.) |
| Disciplina | 621.39732 |
| Altri autori (Persone) |
HeynesMichael
MillerAnne K |
| Soggetto topico |
Logic circuits - Design and construction
Metal oxide semiconductors, Complementary |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-00979-2
9786611009793 0-08-047709-7 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Contents; Foreword; Acknowledgments; About the Authors; Chapter 1: IC Fabrication Overview; Section 1: Introduction; 1.1 Integrated Circuits; 1.2 The Semiconductor Industry; Section 2: Support Technologies; 2.1 Crystal Growth and Wafer Preparation; 2.2 Contamination Control; 2.3 Circuit Design and Mask Making; 2.4 Process Diagnostics and Metrology; Section 3: Integrated Circuit Fabrication; 3.1 Layering; 3.2 Patterning; 3.3 Doping; 3.4 Process Control and In-line Monitoring; Section 4: Test and Assembly; 4.1 Electrical Tests; 4.2 Die Separation; 4.3 Die Attach and Wire Bonding
4.4 Encapsulation4.5 Final Test; Section 5: Summary; Chapter 2: Support Technologies; Section 1: Introduction; Section 2: Contamination Control; 2.1 Why Control Contamination?; 2.2 Contamination Sources; 2.3 The Cleanroom; Section 3: Crystal Growth and Wafer Preparation; 3.1 Introduction; 3.2 Silicon Purification; 3.3 Czochralski Silicon Growth; 3.4 Shaping, Grinding, Cutting and Polishing; 3.5 Final Inspection and Shipping; Section 4: Circuit Design; 4.1 Introduction; 4.2 Product Definition and New Product Plan; 4.3 The Design Team; 4.4 The Design Process; 4.5 Design Verification and Tapeout Section 5: Photomask and Reticle Preparation5.1 Introduction; 5.2 Reticle Substrate Preparation; 5.3 Pattern Transfer; 5.4 Inspection and Defect Repair; Chapter 3: Forming Wells; Section 1: Introduction; Section 2: Initial Oxidation; Section 3: Photolithography; 3.1 Introduction; 3.2 Coat (Spin); 3.3 Exposure (Step); 3.4 Develop; 3.5 After Develop Inspect (ADI); Section 4: Ion Implantation; Chapter 4: Isolate Active Areas (Shallow Trench Isolation); Section 1: Introduction to Shallow Trench Isolation; Section 2: Pad Oxide Growth; Section 3: Silicon Nitride Deposition Section 4: Photolithography for Photo/EtchSection 5: Hard Mask Formation Using Plasma Etch; 5.1 Hard Mask Overview; 5.2 Plasma Etch Overview; 5.3 Etch Chemistry: Silicon Dioxide and Silicon Nitride; Section 6: Form Trenches in Silicon with Plasma Etch; Section 7: Fill Trenches with Silicon Dioxide; Section 8: Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide; Section 9: Wet Etch Removal of Silicon Nitride and Pad Oxide; Chapter 5: Building the Transistors; Section 1: Introduction; Section 2: Thin Film Formation; 2.1 Gate Dielectric Oxidation 2.2 Polycrystalline Silicon (Poly) Deposition2.3 Nitride Cap Deposition; Section 3: Poly Gate Formation; 3.1 Photoresist Patterning; 3.2 Plasma Etch; Section 4: Source/Drain Formation; 4.1 Introduction; 4.2 Shallow Implant; 4.3 Spacer Formation; 4.4 High-Dose Implant; 4.5 Anneal; Section 5: Salicide Formation; 5.1 Sputter Cobalt; 5.2 RTP Reaction Forming Silicide; 5.3 Strip Residual Cobalt; 5.4 Anneal the Silicide; Chapter 6: First Level Metallization; Section 1: Introduction; Section 2: Nitride and Oxide Depositions; 2.1 Nitride Deposition; 2.2 Oxide Deposition; Section 3: CMP Planarization Section 4: Photo/Etch for Contact Holes |
| Record Nr. | UNINA-9910457087103321 |
Yanda Richard F
|
||
| Oxford, : Newnes | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Demystifying chipmaking [[electronic resource] /] / by Richard F. Yanda, Michael Heynes and Anne K. Miller
| Demystifying chipmaking [[electronic resource] /] / by Richard F. Yanda, Michael Heynes and Anne K. Miller |
| Autore | Yanda Richard F |
| Pubbl/distr/stampa | Oxford, : Newnes |
| Descrizione fisica | 1 online resource (276 p.) |
| Disciplina | 621.39732 |
| Altri autori (Persone) |
HeynesMichael
MillerAnne K |
| Soggetto topico |
Logic circuits - Design and construction
Metal oxide semiconductors, Complementary |
| ISBN |
1-281-00979-2
9786611009793 0-08-047709-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Contents; Foreword; Acknowledgments; About the Authors; Chapter 1: IC Fabrication Overview; Section 1: Introduction; 1.1 Integrated Circuits; 1.2 The Semiconductor Industry; Section 2: Support Technologies; 2.1 Crystal Growth and Wafer Preparation; 2.2 Contamination Control; 2.3 Circuit Design and Mask Making; 2.4 Process Diagnostics and Metrology; Section 3: Integrated Circuit Fabrication; 3.1 Layering; 3.2 Patterning; 3.3 Doping; 3.4 Process Control and In-line Monitoring; Section 4: Test and Assembly; 4.1 Electrical Tests; 4.2 Die Separation; 4.3 Die Attach and Wire Bonding
4.4 Encapsulation4.5 Final Test; Section 5: Summary; Chapter 2: Support Technologies; Section 1: Introduction; Section 2: Contamination Control; 2.1 Why Control Contamination?; 2.2 Contamination Sources; 2.3 The Cleanroom; Section 3: Crystal Growth and Wafer Preparation; 3.1 Introduction; 3.2 Silicon Purification; 3.3 Czochralski Silicon Growth; 3.4 Shaping, Grinding, Cutting and Polishing; 3.5 Final Inspection and Shipping; Section 4: Circuit Design; 4.1 Introduction; 4.2 Product Definition and New Product Plan; 4.3 The Design Team; 4.4 The Design Process; 4.5 Design Verification and Tapeout Section 5: Photomask and Reticle Preparation5.1 Introduction; 5.2 Reticle Substrate Preparation; 5.3 Pattern Transfer; 5.4 Inspection and Defect Repair; Chapter 3: Forming Wells; Section 1: Introduction; Section 2: Initial Oxidation; Section 3: Photolithography; 3.1 Introduction; 3.2 Coat (Spin); 3.3 Exposure (Step); 3.4 Develop; 3.5 After Develop Inspect (ADI); Section 4: Ion Implantation; Chapter 4: Isolate Active Areas (Shallow Trench Isolation); Section 1: Introduction to Shallow Trench Isolation; Section 2: Pad Oxide Growth; Section 3: Silicon Nitride Deposition Section 4: Photolithography for Photo/EtchSection 5: Hard Mask Formation Using Plasma Etch; 5.1 Hard Mask Overview; 5.2 Plasma Etch Overview; 5.3 Etch Chemistry: Silicon Dioxide and Silicon Nitride; Section 6: Form Trenches in Silicon with Plasma Etch; Section 7: Fill Trenches with Silicon Dioxide; Section 8: Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide; Section 9: Wet Etch Removal of Silicon Nitride and Pad Oxide; Chapter 5: Building the Transistors; Section 1: Introduction; Section 2: Thin Film Formation; 2.1 Gate Dielectric Oxidation 2.2 Polycrystalline Silicon (Poly) Deposition2.3 Nitride Cap Deposition; Section 3: Poly Gate Formation; 3.1 Photoresist Patterning; 3.2 Plasma Etch; Section 4: Source/Drain Formation; 4.1 Introduction; 4.2 Shallow Implant; 4.3 Spacer Formation; 4.4 High-Dose Implant; 4.5 Anneal; Section 5: Salicide Formation; 5.1 Sputter Cobalt; 5.2 RTP Reaction Forming Silicide; 5.3 Strip Residual Cobalt; 5.4 Anneal the Silicide; Chapter 6: First Level Metallization; Section 1: Introduction; Section 2: Nitride and Oxide Depositions; 2.1 Nitride Deposition; 2.2 Oxide Deposition; Section 3: CMP Planarization Section 4: Photo/Etch for Contact Holes |
| Record Nr. | UNINA-9910784359603321 |
|
Yanda Richard F
|
||
| Oxford, : Newnes | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Demystifying chipmaking / / by Richard F. Yanda, Michael Heynes and Anne K. Miller
| Demystifying chipmaking / / by Richard F. Yanda, Michael Heynes and Anne K. Miller |
| Autore | Yanda Richard F |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Oxford, : Newnes |
| Descrizione fisica | 1 online resource (276 p.) |
| Disciplina | 621.39732 |
| Altri autori (Persone) |
HeynesMichael
MillerAnne K |
| Soggetto topico |
Logic circuits - Design and construction
Metal oxide semiconductors, Complementary |
| ISBN |
1-281-00979-2
9786611009793 0-08-047709-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Contents; Foreword; Acknowledgments; About the Authors; Chapter 1: IC Fabrication Overview; Section 1: Introduction; 1.1 Integrated Circuits; 1.2 The Semiconductor Industry; Section 2: Support Technologies; 2.1 Crystal Growth and Wafer Preparation; 2.2 Contamination Control; 2.3 Circuit Design and Mask Making; 2.4 Process Diagnostics and Metrology; Section 3: Integrated Circuit Fabrication; 3.1 Layering; 3.2 Patterning; 3.3 Doping; 3.4 Process Control and In-line Monitoring; Section 4: Test and Assembly; 4.1 Electrical Tests; 4.2 Die Separation; 4.3 Die Attach and Wire Bonding
4.4 Encapsulation4.5 Final Test; Section 5: Summary; Chapter 2: Support Technologies; Section 1: Introduction; Section 2: Contamination Control; 2.1 Why Control Contamination?; 2.2 Contamination Sources; 2.3 The Cleanroom; Section 3: Crystal Growth and Wafer Preparation; 3.1 Introduction; 3.2 Silicon Purification; 3.3 Czochralski Silicon Growth; 3.4 Shaping, Grinding, Cutting and Polishing; 3.5 Final Inspection and Shipping; Section 4: Circuit Design; 4.1 Introduction; 4.2 Product Definition and New Product Plan; 4.3 The Design Team; 4.4 The Design Process; 4.5 Design Verification and Tapeout Section 5: Photomask and Reticle Preparation5.1 Introduction; 5.2 Reticle Substrate Preparation; 5.3 Pattern Transfer; 5.4 Inspection and Defect Repair; Chapter 3: Forming Wells; Section 1: Introduction; Section 2: Initial Oxidation; Section 3: Photolithography; 3.1 Introduction; 3.2 Coat (Spin); 3.3 Exposure (Step); 3.4 Develop; 3.5 After Develop Inspect (ADI); Section 4: Ion Implantation; Chapter 4: Isolate Active Areas (Shallow Trench Isolation); Section 1: Introduction to Shallow Trench Isolation; Section 2: Pad Oxide Growth; Section 3: Silicon Nitride Deposition Section 4: Photolithography for Photo/EtchSection 5: Hard Mask Formation Using Plasma Etch; 5.1 Hard Mask Overview; 5.2 Plasma Etch Overview; 5.3 Etch Chemistry: Silicon Dioxide and Silicon Nitride; Section 6: Form Trenches in Silicon with Plasma Etch; Section 7: Fill Trenches with Silicon Dioxide; Section 8: Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide; Section 9: Wet Etch Removal of Silicon Nitride and Pad Oxide; Chapter 5: Building the Transistors; Section 1: Introduction; Section 2: Thin Film Formation; 2.1 Gate Dielectric Oxidation 2.2 Polycrystalline Silicon (Poly) Deposition2.3 Nitride Cap Deposition; Section 3: Poly Gate Formation; 3.1 Photoresist Patterning; 3.2 Plasma Etch; Section 4: Source/Drain Formation; 4.1 Introduction; 4.2 Shallow Implant; 4.3 Spacer Formation; 4.4 High-Dose Implant; 4.5 Anneal; Section 5: Salicide Formation; 5.1 Sputter Cobalt; 5.2 RTP Reaction Forming Silicide; 5.3 Strip Residual Cobalt; 5.4 Anneal the Silicide; Chapter 6: First Level Metallization; Section 1: Introduction; Section 2: Nitride and Oxide Depositions; 2.1 Nitride Deposition; 2.2 Oxide Deposition; Section 3: CMP Planarization Section 4: Photo/Etch for Contact Holes |
| Record Nr. | UNINA-9910825105903321 |
|
Yanda Richard F
|
||
| Oxford, : Newnes | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Logic Circuit Design : Selected Topics and Methods / / Shimon P. Vingron
| Logic Circuit Design : Selected Topics and Methods / / Shimon P. Vingron |
| Autore | Vingron Shimon P. |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer Nature Switzerland AG, , [2012] |
| Descrizione fisica | 1 online resource (XII, 240 p. 163 illus., 51 illus. in color.) |
| Disciplina | 621.395 |
| Soggetto topico | Logic circuits - Design and construction |
| ISBN | 3-031-40673-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Logic Variables, Logic Formulas, Karnaugh Maps, Reduced Karnaugh Maps -- Tautologies, Propositional Logic -- Canonical and Shegalkin Normal Forms, Minimising Logic Functions, Composition of Circuits -- Theory of Latches, Automata Models, Asynchronous Sequential Circuits, Verifying a Sequential Design -- FBD language for PLC programming. |
| Record Nr. | UNINA-9910766890303321 |
|
Vingron Shimon P.
|
||
| Cham, Switzerland : , : Springer Nature Switzerland AG, , [2012] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Principles of modern digital design [[electronic resource] /] / Parag K. Lala
| Principles of modern digital design [[electronic resource] /] / Parag K. Lala |
| Autore | Lala Parag K. <1948-> |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley-Interscience, c2007 |
| Descrizione fisica | 1 online resource (437 p.) |
| Disciplina |
621.395
621.39732 |
| Soggetto topico |
Logic design
Logic circuits - Design and construction Digital electronics |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-00216-X
9786611002169 0-470-12521-7 0-470-12520-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
PRINCIPLES OF MODERN DIGITAL DESIGN; CONTENTS; Preface; 1 Number Systems and Binary Codes; 1.1 Introduction; 1.2 Decimal Numbers; 1.3 Binary Numbers; 1.3.1 Basic Binary Arithmetic; 1.4 Octal Numbers; 1.5 Hexadecimal Numbers; 1.6 Signed Numbers; 1.6.1 Diminished Radix Complement; 1.6.2 Radix Complement; 1.7 Floating-Point Numbers; 1.8 Binary Encoding; 1.8.1 Weighted Codes; 1.8.2 Nonweighted Codes; Exercises; 2 Fundamental Concepts of Digital Logic; 2.1 Introduction; 2.2 Sets; 2.3 Relations; 2.4 Partitions; 2.5 Graphs; 2.6 Boolean Algebra; 2.7 Boolean Functions
2.8 Derivation and Classification of Boolean Functions2.9 Canonical Forms of Boolean Functions; 2.10 Logic Gates; Exercises; 3 Combinational Logic Design; 3.1 Introduction; 3.2 Minimization of Boolean Expressions; 3.3 Karnaugh Maps; 3.3.1 Don't Care Conditions; 3.3.2 The Complementary Approach; 3.4 Quine-MCCluskey Method; 3.4.1 Simplification of Boolean Function with Don't Cares; 3.5 Cubical Representation of Boolean Functions; 3.5.1 Tautology; 3.5.2 Complementation Using Shannon's Expansion; 3.6 Heuristic Minimization of Logic Circuits; 3.6.1 Expand; 3.6.2 Reduce; 3.6.3 Irredundant 3.6.4 Espresso3.7 Minimization of Multiple-Output Functions; 3.8 NAND-NAND and NOR-NOR Logic; 3.8.1 NAND-NAND Logic; 3.8.2 NOR-NOR Logic; 3.9 Multilevel Logic Design; 3.9.1 Algebraic and Boolean Division; 3.9.2 Kernels; 3.10 Minimization of Multilevel Circuits Using Don't Cares; 3.10.1 Satisfiability Don't Cares; 3.10.2 Observability Don't Cares; 3.11 Combinational Logic Implementation Using EX-OR and AND Gates; 3.12 Logic Circuit Design Using Multiplexers and Decoders; 3.12.1 Multiplexers; 3.12.2 Demultiplexers and Decoders; 3.13 Arithmetic Circuits; 3.13.1 Half-Adders; 3.13.2 Full Adders 3.13.3 Carry-Lookahead Adders3.13.4 Carry-Select Adder; 3.13.5 Carry-Save Addition; 3.13.6 BCD Adders; 3.13.7 Half-Subtractors; 3.13.8 Full Subtractors; 3.13.9 Two's Complement Subtractors; 3.13.10 BCD Substractors; 3.13.11 Multiplication; 3.13.12 Comparator; 3.14 Combinational Circuit Design Using PLDs; 3.14.1 PROM; 3.14.2 PLA; 3.14.3 PAL; Exercises; References; 4 Fundamentals of Synchronous Sequential Circuits; 4.1 Introduction; 4.2 Synchronous and Asynchronous Operation; 4.3 Latches; 4.4 Flip-Flops; 4.4.1 D Flip-Flop; 4.4.2 JK Flip-Flop; 4.4.3 T Flip-Flop 4.5 Timing in Synchronous Sequential Circuits4.6 State Tables and State Diagrams; 4.7 Mealy and Moore Models; 4.8 Analysis of Synchronous Sequential Circuits; Exercises; References; 5 VHDL in Digital Design; 5.1 Introduction; 5.2 Entity and Architecture; 5.2.1 Entity; 5.2.2 Architecture; 5.3 Lexical Elements in VHDL; 5.4 Data Types; 5.5 Operators; 5.6 Concurrent and Sequential Statements; 5.7 Architecture Description; 5.8 Structural Description; 5.9 Behavioral Description; 5.10 RTL Description; Exercises; 6 Combinational Logic Design Using VHDL; 6.1 Introduction 6.2 Concurrent Assignment Statements |
| Record Nr. | UNINA-9910144576903321 |
|
Lala Parag K. <1948->
|
||
| Hoboken, N.J., : Wiley-Interscience, c2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Principles of modern digital design [[electronic resource] /] / Parag K. Lala
| Principles of modern digital design [[electronic resource] /] / Parag K. Lala |
| Autore | Lala Parag K. <1948-> |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley-Interscience, c2007 |
| Descrizione fisica | 1 online resource (437 p.) |
| Disciplina |
621.395
621.39732 |
| Soggetto topico |
Logic design
Logic circuits - Design and construction Digital electronics |
| ISBN |
1-281-00216-X
9786611002169 0-470-12521-7 0-470-12520-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
PRINCIPLES OF MODERN DIGITAL DESIGN; CONTENTS; Preface; 1 Number Systems and Binary Codes; 1.1 Introduction; 1.2 Decimal Numbers; 1.3 Binary Numbers; 1.3.1 Basic Binary Arithmetic; 1.4 Octal Numbers; 1.5 Hexadecimal Numbers; 1.6 Signed Numbers; 1.6.1 Diminished Radix Complement; 1.6.2 Radix Complement; 1.7 Floating-Point Numbers; 1.8 Binary Encoding; 1.8.1 Weighted Codes; 1.8.2 Nonweighted Codes; Exercises; 2 Fundamental Concepts of Digital Logic; 2.1 Introduction; 2.2 Sets; 2.3 Relations; 2.4 Partitions; 2.5 Graphs; 2.6 Boolean Algebra; 2.7 Boolean Functions
2.8 Derivation and Classification of Boolean Functions2.9 Canonical Forms of Boolean Functions; 2.10 Logic Gates; Exercises; 3 Combinational Logic Design; 3.1 Introduction; 3.2 Minimization of Boolean Expressions; 3.3 Karnaugh Maps; 3.3.1 Don't Care Conditions; 3.3.2 The Complementary Approach; 3.4 Quine-MCCluskey Method; 3.4.1 Simplification of Boolean Function with Don't Cares; 3.5 Cubical Representation of Boolean Functions; 3.5.1 Tautology; 3.5.2 Complementation Using Shannon's Expansion; 3.6 Heuristic Minimization of Logic Circuits; 3.6.1 Expand; 3.6.2 Reduce; 3.6.3 Irredundant 3.6.4 Espresso3.7 Minimization of Multiple-Output Functions; 3.8 NAND-NAND and NOR-NOR Logic; 3.8.1 NAND-NAND Logic; 3.8.2 NOR-NOR Logic; 3.9 Multilevel Logic Design; 3.9.1 Algebraic and Boolean Division; 3.9.2 Kernels; 3.10 Minimization of Multilevel Circuits Using Don't Cares; 3.10.1 Satisfiability Don't Cares; 3.10.2 Observability Don't Cares; 3.11 Combinational Logic Implementation Using EX-OR and AND Gates; 3.12 Logic Circuit Design Using Multiplexers and Decoders; 3.12.1 Multiplexers; 3.12.2 Demultiplexers and Decoders; 3.13 Arithmetic Circuits; 3.13.1 Half-Adders; 3.13.2 Full Adders 3.13.3 Carry-Lookahead Adders3.13.4 Carry-Select Adder; 3.13.5 Carry-Save Addition; 3.13.6 BCD Adders; 3.13.7 Half-Subtractors; 3.13.8 Full Subtractors; 3.13.9 Two's Complement Subtractors; 3.13.10 BCD Substractors; 3.13.11 Multiplication; 3.13.12 Comparator; 3.14 Combinational Circuit Design Using PLDs; 3.14.1 PROM; 3.14.2 PLA; 3.14.3 PAL; Exercises; References; 4 Fundamentals of Synchronous Sequential Circuits; 4.1 Introduction; 4.2 Synchronous and Asynchronous Operation; 4.3 Latches; 4.4 Flip-Flops; 4.4.1 D Flip-Flop; 4.4.2 JK Flip-Flop; 4.4.3 T Flip-Flop 4.5 Timing in Synchronous Sequential Circuits4.6 State Tables and State Diagrams; 4.7 Mealy and Moore Models; 4.8 Analysis of Synchronous Sequential Circuits; Exercises; References; 5 VHDL in Digital Design; 5.1 Introduction; 5.2 Entity and Architecture; 5.2.1 Entity; 5.2.2 Architecture; 5.3 Lexical Elements in VHDL; 5.4 Data Types; 5.5 Operators; 5.6 Concurrent and Sequential Statements; 5.7 Architecture Description; 5.8 Structural Description; 5.9 Behavioral Description; 5.10 RTL Description; Exercises; 6 Combinational Logic Design Using VHDL; 6.1 Introduction 6.2 Concurrent Assignment Statements |
| Record Nr. | UNINA-9910830744803321 |
|
Lala Parag K. <1948->
|
||
| Hoboken, N.J., : Wiley-Interscience, c2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Principles of modern digital design / / Parag K. Lala
| Principles of modern digital design / / Parag K. Lala |
| Autore | Lala Parag K. <1948-> |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley-Interscience, c2007 |
| Descrizione fisica | 1 online resource (437 p.) |
| Disciplina | 621.39/5 |
| Soggetto topico |
Logic design
Logic circuits - Design and construction Digital electronics |
| ISBN |
1-281-00216-X
9786611002169 0-470-12521-7 0-470-12520-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
PRINCIPLES OF MODERN DIGITAL DESIGN; CONTENTS; Preface; 1 Number Systems and Binary Codes; 1.1 Introduction; 1.2 Decimal Numbers; 1.3 Binary Numbers; 1.3.1 Basic Binary Arithmetic; 1.4 Octal Numbers; 1.5 Hexadecimal Numbers; 1.6 Signed Numbers; 1.6.1 Diminished Radix Complement; 1.6.2 Radix Complement; 1.7 Floating-Point Numbers; 1.8 Binary Encoding; 1.8.1 Weighted Codes; 1.8.2 Nonweighted Codes; Exercises; 2 Fundamental Concepts of Digital Logic; 2.1 Introduction; 2.2 Sets; 2.3 Relations; 2.4 Partitions; 2.5 Graphs; 2.6 Boolean Algebra; 2.7 Boolean Functions
2.8 Derivation and Classification of Boolean Functions2.9 Canonical Forms of Boolean Functions; 2.10 Logic Gates; Exercises; 3 Combinational Logic Design; 3.1 Introduction; 3.2 Minimization of Boolean Expressions; 3.3 Karnaugh Maps; 3.3.1 Don't Care Conditions; 3.3.2 The Complementary Approach; 3.4 Quine-MCCluskey Method; 3.4.1 Simplification of Boolean Function with Don't Cares; 3.5 Cubical Representation of Boolean Functions; 3.5.1 Tautology; 3.5.2 Complementation Using Shannon's Expansion; 3.6 Heuristic Minimization of Logic Circuits; 3.6.1 Expand; 3.6.2 Reduce; 3.6.3 Irredundant 3.6.4 Espresso3.7 Minimization of Multiple-Output Functions; 3.8 NAND-NAND and NOR-NOR Logic; 3.8.1 NAND-NAND Logic; 3.8.2 NOR-NOR Logic; 3.9 Multilevel Logic Design; 3.9.1 Algebraic and Boolean Division; 3.9.2 Kernels; 3.10 Minimization of Multilevel Circuits Using Don't Cares; 3.10.1 Satisfiability Don't Cares; 3.10.2 Observability Don't Cares; 3.11 Combinational Logic Implementation Using EX-OR and AND Gates; 3.12 Logic Circuit Design Using Multiplexers and Decoders; 3.12.1 Multiplexers; 3.12.2 Demultiplexers and Decoders; 3.13 Arithmetic Circuits; 3.13.1 Half-Adders; 3.13.2 Full Adders 3.13.3 Carry-Lookahead Adders3.13.4 Carry-Select Adder; 3.13.5 Carry-Save Addition; 3.13.6 BCD Adders; 3.13.7 Half-Subtractors; 3.13.8 Full Subtractors; 3.13.9 Two's Complement Subtractors; 3.13.10 BCD Substractors; 3.13.11 Multiplication; 3.13.12 Comparator; 3.14 Combinational Circuit Design Using PLDs; 3.14.1 PROM; 3.14.2 PLA; 3.14.3 PAL; Exercises; References; 4 Fundamentals of Synchronous Sequential Circuits; 4.1 Introduction; 4.2 Synchronous and Asynchronous Operation; 4.3 Latches; 4.4 Flip-Flops; 4.4.1 D Flip-Flop; 4.4.2 JK Flip-Flop; 4.4.3 T Flip-Flop 4.5 Timing in Synchronous Sequential Circuits4.6 State Tables and State Diagrams; 4.7 Mealy and Moore Models; 4.8 Analysis of Synchronous Sequential Circuits; Exercises; References; 5 VHDL in Digital Design; 5.1 Introduction; 5.2 Entity and Architecture; 5.2.1 Entity; 5.2.2 Architecture; 5.3 Lexical Elements in VHDL; 5.4 Data Types; 5.5 Operators; 5.6 Concurrent and Sequential Statements; 5.7 Architecture Description; 5.8 Structural Description; 5.9 Behavioral Description; 5.10 RTL Description; Exercises; 6 Combinational Logic Design Using VHDL; 6.1 Introduction 6.2 Concurrent Assignment Statements |
| Record Nr. | UNINA-9910877320203321 |
|
Lala Parag K. <1948->
|
||
| Hoboken, N.J., : Wiley-Interscience, c2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
