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42nd European Solid-State Circuits Conference : 12-15 September 2016, Lausanne, Switzerland / / Institute of Electrical and Electronics Engineers
| 42nd European Solid-State Circuits Conference : 12-15 September 2016, Lausanne, Switzerland / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2016 |
| Descrizione fisica | 1 online resource (108 pages) |
| Disciplina | 621.38152 |
| Soggetto topico |
Semiconductors
Integrated circuits Logic circuits |
| ISBN | 1-5090-2972-9 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910332498603321 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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42nd European Solid-State Circuits Conference : 12-15 September 2016, Lausanne, Switzerland / / Institute of Electrical and Electronics Engineers
| 42nd European Solid-State Circuits Conference : 12-15 September 2016, Lausanne, Switzerland / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2016 |
| Descrizione fisica | 1 online resource (108 pages) |
| Disciplina | 621.38152 |
| Soggetto topico |
Semiconductors
Integrated circuits Logic circuits |
| ISBN | 1-5090-2972-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996575453003316 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Accelerated training for large feedforward neural networks / / Slawomir W. Stepniewski, Charles C. Jorgensen
| Accelerated training for large feedforward neural networks / / Slawomir W. Stepniewski, Charles C. Jorgensen |
| Autore | Stepniewski Slawomir W. |
| Pubbl/distr/stampa | Moffett Field, California : , : National Aeronautics and Space Administration, Ames Research Center, , November 1998 |
| Descrizione fisica | 1 online resource (8 pages) : illustrations |
| Collana | NASA/TM |
| Soggetto topico |
Feedforward control
Logic circuits Neural nets Matrices (mathematics) Pulse rate |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910705876403321 |
Stepniewski Slawomir W.
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| Moffett Field, California : , : National Aeronautics and Space Administration, Ames Research Center, , November 1998 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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L'algebra di Boole e i circuiti logici / Franco Cianflone
| L'algebra di Boole e i circuiti logici / Franco Cianflone |
| Autore | Cianflone, Franco |
| Pubbl/distr/stampa | Milano : ETAS Kompass, c1968 |
| Descrizione fisica | 267 p. : ill. ; 24 cm. |
| Disciplina | 001.64 |
| Collana | Biblioteca del tecnico |
| Soggetto topico |
Boolean algebras
Logic circuits |
| Classificazione |
AMS 03G05
AMS 94C10 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | ita |
| Record Nr. | UNISALENTO-991000653059707536 |
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Cianflone, Franco
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| Milano : ETAS Kompass, c1968 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Salento | ||
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ANSI/IEEE Std 991-1986 : IEEE Standard for Logic Circuit Diagrams / / Institute of Electrical and Electronics Engineers
| ANSI/IEEE Std 991-1986 : IEEE Standard for Logic Circuit Diagrams / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, NJ : , : IEEE, , 1986 |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.38195835 |
| Soggetto topico | Logic circuits |
| ISBN | 0-7381-0950-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | ANSI/IEEE Std 991-1986: IEEE Standard for Logic Circuit Diagrams. Corrected Edition |
| Record Nr. | UNISA-996279563003316 |
| Piscataway, NJ : , : IEEE, , 1986 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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ANSI/IEEE Std 991-1986 : IEEE Standard for Logic Circuit Diagrams / / Institute of Electrical and Electronics Engineers
| ANSI/IEEE Std 991-1986 : IEEE Standard for Logic Circuit Diagrams / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, NJ : , : IEEE, , 1986 |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.38195835 |
| Soggetto topico | Logic circuits |
| ISBN | 0-7381-0950-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | ANSI/IEEE Std 991-1986: IEEE Standard for Logic Circuit Diagrams. Corrected Edition |
| Record Nr. | UNINA-9910135763503321 |
| Piscataway, NJ : , : IEEE, , 1986 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Correlation between analog noise measurements and the expected bit error rate of a digital signal propagating through passive components / / Joseph D. Warner and Onoufrios Theofylaktos
| Correlation between analog noise measurements and the expected bit error rate of a digital signal propagating through passive components / / Joseph D. Warner and Onoufrios Theofylaktos |
| Autore | Warner Joseph D. |
| Pubbl/distr/stampa | Cleveland, Ohio : , : National Aeronautics and Space Administration, Glenn Research Center, , [2012] |
| Descrizione fisica | 1 online resource (5 pages) : illustrations |
| Collana | NASA/TM 2012-217238 |
| Soggetto topico |
Cosmic rays
Logic circuits Bit error rate Circuits Correlation |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910704467403321 |
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Warner Joseph D.
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| Cleveland, Ohio : , : National Aeronautics and Space Administration, Glenn Research Center, , [2012] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Design, analysis and test of logic circuits under uncertainty / / Smita Krishnaswamy, Igor L. Markov, John P. Hayes
| Design, analysis and test of logic circuits under uncertainty / / Smita Krishnaswamy, Igor L. Markov, John P. Hayes |
| Autore | Krishnaswamy Smita |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | New York, : Springer, 2013 |
| Descrizione fisica | 1 online resource (129 p.) |
| Disciplina | 621.395 |
| Altri autori (Persone) |
MarkovIgor L
HayesJohn P <1944-> (John Patrick) |
| Collana | Lecture notes in electrical engineering |
| Soggetto topico |
Logic circuits
Uncertainty (Information theory) |
| ISBN |
1-283-64077-5
90-481-9644-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Probabilistic Transfer Matrices -- Computing with Probabilistic Transfer Matrices -- Testing Logic Circuits for Probabilistic Faults -- Signtaure-based Reliability Analysis -- Design for Robustness -- Summary and Extensions. |
| Record Nr. | UNINA-9910438050203321 |
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Krishnaswamy Smita
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| New York, : Springer, 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Digital design [[electronic resource]] : with a introduction to the verilog hdl / / M. Morris Mano, Michael D. Ciletti ; international edition contributions by B.R. Chandavarkar
| Digital design [[electronic resource]] : with a introduction to the verilog hdl / / M. Morris Mano, Michael D. Ciletti ; international edition contributions by B.R. Chandavarkar |
| Autore | Mano M. Morris <1927-> |
| Edizione | [Fifth edition, International edition.] |
| Pubbl/distr/stampa | Upper Saddle River, New Jersey : , : Pearson Prentice Hall, , [2013] |
| Descrizione fisica | 1 online resource (564 pages) |
| Disciplina | 621.395 |
| Soggetto topico |
Electronic digital computers - Circuits
Logic circuits Logic design Digital integrated circuits |
| ISBN | 0-273-77546-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover -- Contents -- Preface -- 1 Digital Systems and Binary Numbers -- 1.1 Digital Systems -- 1.2 Binary Numbers -- 1.3 Number-Base Conversions -- 1.4 Octal and Hexadecimal Numbers -- 1.5 Complements of Numbers -- 1.6 Signed Binary Numbers -- 1.7 Binary Codes -- 1.8 Binary Storage and Registers -- 1.9 Binary Logic -- 2 Boolean Algebra and Logic Gates -- 2.1 Introduction -- 2.2 Basic Definitions -- 2.3 Axiomatic Definition of Boolean Algebra -- 2.4 Basic Theorems and Properties of Boolean Algebra -- 2.5 Boolean Functions -- 2.6 Canonical and Standard Forms -- 2.7 Other Logic Operations -- 2.8 Digital Logic Gates -- 2.9 Integrated Circuits -- 3 Gate-Level Minimization -- 3.1 Introduction -- 3.2 The Map Method -- 3.3 Four-Variable K-Map -- 3.4 Product-of-Sums Simplification -- 3.5 Don't-Care Conditions -- 3.6 NAND and NOR Implementation -- 3.7 Other Two-Level Implementations -- 3.8 Exclusive-OR Function -- 3.9 Hardware Description Language -- 4 Combinational Logic -- 4.1 Introduction -- 4.2 Combinational Circuits -- 4.3 Analysis Procedure -- 4.4 Design Procedure -- 4.5 Binary Adder-Subtractor -- 4.6 Decimal Adder -- 4.7 Binary Multiplier -- 4.8 Magnitude Comparator -- 4.9 Decoders -- 4.10 Encoders -- 4.11 Multiplexers -- 4.12 HDL Models of Combinational Circuits -- 5 Synchronous Sequential Logic -- 5.1 Introduction -- 5.2 Sequential Circuits -- 5.3 Storage Elements: Latches -- 5.4 Storage Elements: Flip-Flops -- 5.5 Analysis of Clocked Sequential Circuits -- 5.6 Synthesizable HDL Models of Sequential Circuits -- 5.7 State Reduction and Assignment -- 5.8 Design Procedure -- 6 Registers and Counters -- 6.1 Registers -- 6.2 Shift Registers -- 6.3 Ripple Counters -- 6.4 Synchronous Counters -- 6.5 Other Counters -- 6.6 HDL for Registers and Counters -- 7 Memory and Programmable Logic -- 7.1 Introduction -- 7.2 Random-Access Memory.
7.3 Memory Decoding -- 7.4 Error Detection and Correction -- 7.5 Read-Only Memory -- 7.6 Programmable Logic Array -- 7.7 Programmable Array Logic -- 7.8 Sequential Programmable Devices -- 8 Design at the Register Transfer Level -- 8.1 Introduction -- 8.2 Register Transfer Level Notation -- 8.3 Register Transfer Level in HDL -- 8.4 Algorithmic State Machines (ASMs) -- 8.5 Design Example (ASMD Chart) -- 8.6 HDL Description of Design Example -- 8.7 Sequential Binary Multiplier -- 8.8 Control Logic -- 8.9 HDL Description of Binary Multiplier -- 8.10 Design with Multiplexers -- 8.11 Race-Free Design (Software Race Conditions) -- 8.12 Latch-Free Design (Why Waste Silicon?) -- 8.13 Other Language Features -- 9 Laboratory Experiments with Standard ICs and FPGAs -- 9.1 Introduction to Experiments -- 9.2 Experiment 1: Binary and Decimal Numbers -- 9.3 Experiment 2: Digital Logic Gates -- 9.4 Experiment 3: Simplification of Boolean Functions -- 9.5 Experiment 4: Combinational Circuits -- 9.6 Experiment 5: Code Converters -- 9.7 Experiment 6: Design with Multiplexers -- 9.8 Experiment 7: Adders and Subtractors -- 9.9 Experiment 8: Flip-Flops -- 9.10 Experiment 9: Sequential Circuits -- 9.11 Experiment 10: Counters -- 9.12 Experiment 11: Shift Registers -- 9.13 Experiment 12: Serial Addition -- 9.14 Experiment 13: Memory Unit -- 9.15 Experiment 14: Lamp Handball -- 9.16 Experiment 15: Clock-Pulse Generator -- 9.17 Experiment 16: Parallel Adder and Accumulator -- 9.18 Experiment 17: Binary Multiplier -- 9.19 Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAs -- 10 Standard Graphic Symbols -- 10.1 Rectangular-Shape Symbols -- 10.2 Qualifying Symbols -- 10.3 Dependency Notation -- 10.4 Symbols for Combinational Elements -- 10.5 Symbols for Flip-Flops -- 10.6 Symbols for Registers -- 10.7 Symbols for Counters -- 10.8 Symbol for RAM -- Appendix. Answers to Selected Problems -- Index. |
| Record Nr. | UNINA-9910150213903321 |
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Mano M. Morris <1927->
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| Upper Saddle River, New Jersey : , : Pearson Prentice Hall, , [2013] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Digital electronics . 1 Combinational logic circuits / / Tertulien Ndjountche
| Digital electronics . 1 Combinational logic circuits / / Tertulien Ndjountche |
| Autore | Ndjountche Tertulien |
| Pubbl/distr/stampa | London, England ; ; Hoboken, New Jersey : , : ISTE : , : Wiley, , 2016 |
| Descrizione fisica | 1 online resource (288 p.) |
| Disciplina | 621.38195835 |
| Soggetto topico | Logic circuits |
| ISBN |
1-119-31864-5
1-119-31863-7 1-119-31862-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro; Table of Contents; Title; Copyright; Preface; 1 Number Systems; 2 Logic Gates; 3 Function Blocks of Combinational Logic; 4 Systematic Methods for the Simplification of Logic Functions; Bibliography; Index; End User License Agreement; 1. Summary; 2. The reader; 1.1. Introduction; 1.2. Decimal numbers; 1.3. Binary numbers; 1.4. Octal numbers; 1.5. Hexadecimal numeration; 1.6. Representation in a radix B; 1.7. Binary-coded decimal numbers; 1.8. Representations of signed integers; 1.9. Representation of the fractional part of a number; 1.10. Arithmetic operations on binary numbers
1.11. Representation of real numbers1.12. Data representation; 1.13. Codes to protect against errors; 1.14. Exercises; 1.15. Solutions; 2.1. Introduction; 2.2. Logic gates; 2.3. Three-state buffer; 2.4. Logic function; 2.5. The correspondence between a truth table and a logic function; 2.6. Boolean algebra; 2.7. Multi-level logic circuit implementation; 2.8. Practical considerations; 2.9. Demonstration of some Boolean algebra identities; 2.10. Exercises; 2.11. Solutions; 3.1. Introduction; 3.2. Multiplexer; 3.3. Demultiplexer and decoder 3.4. Implementation of logic functions using multiplexers or decoders3.5. Encoders; 3.6. Transcoders; 3.7. Parity check generator; 3.8. Barrel shifter; 3.9. Exercises; 3.10. Solutions; 4.1. Introduction; 4.2. Definitions and reminders; 4.3. Karnaugh maps; 4.4. Systematic methods for simplification; 4.5. Exercises; 4.6. Solutions |
| Record Nr. | UNINA-9910134862503321 |
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Ndjountche Tertulien
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| London, England ; ; Hoboken, New Jersey : , : ISTE : , : Wiley, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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