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1990 proceedings
| 1990 proceedings |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society Press, 1990 |
| Descrizione fisica | 1 online resource (xiv, 342 pages) : illustrations |
| Disciplina | 621.3815 |
| Soggetto topico | Integrated circuits - Wafer-scale integration |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | The Lincoln programmable image-processing wafer,"R. -- MUSE: a wafer-scale systolic DSP,"D. -- WASP: a wafer-scale massively parallel processor,"R. -- The WASP demonstrator programme: the engineering of a wafer-scale system,"I. -- Re-wafer scale integration: a new approach to active phased arrays,"L. -- A 64 Mb MROM with good pair selection architecture,"K. -- A high performance single chip FFT array processor for wafer scale integration,"Jaehee -- Implementation of configurable hardware using wafer scale integration,"T. -- Crosspoint Arithmetic Processor architecture for wafer scale integration,"J. -- A linear-array WSI architecture for improved yield and performance,"R. -- Introduction of a new architecture for wafer integration through configuration hierarchies: resulting in practical monolithic self configuring wafer scale integration,"P. -- WSI architecture for L-U decomposition: a radar array processor,"V. -- Defect tolerance scheme for gigaFLOP WSI architectures,"A. -- A general configurable architecture for WSI implementation for neural nets,"F. -- WSI architecture of a neurocomputer module,"U. -- Defect tolerant sorting networks for WSI implementation,"Sheng-Chiech -- Data manipulator network for WSI designs,"J. -- Multiple fault detection and location in WSI baseline interconnection networks,"C. -- Effects of switch failure on soft-configurable WSI yield,"M. -- Defect tolerant implementations of feed-forward and recurrent neural networks," -- A visually oriented architectural fault simulation environment for WSI," -- Hierarchical fault tolerance for 3D microelectronics," -- Distributed diagnosis for wafer scale systems," -- Fault tolerance performance of WSI systolic sorter," -- Fault-tolerant WSI array processors: the use of Berger codes in parallel arithmetic-logic units," -- A defect and fault tolerant design of WSI static RAM modules, -- A methodology for wafer scale integration of linear pipelined arrays," -- Some new algorithms for reconfiguring VLSI/WSI arrays," -- Soft-programmable bypass switch design for defect-tolerant arrays," -- Yield enhancement for WSI array processors using two-and-half-track switches," -- Testing wafer scale arrays: constant testability under multiple faults," -- A self-test methodology for restructurable WSI," -- Divide-and-conquer in wafer scale array testing," -- Yield modeling and optimization of large redundant RAMs," -- Power distribution strategies based on current estimation and simulation of lossy transmission lines in conjunction with power isolation circuits," -- Investigations of Nd:YAG laser formed connections and disconnections of standard CMOS double level metallizations," -- Hybrid wafer scale interconnection inventing a new technology," -- WSI implemented with button board interconnection," -- A study of high density multilayer LSI," -- Wafer scale integration (WSI) of programmable gate arrays (PGA's),". --. |
| Record Nr. | UNISA-996211381703316 |
| [Place of publication not identified], : IEEE Computer Society Press, 1990 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Advances in embedded and fan-out wafer level packaging technologies / / edited by Beth Keser and Steffen Kröhnert
| Advances in embedded and fan-out wafer level packaging technologies / / edited by Beth Keser and Steffen Kröhnert |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, New Jersey, USA : , : John Wiley & Sons, Inc., , 2019 |
| Descrizione fisica | 1 online resource (xxvii, 548 pages) : illustrations |
| Disciplina | 621.38173 |
| Soggetto topico |
Integrated circuits
Integrated circuits - Wafer-scale integration Chip scale packaging |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-119-31397-X
1-119-31399-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Preface xvii -- List of Contributors xxiii -- Acknowledgments xxvii -- 1 History of Embedded and Fan-Out Packaging Technology 1 /Michael Topper, Andreas Ostmann, Tanja Braun, and Klaus-Dieter Lang -- 2 FO-WLP Market and Technology Trends 39 /E. Jan Vardaman -- 3 Embedded Wafer-Level Ball Grid Array (eWLB) Packaging Technology Platform 55 /Thorsten Meyer and Steffen Krohnert -- 4 Ultrathin 3D FO-WLP eWLB-PoP (Embedded Wafer-Level Ball Grid Array-Package-on-Package) Technology 77 /S.W. Yoon -- 5 NEPES’ Fan-Out Packaging Technology from Single die, SiP to Panel-Level Packaging 97 /Jong Heon (Jay) Kim -- 6 M-Series Fan-Out with Adaptive Patterning 117 /Tim Olson and Chris Scanlan -- 7 SWIFTR Semiconductor Packaging Technology 141 /Ron Huemoeller and Curtis Zwenger -- 8 Embedded Silicon Fan-Out (eSiFOR) Technology for Wafer-Level System Integration 169 /Daquan Yu -- 9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology 185 /Thomas Gottwald, Christian Roessle, and Alexander Neumann -- 10 Embedding of Power Electronic Components: The Smart p2 Pack Technology 201 /Thomas Gottwald and Christian Roessle -- 11 Embedded Die in Substrate (Panel-Level) Packaging Technology 217 /Tomoko Takahashi and Akio Katsumata -- 12 Blade: A Chip-First Embedded Technology for Power Packaging 241 /Boris Plikat and Thorsten Scharf -- 13 The Role of Liquid Molding Compounds in the Success of Fan-Out Wafer-Level Packaging Technology 261 /Katsushi Kan, Michiyasu Sugahara, and Markus Cichon -- 14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan-Out Wafer-Level Packaging (FO-WLP) 271 /T. Enomoto, J.I. Matthews, and T. Motobe -- 15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer-Level Packaging 317 /Stefan Vanclooster and Dimitri Janssen -- 16 The Role of Pick and Place in Fan-Out Wafer-Level Packaging 347 /Hugo Pristauz, Alastair Attard, and Harald Meixner -- 17 Process and Equipment for eWLB: Chip Embedding by Molding 371 /Edward Furgut, Hirohito Oshimori, and Hiroaki Yamagishi.
18 Tools for Fan-Out Wafer-Level Package Processing 403 /Nelson Fan, Eric Kuah, Eric Ng, and Otto Cheung -- 19 Equipment and Process for eWLB: Required PVD/Sputter Solutions 419 /Chris Jones, Ricardo Gaio, and Jose Castro -- 20 Excimer Laser Ablation for the Patterning of Ultra-fine Routings 441 /Habib Hichri, Markus Arendt, and Seongkuk Lee -- 21 Temporary Carrier Technologies for eWLB and RDL-First Fan-Out Wafer-Level Packages 457 /Thomas Uhrmann and Boris Povazay -- 22 Encapsulated Wafer-Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection 471 /S.W. Yoon -- 23 Embedded Multi-die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect 487 /Ravi Mahajan, Robert Sankman, Kemal Aygun, Zhiguo Qian, Ashish Dhall, Jonathan Rosch, Debendra Mallik, and Islam Salama -- 24 Interconnection Technology Innovations in 2.5D Integrated Electronic Systems 501 /Paragkumar A. Thadesar, Paul K. Jo, and Muhannad S. Bakir -- References 515 -- Index 521. |
| Record Nr. | UNINA-9910467588503321 |
| Hoboken, New Jersey, USA : , : John Wiley & Sons, Inc., , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Advances in embedded and fan-out wafer level packaging technologies / / edited by Beth Keser and Steffen Kröhnert
| Advances in embedded and fan-out wafer level packaging technologies / / edited by Beth Keser and Steffen Kröhnert |
| Edizione | [First edition] |
| Pubbl/distr/stampa | Hoboken, New Jersey, USA : , : John Wiley & Sons, Inc., , 2019 |
| Descrizione fisica | 1 online resource (xxvii, 548 pages) : illustrations |
| Disciplina | 621.38173 |
| Collana | THEi Wiley ebooks. |
| Soggetto topico |
Integrated circuits
Integrated circuits - Wafer-scale integration Chip scale packaging |
| ISBN |
1-119-31398-8
1-119-31397-X 1-119-31399-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Preface xvii -- List of Contributors xxiii -- Acknowledgments xxvii -- 1 History of Embedded and Fan-Out Packaging Technology 1 /Michael Topper, Andreas Ostmann, Tanja Braun, and Klaus-Dieter Lang -- 2 FO-WLP Market and Technology Trends 39 /E. Jan Vardaman -- 3 Embedded Wafer-Level Ball Grid Array (eWLB) Packaging Technology Platform 55 /Thorsten Meyer and Steffen Krohnert -- 4 Ultrathin 3D FO-WLP eWLB-PoP (Embedded Wafer-Level Ball Grid Array-Package-on-Package) Technology 77 /S.W. Yoon -- 5 NEPES’ Fan-Out Packaging Technology from Single die, SiP to Panel-Level Packaging 97 /Jong Heon (Jay) Kim -- 6 M-Series Fan-Out with Adaptive Patterning 117 /Tim Olson and Chris Scanlan -- 7 SWIFTR Semiconductor Packaging Technology 141 /Ron Huemoeller and Curtis Zwenger -- 8 Embedded Silicon Fan-Out (eSiFOR) Technology for Wafer-Level System Integration 169 /Daquan Yu -- 9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology 185 /Thomas Gottwald, Christian Roessle, and Alexander Neumann -- 10 Embedding of Power Electronic Components: The Smart p2 Pack Technology 201 /Thomas Gottwald and Christian Roessle -- 11 Embedded Die in Substrate (Panel-Level) Packaging Technology 217 /Tomoko Takahashi and Akio Katsumata -- 12 Blade: A Chip-First Embedded Technology for Power Packaging 241 /Boris Plikat and Thorsten Scharf -- 13 The Role of Liquid Molding Compounds in the Success of Fan-Out Wafer-Level Packaging Technology 261 /Katsushi Kan, Michiyasu Sugahara, and Markus Cichon -- 14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan-Out Wafer-Level Packaging (FO-WLP) 271 /T. Enomoto, J.I. Matthews, and T. Motobe -- 15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer-Level Packaging 317 /Stefan Vanclooster and Dimitri Janssen -- 16 The Role of Pick and Place in Fan-Out Wafer-Level Packaging 347 /Hugo Pristauz, Alastair Attard, and Harald Meixner -- 17 Process and Equipment for eWLB: Chip Embedding by Molding 371 /Edward Furgut, Hirohito Oshimori, and Hiroaki Yamagishi.
18 Tools for Fan-Out Wafer-Level Package Processing 403 /Nelson Fan, Eric Kuah, Eric Ng, and Otto Cheung -- 19 Equipment and Process for eWLB: Required PVD/Sputter Solutions 419 /Chris Jones, Ricardo Gaio, and Jose Castro -- 20 Excimer Laser Ablation for the Patterning of Ultra-fine Routings 441 /Habib Hichri, Markus Arendt, and Seongkuk Lee -- 21 Temporary Carrier Technologies for eWLB and RDL-First Fan-Out Wafer-Level Packages 457 /Thomas Uhrmann and Boris Povazay -- 22 Encapsulated Wafer-Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection 471 /S.W. Yoon -- 23 Embedded Multi-die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect 487 /Ravi Mahajan, Robert Sankman, Kemal Aygun, Zhiguo Qian, Ashish Dhall, Jonathan Rosch, Debendra Mallik, and Islam Salama -- 24 Interconnection Technology Innovations in 2.5D Integrated Electronic Systems 501 /Paragkumar A. Thadesar, Paul K. Jo, and Muhannad S. Bakir -- References 515 -- Index 521. |
| Record Nr. | UNINA-9910535058003321 |
| Hoboken, New Jersey, USA : , : John Wiley & Sons, Inc., , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Advances in embedded and fan-out wafer level packaging technologies / / edited by Beth Keser and Steffen Kröhnert
| Advances in embedded and fan-out wafer level packaging technologies / / edited by Beth Keser and Steffen Kröhnert |
| Edizione | [First edition] |
| Pubbl/distr/stampa | Hoboken, New Jersey, USA : , : John Wiley & Sons, Inc., , 2019 |
| Descrizione fisica | 1 online resource (xxvii, 548 pages) : illustrations |
| Disciplina | 621.38173 |
| Collana | THEi Wiley ebooks. |
| Soggetto topico |
Integrated circuits
Integrated circuits - Wafer-scale integration Chip scale packaging |
| ISBN |
1-119-31398-8
1-119-31397-X 1-119-31399-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Preface xvii -- List of Contributors xxiii -- Acknowledgments xxvii -- 1 History of Embedded and Fan-Out Packaging Technology 1 /Michael Topper, Andreas Ostmann, Tanja Braun, and Klaus-Dieter Lang -- 2 FO-WLP Market and Technology Trends 39 /E. Jan Vardaman -- 3 Embedded Wafer-Level Ball Grid Array (eWLB) Packaging Technology Platform 55 /Thorsten Meyer and Steffen Krohnert -- 4 Ultrathin 3D FO-WLP eWLB-PoP (Embedded Wafer-Level Ball Grid Array-Package-on-Package) Technology 77 /S.W. Yoon -- 5 NEPES’ Fan-Out Packaging Technology from Single die, SiP to Panel-Level Packaging 97 /Jong Heon (Jay) Kim -- 6 M-Series Fan-Out with Adaptive Patterning 117 /Tim Olson and Chris Scanlan -- 7 SWIFTR Semiconductor Packaging Technology 141 /Ron Huemoeller and Curtis Zwenger -- 8 Embedded Silicon Fan-Out (eSiFOR) Technology for Wafer-Level System Integration 169 /Daquan Yu -- 9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology 185 /Thomas Gottwald, Christian Roessle, and Alexander Neumann -- 10 Embedding of Power Electronic Components: The Smart p2 Pack Technology 201 /Thomas Gottwald and Christian Roessle -- 11 Embedded Die in Substrate (Panel-Level) Packaging Technology 217 /Tomoko Takahashi and Akio Katsumata -- 12 Blade: A Chip-First Embedded Technology for Power Packaging 241 /Boris Plikat and Thorsten Scharf -- 13 The Role of Liquid Molding Compounds in the Success of Fan-Out Wafer-Level Packaging Technology 261 /Katsushi Kan, Michiyasu Sugahara, and Markus Cichon -- 14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan-Out Wafer-Level Packaging (FO-WLP) 271 /T. Enomoto, J.I. Matthews, and T. Motobe -- 15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer-Level Packaging 317 /Stefan Vanclooster and Dimitri Janssen -- 16 The Role of Pick and Place in Fan-Out Wafer-Level Packaging 347 /Hugo Pristauz, Alastair Attard, and Harald Meixner -- 17 Process and Equipment for eWLB: Chip Embedding by Molding 371 /Edward Furgut, Hirohito Oshimori, and Hiroaki Yamagishi.
18 Tools for Fan-Out Wafer-Level Package Processing 403 /Nelson Fan, Eric Kuah, Eric Ng, and Otto Cheung -- 19 Equipment and Process for eWLB: Required PVD/Sputter Solutions 419 /Chris Jones, Ricardo Gaio, and Jose Castro -- 20 Excimer Laser Ablation for the Patterning of Ultra-fine Routings 441 /Habib Hichri, Markus Arendt, and Seongkuk Lee -- 21 Temporary Carrier Technologies for eWLB and RDL-First Fan-Out Wafer-Level Packages 457 /Thomas Uhrmann and Boris Povazay -- 22 Encapsulated Wafer-Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection 471 /S.W. Yoon -- 23 Embedded Multi-die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect 487 /Ravi Mahajan, Robert Sankman, Kemal Aygun, Zhiguo Qian, Ashish Dhall, Jonathan Rosch, Debendra Mallik, and Islam Salama -- 24 Interconnection Technology Innovations in 2.5D Integrated Electronic Systems 501 /Paragkumar A. Thadesar, Paul K. Jo, and Muhannad S. Bakir -- References 515 -- Index 521. |
| Record Nr. | UNINA-9910815323503321 |
| Hoboken, New Jersey, USA : , : John Wiley & Sons, Inc., , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces : high performance compute and system-in-package / / edited by Beth Keser and Steffen Kröhnert
| Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces : high performance compute and system-in-package / / edited by Beth Keser and Steffen Kröhnert |
| Pubbl/distr/stampa | Piscataway, New Jersey ; ; Hoboken, New Jersey : , : IEEE Press : , : Wiley, , [2022] |
| Descrizione fisica | 1 online resource (323 pages) |
| Disciplina | 621.395 |
| Collana | IEEE Press Ser. |
| Soggetto topico |
Chip scale packaging
Integrated circuits - Wafer-scale integration Microelectronics |
| ISBN |
1-119-79389-0
1-119-79390-4 1-119-79384-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910555144103321 |
| Piscataway, New Jersey ; ; Hoboken, New Jersey : , : IEEE Press : , : Wiley, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces : high performance compute and system-in-package / / edited by Beth Keser and Steffen Kröhnert
| Embedded and fan-out wafer and panel level packaging technologies for advanced application spaces : high performance compute and system-in-package / / edited by Beth Keser and Steffen Kröhnert |
| Pubbl/distr/stampa | Piscataway, New Jersey ; ; Hoboken, New Jersey : , : IEEE Press : , : Wiley, , [2022] |
| Descrizione fisica | 1 online resource (323 pages) |
| Disciplina | 621.395 |
| Collana | IEEE Press |
| Soggetto topico |
Chip scale packaging
Integrated circuits - Wafer-scale integration Microelectronics |
| ISBN |
1-119-79389-0
1-119-79390-4 1-119-79384-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910830048403321 |
| Piscataway, New Jersey ; ; Hoboken, New Jersey : , : IEEE Press : , : Wiley, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
IEEE International Conference on Wafer Scale Integration, 1993
| IEEE International Conference on Wafer Scale Integration, 1993 |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 1993 |
| Descrizione fisica | 1 online resource (384 pages) : illustrations |
| Disciplina | 621.38173 |
| Soggetto topico |
Integrated circuits - Wafer-scale integration
Integrated circuits |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996211914203316 |
| [Place of publication not identified], : IEEE, 1993 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Proceedings / / International Conference on Innovative Systems in Silicon
| Proceedings / / International Conference on Innovative Systems in Silicon |
| Pubbl/distr/stampa | [New York, N.Y.], : Institute of Electrical and Electronics Engineers, c1996- |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.39/5 |
| Soggetto topico |
Integrated circuits - Very large scale integration
Integrated circuits - Wafer-scale integration Semiconductors |
| Soggetto genere / forma |
Conference papers and proceedings.
Congresses. |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
IEEE International Conference on Innovative Systems in Silicon
IEEE Innovative systems in Silicon Innovative Systems in Silicon |
| Record Nr. | UNISA-996280031503316 |
| [New York, N.Y.], : Institute of Electrical and Electronics Engineers, c1996- | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Proceedings / / International Conference on Innovative Systems in Silicon
| Proceedings / / International Conference on Innovative Systems in Silicon |
| Pubbl/distr/stampa | [New York, N.Y.], : Institute of Electrical and Electronics Engineers, c1996- |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.39/5 |
| Soggetto topico |
Integrated circuits - Very large scale integration
Integrated circuits - Wafer-scale integration Semiconductors |
| Soggetto genere / forma |
Conference papers and proceedings.
Congresses. |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
IEEE International Conference on Innovative Systems in Silicon
IEEE Innovative systems in Silicon Innovative Systems in Silicon |
| Record Nr. | UNINA-9910626012503321 |
| [New York, N.Y.], : Institute of Electrical and Electronics Engineers, c1996- | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Proceedings / / International Conference on Wafer Scale Integration
| Proceedings / / International Conference on Wafer Scale Integration |
| Pubbl/distr/stampa | Washington, D.C., : IEEE Computer Society Press, ©1989-©1995 |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.3815 |
| Soggetto topico | Integrated circuits - Wafer-scale integration |
| Soggetto genere / forma | Conference papers and proceedings. |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996281128603316 |
| Washington, D.C., : IEEE Computer Society Press, ©1989-©1995 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
