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Mixed analog-digital VLSI devices and technology [[electronic resource] /] / Yannis Tsividis
| Mixed analog-digital VLSI devices and technology [[electronic resource] /] / Yannis Tsividis |
| Autore | Tsividis Yannis |
| Pubbl/distr/stampa | Singapore ; ; River Edge, N.J., : World Scientific, c2002 |
| Descrizione fisica | x, 284 p. : ill |
| Disciplina | 621.39/5 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design and construction
Integrated circuits - Very large scale integration - Mathematical models Mixed signal circuits |
| Soggetto genere / forma | Electronic books. |
| ISBN | 981-270-384-5 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | ch. 1. Introduction: mixed analog-digital chips. 1.1. The role and place of modern mixed analog-digital chips. 1.2. Advantages of mixing analog and digital circuits on the same chip. 1.3. Applications of MAD chips. 1.4. Obstacles in the design of MAD chips. 1.5. The aim and contents of this book -- ch. 2. The MOSFET: introduction and qualitative view. 2.1. Introduction. 2.2. MOS transistor structure. 2.3. Assumptions about terminal voltages, currents, and temperature. 2.4. A qualitative description of MOSFET operation. 2.5. A fluid dynamical analog. 2.6. Complete set of characteristics. 2.7. Form of functional [symbol] dependence: practical limits for regions of inversion. 2.8. Factors affecting the extrapolated threshold voltage. 2.9. Other factors affecting the drain current -- ch. 3. MOSFET DC modeling. 3.1. Introduction. 3.2. DC model for weak and for strong inversion. 3.3. Drain versus source. 3.4. Symmetric models. 3.5. General models and moderate inversion. 3.6. Mobility dependence on gate and substrate bias. 3.7. Temperature effects. 3.8. Small-dimension effects. 3.9. Breakdown. 3.10. The pMOS transistor. 3.11. Device symbols. 3.12. Model accuracy, parameter extraction, and computer simulation -- ch. 4. MOSFET small-signal modeling. 4.1. Introduction. 4.2. Small-signal conductance parameters. 4.3. Expressions for small-signal conductance parameters in weak and in strong inversion. 4.4. Capacitance parameters. 4.5. Intrinsic cutoff frequency and limits of model validity. 4.6. The transistor at very high frequencies. 4.7. Noise. 4.8. General models and moderate inversion. 4.9. Parameter extraction for accurate small-signal modeling. 4.10. Requirements for good CAD models -- ch. 5. Technology and available circuit components. 5.1. Introduction. 5.2. The n-well CMOS process. 5.3. BiCMOS processes. 5.4. Other silicon processes. 5.5. Sensors. 5.6. Trimming. 5.7. Tolerance and matching of electrical parameters. 5.8. Chip size and yield. 5.9. The influence of pads and package -- ch. 6. Layout. 6.1. Introduction. 6.2. Relation of fabricated transistors to layout. 6.3. Transistor geometry and layout. 6.4. Layout for device matching and precision parameter ratios. 6.5. Layout for interference reduction. 6.6. Integrated-circuit design. |
| Record Nr. | UNINA-9910451952803321 |
Tsividis Yannis
|
||
| Singapore ; ; River Edge, N.J., : World Scientific, c2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Mixed analog-digital VLSI devices and technology [[electronic resource] /] / Yannis Tsividis
| Mixed analog-digital VLSI devices and technology [[electronic resource] /] / Yannis Tsividis |
| Autore | Tsividis Yannis |
| Pubbl/distr/stampa | Singapore ; ; River Edge, N.J., : World Scientific, c2002 |
| Descrizione fisica | x, 284 p. : ill |
| Disciplina | 621.39/5 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design and construction
Integrated circuits - Very large scale integration - Mathematical models Mixed signal circuits |
| ISBN | 981-270-384-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | ch. 1. Introduction: mixed analog-digital chips. 1.1. The role and place of modern mixed analog-digital chips. 1.2. Advantages of mixing analog and digital circuits on the same chip. 1.3. Applications of MAD chips. 1.4. Obstacles in the design of MAD chips. 1.5. The aim and contents of this book -- ch. 2. The MOSFET: introduction and qualitative view. 2.1. Introduction. 2.2. MOS transistor structure. 2.3. Assumptions about terminal voltages, currents, and temperature. 2.4. A qualitative description of MOSFET operation. 2.5. A fluid dynamical analog. 2.6. Complete set of characteristics. 2.7. Form of functional [symbol] dependence: practical limits for regions of inversion. 2.8. Factors affecting the extrapolated threshold voltage. 2.9. Other factors affecting the drain current -- ch. 3. MOSFET DC modeling. 3.1. Introduction. 3.2. DC model for weak and for strong inversion. 3.3. Drain versus source. 3.4. Symmetric models. 3.5. General models and moderate inversion. 3.6. Mobility dependence on gate and substrate bias. 3.7. Temperature effects. 3.8. Small-dimension effects. 3.9. Breakdown. 3.10. The pMOS transistor. 3.11. Device symbols. 3.12. Model accuracy, parameter extraction, and computer simulation -- ch. 4. MOSFET small-signal modeling. 4.1. Introduction. 4.2. Small-signal conductance parameters. 4.3. Expressions for small-signal conductance parameters in weak and in strong inversion. 4.4. Capacitance parameters. 4.5. Intrinsic cutoff frequency and limits of model validity. 4.6. The transistor at very high frequencies. 4.7. Noise. 4.8. General models and moderate inversion. 4.9. Parameter extraction for accurate small-signal modeling. 4.10. Requirements for good CAD models -- ch. 5. Technology and available circuit components. 5.1. Introduction. 5.2. The n-well CMOS process. 5.3. BiCMOS processes. 5.4. Other silicon processes. 5.5. Sensors. 5.6. Trimming. 5.7. Tolerance and matching of electrical parameters. 5.8. Chip size and yield. 5.9. The influence of pads and package -- ch. 6. Layout. 6.1. Introduction. 6.2. Relation of fabricated transistors to layout. 6.3. Transistor geometry and layout. 6.4. Layout for device matching and precision parameter ratios. 6.5. Layout for interference reduction. 6.6. Integrated-circuit design. |
| Record Nr. | UNINA-9910778263203321 |
|
Tsividis Yannis
|
||
| Singapore ; ; River Edge, N.J., : World Scientific, c2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
A one-semester course in modeling of VLSI interconnections / / Ashok K. Goel
| A one-semester course in modeling of VLSI interconnections / / Ashok K. Goel |
| Autore | Goel Ashok K. <1953-> |
| Pubbl/distr/stampa | New York, NY : , : Momentum Press, , [2015] |
| Descrizione fisica | 1 online resource (362 p.) |
| Disciplina | 621.395 |
| Collana | Electronic circuits and semiconductor devices collection |
| Soggetto topico | Integrated circuits - Very large scale integration - Mathematical models |
| Soggetto genere / forma | Electronic books. |
| ISBN | 1-60650-513-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
1. Introductory concepts -- 1.1 Metallic interconnections -- 1.2 Simplified modeling of resistive interconnections as ladder networks -- 1.3 Propagation modes in a metallic interconnection -- 1.4 Slow-wave mode -- 1.5 Propagation delays --
2. Modeling of interconnection resistances, capacitances, and inductances -- 2.1 Interconnection resistance -- 2.2 Modeling of resistance for a copper interconnection -- 2.3 Interconnection capacitances -- 2.4 The Green's function method, Method of images -- 2.5 Green's function method, Fourier integral approach -- 2.6 Interconnection inductances -- 2.7 Inductance extraction using FastHenry -- 2.8 Approximate equations for capacitances -- 2.9 Approximate equations for interconnection capacitances and inductances on silicon and GaAs substrates -- 3. Modeling of interconnection delays -- 3.1 Metal-insulator-semiconductor microstrip line model of an interconnection -- 3.2 Transmission line analysis of single-level interconnections -- 3.3 Transmission line model for multilevel interconnections -- 3.4 Modeling of parallel and crossing interconnections -- 3.5 Modeling of very-high-frequency losses in interconnections -- 3.6 Compact modeling of interconnection delays -- 3.7 Modeling of active interconnections -- 4. Modeling of interconnection crosstalk -- 4.1 Lumped capacitance model -- 4.2 Coupled multiconductor MIS microstrip line model -- 4.3 Frequency-domain model analysis of single-level interconnections -- 4.4 Transmission line analysis of parallel multilevel interconnections -- 4.5 Compact expressions for crosstalk analysis -- 5. Modeling of electromigration-induced interconnection failure -- 5.1 Electromigration factors and mechanism -- 5.2 Problems caused by electromigration -- 5.3 Reduction of electromigration -- 5.4 Measurement of electromigration -- 5.5 Electromigration in the copper interconnections -- 5.6 Models of integrated circuit reliability -- 5.7 Modeling of electromigration due to current pulses -- 5.8 Guidelines for testing electromigration -- 6. Other interconnection technologies -- 6.1 Optical interconnections -- 6.2 Superconducting interconnections -- 6.3 Nanotechnology circuit interconnections -- Appendixes -- A. Tables of constants -- B. Method of images -- C. Method of moments -- D. Transmission line equations -- E. Miller's theorem -- F. Inverse Laplace transformation technique -- Index. |
| Record Nr. | UNINA-9910459790103321 |
|
Goel Ashok K. <1953->
|
||
| New York, NY : , : Momentum Press, , [2015] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
A one-semester course in modeling of VLSI interconnections / / Ashok K. Goel
| A one-semester course in modeling of VLSI interconnections / / Ashok K. Goel |
| Autore | Goel Ashok K. <1953-> |
| Pubbl/distr/stampa | New York, NY : , : Momentum Press, , [2015] |
| Descrizione fisica | 1 online resource (362 p.) |
| Disciplina | 621.395 |
| Collana | Electronic circuits and semiconductor devices collection |
| Soggetto topico | Integrated circuits - Very large scale integration - Mathematical models |
| ISBN | 1-60650-513-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
1. Introductory concepts -- 1.1 Metallic interconnections -- 1.2 Simplified modeling of resistive interconnections as ladder networks -- 1.3 Propagation modes in a metallic interconnection -- 1.4 Slow-wave mode -- 1.5 Propagation delays --
2. Modeling of interconnection resistances, capacitances, and inductances -- 2.1 Interconnection resistance -- 2.2 Modeling of resistance for a copper interconnection -- 2.3 Interconnection capacitances -- 2.4 The Green's function method, Method of images -- 2.5 Green's function method, Fourier integral approach -- 2.6 Interconnection inductances -- 2.7 Inductance extraction using FastHenry -- 2.8 Approximate equations for capacitances -- 2.9 Approximate equations for interconnection capacitances and inductances on silicon and GaAs substrates -- 3. Modeling of interconnection delays -- 3.1 Metal-insulator-semiconductor microstrip line model of an interconnection -- 3.2 Transmission line analysis of single-level interconnections -- 3.3 Transmission line model for multilevel interconnections -- 3.4 Modeling of parallel and crossing interconnections -- 3.5 Modeling of very-high-frequency losses in interconnections -- 3.6 Compact modeling of interconnection delays -- 3.7 Modeling of active interconnections -- 4. Modeling of interconnection crosstalk -- 4.1 Lumped capacitance model -- 4.2 Coupled multiconductor MIS microstrip line model -- 4.3 Frequency-domain model analysis of single-level interconnections -- 4.4 Transmission line analysis of parallel multilevel interconnections -- 4.5 Compact expressions for crosstalk analysis -- 5. Modeling of electromigration-induced interconnection failure -- 5.1 Electromigration factors and mechanism -- 5.2 Problems caused by electromigration -- 5.3 Reduction of electromigration -- 5.4 Measurement of electromigration -- 5.5 Electromigration in the copper interconnections -- 5.6 Models of integrated circuit reliability -- 5.7 Modeling of electromigration due to current pulses -- 5.8 Guidelines for testing electromigration -- 6. Other interconnection technologies -- 6.1 Optical interconnections -- 6.2 Superconducting interconnections -- 6.3 Nanotechnology circuit interconnections -- Appendixes -- A. Tables of constants -- B. Method of images -- C. Method of moments -- D. Transmission line equations -- E. Miller's theorem -- F. Inverse Laplace transformation technique -- Index. |
| Record Nr. | UNINA-9910787492903321 |
|
Goel Ashok K. <1953->
|
||
| New York, NY : , : Momentum Press, , [2015] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
A one-semester course in modeling of VLSI interconnections / / Ashok K. Goel
| A one-semester course in modeling of VLSI interconnections / / Ashok K. Goel |
| Autore | Goel Ashok K. <1953-> |
| Pubbl/distr/stampa | New York, NY : , : Momentum Press, , [2015] |
| Descrizione fisica | 1 online resource (362 p.) |
| Disciplina | 621.395 |
| Collana | Electronic circuits and semiconductor devices collection |
| Soggetto topico | Integrated circuits - Very large scale integration - Mathematical models |
| ISBN | 1-60650-513-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
1. Introductory concepts -- 1.1 Metallic interconnections -- 1.2 Simplified modeling of resistive interconnections as ladder networks -- 1.3 Propagation modes in a metallic interconnection -- 1.4 Slow-wave mode -- 1.5 Propagation delays --
2. Modeling of interconnection resistances, capacitances, and inductances -- 2.1 Interconnection resistance -- 2.2 Modeling of resistance for a copper interconnection -- 2.3 Interconnection capacitances -- 2.4 The Green's function method, Method of images -- 2.5 Green's function method, Fourier integral approach -- 2.6 Interconnection inductances -- 2.7 Inductance extraction using FastHenry -- 2.8 Approximate equations for capacitances -- 2.9 Approximate equations for interconnection capacitances and inductances on silicon and GaAs substrates -- 3. Modeling of interconnection delays -- 3.1 Metal-insulator-semiconductor microstrip line model of an interconnection -- 3.2 Transmission line analysis of single-level interconnections -- 3.3 Transmission line model for multilevel interconnections -- 3.4 Modeling of parallel and crossing interconnections -- 3.5 Modeling of very-high-frequency losses in interconnections -- 3.6 Compact modeling of interconnection delays -- 3.7 Modeling of active interconnections -- 4. Modeling of interconnection crosstalk -- 4.1 Lumped capacitance model -- 4.2 Coupled multiconductor MIS microstrip line model -- 4.3 Frequency-domain model analysis of single-level interconnections -- 4.4 Transmission line analysis of parallel multilevel interconnections -- 4.5 Compact expressions for crosstalk analysis -- 5. Modeling of electromigration-induced interconnection failure -- 5.1 Electromigration factors and mechanism -- 5.2 Problems caused by electromigration -- 5.3 Reduction of electromigration -- 5.4 Measurement of electromigration -- 5.5 Electromigration in the copper interconnections -- 5.6 Models of integrated circuit reliability -- 5.7 Modeling of electromigration due to current pulses -- 5.8 Guidelines for testing electromigration -- 6. Other interconnection technologies -- 6.1 Optical interconnections -- 6.2 Superconducting interconnections -- 6.3 Nanotechnology circuit interconnections -- Appendixes -- A. Tables of constants -- B. Method of images -- C. Method of moments -- D. Transmission line equations -- E. Miller's theorem -- F. Inverse Laplace transformation technique -- Index. |
| Record Nr. | UNINA-9910807642703321 |
|
Goel Ashok K. <1953->
|
||
| New York, NY : , : Momentum Press, , [2015] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
