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2006 IEEE International Conference on Integrated Circuit Design and Technology, 2006 : ICICDT '06, Padova, Italy, 24-26, May, 2006 : proceedings
| 2006 IEEE International Conference on Integrated Circuit Design and Technology, 2006 : ICICDT '06, Padova, Italy, 24-26, May, 2006 : proceedings |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2006 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design
Computer-aided design Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN | 1-5090-9417-2 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996207702203316 |
| [Place of publication not identified], : IEEE, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2006 IEEE International Conference on Integrated Circuit Design and Technology, 2006 : ICICDT '06, Padova, Italy, 24-26, May, 2006 : proceedings
| 2006 IEEE International Conference on Integrated Circuit Design and Technology, 2006 : ICICDT '06, Padova, Italy, 24-26, May, 2006 : proceedings |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2006 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design
Computer-aided design Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
9781509094172
1509094172 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910145607103321 |
| [Place of publication not identified], : IEEE, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2007 IEEE International Conference on Integrated Circuit Design and Technology : Austin, Texas, May 30-June 1, 2007 : proceedings / / sponsored by IEEE Central Texas Station ... [et al.]
| 2007 IEEE International Conference on Integrated Circuit Design and Technology : Austin, Texas, May 30-June 1, 2007 : proceedings / / sponsored by IEEE Central Texas Station ... [et al.] |
| Pubbl/distr/stampa | IEEE |
| Disciplina | 621.3815 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design
Computer-aided design |
| ISBN | 1-5090-8724-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
2007 IEEE International Conference on Integrated Circuit Design and Technology
Electromagnetics in Advanced Applications |
| Record Nr. | UNISA-996280032303316 |
| IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2007 IEEE International Conference on Integrated Circuit Design and Technology : Austin, Texas, May 30-June 1, 2007 : proceedings / / sponsored by IEEE Central Texas Station ... [et al.]
| 2007 IEEE International Conference on Integrated Circuit Design and Technology : Austin, Texas, May 30-June 1, 2007 : proceedings / / sponsored by IEEE Central Texas Station ... [et al.] |
| Pubbl/distr/stampa | IEEE |
| Disciplina | 621.3815 |
| Soggetto topico |
Integrated circuits - Very large scale integration - Design
Computer-aided design |
| ISBN |
9781509087242
1509087249 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
2007 IEEE International Conference on Integrated Circuit Design and Technology
Electromagnetics in Advanced Applications |
| Record Nr. | UNINA-9910143016903321 |
| IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2008 IEEE International Conference on IC Design and Technology and Tutorial
| 2008 IEEE International Conference on IC Design and Technology and Tutorial |
| Pubbl/distr/stampa | [Place of publication not identified], : I E E E, 2008 |
| Descrizione fisica | 1 online resource |
| Disciplina | 620.00420285 |
| Soggetto topico |
Computer-aided design
Integrated circuits - Very large scale integration - Design |
| ISBN |
1-5090-7937-8
1-4244-1811-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996202465403316 |
| [Place of publication not identified], : I E E E, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2008 IEEE International Conference on IC Design and Technology and Tutorial
| 2008 IEEE International Conference on IC Design and Technology and Tutorial |
| Pubbl/distr/stampa | [Place of publication not identified], : I E E E, 2008 |
| Descrizione fisica | 1 online resource |
| Disciplina | 620.00420285 |
| Soggetto topico |
Computer-aided design
Integrated circuits - Very large scale integration - Design |
| ISBN |
9781509079377
1509079378 9781424418114 1424418119 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910145684103321 |
| [Place of publication not identified], : I E E E, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Advanced model order reduction techniques in VLSI design / / Sheldon X.-D. Tan, Lei He
| Advanced model order reduction techniques in VLSI design / / Sheldon X.-D. Tan, Lei He |
| Autore | Tan Sheldon X. D. |
| Pubbl/distr/stampa | Cambridge : , : Cambridge University Press, , 2007 |
| Descrizione fisica | 1 online resource (xviii, 240 pages) : digital, PDF file(s) |
| Disciplina | 621.395 |
| Soggetto topico | Integrated circuits - Very large scale integration - Design |
| ISBN |
1-107-17882-7
1-280-91713-X 9786610917136 0-511-32232-1 0-511-28972-3 0-511-29032-2 0-511-28841-7 1-60119-729-2 0-511-54111-2 0-511-28909-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | List of figures; List of tables; Preface; 1. Introduction; 2. Projection-based model order reduction algorithms; 3. Truncated balanced realization methods for model order reduction; 4. Passive balanced truncation of linear systems in descriptor form; 5. Passive hierarchical model order reduction; 6. Terminal reduction of linear dynamic circuits; 7. Vector potential equivalent circuit for inductance modeling; 8. Structure-preserving model order reduction; 9. Block structure-preserving reduction for RLCK circuits; 10. Model optimization and passivity enforcement; 11. General multi-port circuit realization; 12. Model order reduction for multi-terminal linear dynamic circuits; 13. Passive modeling by signal waveform shaping; References; Index. |
| Record Nr. | UNINA-9911006654403321 |
Tan Sheldon X. D.
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| Cambridge : , : Cambridge University Press, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Bio/CMOS interfaces and co-design / / by Sandro Carrara
| Bio/CMOS interfaces and co-design / / by Sandro Carrara |
| Autore | Carrara Sandro |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | New York ; ; London, : Springer, 2012 |
| Descrizione fisica | 1 online resource (265 p.) |
| Disciplina | 621.3815/2 |
| Soggetto topico |
Biochips
Biomolecules Biosensors Metal oxide semiconductors, Complementary - Design Integrated circuits - Very large scale integration - Design |
| ISBN |
1-283-86500-9
1-4614-4690-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Chemistry of Conductive Solutions -- Biochemistry of Targets and Probes -- Target/Probe interactions -- Surface Immobilization of Probes -- Nano Technology to prevent Electron Transfer -- Bio/CMOS interface for Label-free Capacitance Sensing -- nanotechnology to enhance electron transfer -- Bio/CMOS interface in Constant Bias.-Bio/CMOS interface in Voltage Scan -- Appendix 1 - Basic Chemistry -- Appendix 2 - Basic Configurations of Operational Amplifiers -- Appendix 3 - The Fourier Theorem -- Appendix 4 - The Fourier and Laplace Transforms. |
| Record Nr. | UNINA-9910437891303321 |
|
Carrara Sandro
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| New York ; ; London, : Springer, 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
System-on-chip test architectures [[electronic resource] ] : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba
| System-on-chip test architectures [[electronic resource] ] : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (893 p.) |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
WangLaung-Terng
StroudCharles E ToubaNur A |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip - Testing
Integrated circuits - Very large scale integration - Testing Integrated circuits - Very large scale integration - Design |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-10004-8
9786611100049 0-08-055680-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; System-on-Chip Test Architectures; Copyright Page; Table of Contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; Chapter 1 Introduction; 1.1 Importance of System-on-Chip Testing; 1.1.1 Yield and Reject Rate; 1.1.2 Reliability and System Availability; 1.2 Basics of SOC Testing; 1.2.1 Boundary Scan (IEEE 1149.1 Standard); 1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard); 1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687); 1.2.4 Core-Based Testing (IEEE 1500 Standard); 1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard)
1.3 Basics of Memory Testing1.4 SOC Design Examples; 1.4.1 BioMEMS Sensor; 1.4.2 Network-on-Chip Processor; 1.5 About This Book; 1.5.1 DFT Architectures; 1.5.2 New Fault Models and Advanced Techniques; 1.5.3 Yield and Reliability Enhancement; 1.5.4 Nanotechnology Testing Aspects; 1.6 Exercises; Acknowledgments; References; Chapter 2 Digital Test Architectures; 2.1 Introduction; 2.2 Scan Design; 2.2.1 Scan Architectures; 2.2.1.1 Muxed-D Scan Design; 2.2.1.2 Clocked-Scan Design; 2.2.1.3 LSSD Scan Design; 2.2.1.4 Enhanced-Scan Design; 2.2.2 Low-Power Scan Architectures 2.2.2.1 Reduced-Voltage Low-Power Scan Design2.2.2.2 Reduced-Frequency Low-Power Scan Design; 2.2.2.3 Multi-Phase or Multi-Duty Low-Power Scan Design; 2.2.2.4 Bandwidth-Matching Low-Power Scan Design; 2.2.2.5 Hybrid Low-Power Scan Design; 2.2.3 At-Speed Scan Architectures; 2.3 Logic Built-In Self-Test; 2.3.1 Logic BIST Architectures; 2.3.1.1 Self-Testing Using MISR and Parallel SRSG (STUMPS); 2.3.1.2 Concurrent Built-In Logic Block Observer (CBILBO); 2.3.2 Coverage-Driven Logic BIST Architectures; 2.3.2.1 Weighted Pattern Generation; 2.3.2.2 Test Point Insertion; 2.3.2.3 Mixed-Mode BIST 2.3.2.4 Hybrid BIST2.3.3 Low-Power Logic BIST Architectures; 2.3.3.1 Low-Transition BIST Design; 2.3.3.2 Test-Vector-Inhibiting BIST Design; 2.3.3.3 Modified LFSR Low-Power BIST Design; 2.3.4 At-Speed Logic BIST Architectures; 2.3.4.1 Single-Capture; 2.3.4.2 Skewed-Load; 2.3.4.3 Double-Capture; 2.3.5 Industry Practices; 2.4 Test Compression; 2.4.1 Circuits for Test Stimulus Compression; 2.4.1.1 Linear-Decompression-Based Schemes; 2.4.1.2 Broadcast-Scan-Based Schemes; 2.4.1.3 Comparison; 2.4.2 Circuits for Test Response Compaction; 2.4.2.1 Space Compaction; 2.4.2.2 Time Compaction 2.4.2.3 Mixed Time and Space Compaction2.4.3 Low-Power Test Compression Architectures; 2.4.4 Industry Practices; 2.5 Random-Access Scan Design; 2.5.1 Random-Access Scan Architectures; 2.5.1.1 Progressive Random-Access Scan Design; 2.5.1.2 Shift-Addressable Random-Access Scan Design; 2.5.2 Test Compression RAS Architectures; 2.5.3 At-Speed RAS Architectures; 2.6 Concluding Remarks; 2.7 Exercises; Acknowledgments; References; Chapter 3 Fault-Tolerant Design; 3.1 Introduction; 3.2 Fundamentals of Fault Tolerance; 3.2.1 Reliability; 3.2.2 Mean Time to Failure (MTTF); 3.2.3 Maintainability 3.2.4 Availability |
| Record Nr. | UNINA-9910451492103321 |
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
System-on-chip test architectures [[electronic resource] ] : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba
| System-on-chip test architectures [[electronic resource] ] : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 |
| Descrizione fisica | 1 online resource (893 p.) |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
WangLaung-Terng
StroudCharles E ToubaNur A |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Systems on a chip - Testing
Integrated circuits - Very large scale integration - Testing Integrated circuits - Very large scale integration - Design |
| ISBN |
1-281-10004-8
9786611100049 0-08-055680-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; System-on-Chip Test Architectures; Copyright Page; Table of Contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; Chapter 1 Introduction; 1.1 Importance of System-on-Chip Testing; 1.1.1 Yield and Reject Rate; 1.1.2 Reliability and System Availability; 1.2 Basics of SOC Testing; 1.2.1 Boundary Scan (IEEE 1149.1 Standard); 1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard); 1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687); 1.2.4 Core-Based Testing (IEEE 1500 Standard); 1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard)
1.3 Basics of Memory Testing1.4 SOC Design Examples; 1.4.1 BioMEMS Sensor; 1.4.2 Network-on-Chip Processor; 1.5 About This Book; 1.5.1 DFT Architectures; 1.5.2 New Fault Models and Advanced Techniques; 1.5.3 Yield and Reliability Enhancement; 1.5.4 Nanotechnology Testing Aspects; 1.6 Exercises; Acknowledgments; References; Chapter 2 Digital Test Architectures; 2.1 Introduction; 2.2 Scan Design; 2.2.1 Scan Architectures; 2.2.1.1 Muxed-D Scan Design; 2.2.1.2 Clocked-Scan Design; 2.2.1.3 LSSD Scan Design; 2.2.1.4 Enhanced-Scan Design; 2.2.2 Low-Power Scan Architectures 2.2.2.1 Reduced-Voltage Low-Power Scan Design2.2.2.2 Reduced-Frequency Low-Power Scan Design; 2.2.2.3 Multi-Phase or Multi-Duty Low-Power Scan Design; 2.2.2.4 Bandwidth-Matching Low-Power Scan Design; 2.2.2.5 Hybrid Low-Power Scan Design; 2.2.3 At-Speed Scan Architectures; 2.3 Logic Built-In Self-Test; 2.3.1 Logic BIST Architectures; 2.3.1.1 Self-Testing Using MISR and Parallel SRSG (STUMPS); 2.3.1.2 Concurrent Built-In Logic Block Observer (CBILBO); 2.3.2 Coverage-Driven Logic BIST Architectures; 2.3.2.1 Weighted Pattern Generation; 2.3.2.2 Test Point Insertion; 2.3.2.3 Mixed-Mode BIST 2.3.2.4 Hybrid BIST2.3.3 Low-Power Logic BIST Architectures; 2.3.3.1 Low-Transition BIST Design; 2.3.3.2 Test-Vector-Inhibiting BIST Design; 2.3.3.3 Modified LFSR Low-Power BIST Design; 2.3.4 At-Speed Logic BIST Architectures; 2.3.4.1 Single-Capture; 2.3.4.2 Skewed-Load; 2.3.4.3 Double-Capture; 2.3.5 Industry Practices; 2.4 Test Compression; 2.4.1 Circuits for Test Stimulus Compression; 2.4.1.1 Linear-Decompression-Based Schemes; 2.4.1.2 Broadcast-Scan-Based Schemes; 2.4.1.3 Comparison; 2.4.2 Circuits for Test Response Compaction; 2.4.2.1 Space Compaction; 2.4.2.2 Time Compaction 2.4.2.3 Mixed Time and Space Compaction2.4.3 Low-Power Test Compression Architectures; 2.4.4 Industry Practices; 2.5 Random-Access Scan Design; 2.5.1 Random-Access Scan Architectures; 2.5.1.1 Progressive Random-Access Scan Design; 2.5.1.2 Shift-Addressable Random-Access Scan Design; 2.5.2 Test Compression RAS Architectures; 2.5.3 At-Speed RAS Architectures; 2.6 Concluding Remarks; 2.7 Exercises; Acknowledgments; References; Chapter 3 Fault-Tolerant Design; 3.1 Introduction; 3.2 Fundamentals of Fault Tolerance; 3.2.1 Reliability; 3.2.2 Mean Time to Failure (MTTF); 3.2.3 Maintainability 3.2.4 Availability |
| Record Nr. | UNINA-9910785095503321 |
| Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
