Pubbl/distr/stampa	[Place of publication not identified], : IEEE, 2008
Disciplina	005.8
Soggetto topico	Computers - Design and construction - Circuits Integrated circuits - Verification Computer security Electronic security systems Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering
ISBN	1-5090-7858-4
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Record Nr.	UNISA-996205031403316

Pubbl/distr/stampa	[Place of publication not identified], : IEEE, 2008
Descrizione fisica	1 online resource (110 pages)
Soggetto topico	Microprocessors - Testing Systems on a chip - Testing Integrated circuits - Verification
ISBN	1-5090-7784-7
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Record Nr.	UNISA-996213969703316

Edizione	[Neuerscheinung]
Pubbl/distr/stampa	Berlin, Germany : , : VDE Verlag, , 2019
Descrizione fisica	1 online resource (9 pages)
Disciplina	621.392
Soggetto topico	Computer hardware description languages Integrated circuits - Verification System design
ISBN	3-8007-4946-7
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Record Nr.	UNISA-996575445603316

Autore	Wile Bruce
Pubbl/distr/stampa	Amsterdam ; ; Boston, : Elsevier/Morgan Kaufmann, c2005
Descrizione fisica	1 online resource (702 p.)
Disciplina	621.3815/48
Altri autori (Persone)	GossJohn C RoesnerW (Wolfgang)
Collana	Systems on Silicon
Soggetto topico	Circuits integrats - Verificació Integrated circuits - Verification Computer engineering
Soggetto genere / forma	Electronic books.
ISBN	1-281-00839-7 9786611008390 1-4237-2233-7 9780080476643 0-08-047664-3
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Cover; Author Bios; FOREWORD; Table of contents; PREFACE; ACKNOWLEDGEMENTS; PART I: INTRODUCTION TO VERIFICATION; PART II: SIMULATION-BASED VERIFICATION; PART III: FORMAL VERIFICATION; PART IV: COMPREHENSIVE VERIFICATION; PART V: CASE STUDIES; VERIFICATION GLOSSARY; REFERENCES; SUBJECT INDEX
Record Nr.	UNINA-9910458499603321

Edizione	[1st ed. 1999.]
Pubbl/distr/stampa	Berlin : , : Springer, , [1999]
Descrizione fisica	1 online resource (XII, 376 p.)
Disciplina	621.395
Collana	Lecture notes in computer science
Soggetto topico	Integrated circuits - Very large scale integration - Computer-aided design Integrated circuits - Verification
ISBN	3-540-48153-2
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Invited Talks -- Esterel and Jazz : Two Synchronous Languages for Circuit Design -- Design Process of Embedded Automotive Systems—Using Model Checking for Correct Specifications -- Proof of Microprocessors -- A Proof of Correctness of a Processor Implementing Tomasulo’s Algorithm without a Reorder Buffer -- Formal Verification of Explicitly Parallel Microprocessors -- Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic -- Model Checking -- Model Checking TLA+ Specifications -- Efficient Decompositional Model Checking for Regular Timing Diagrams -- Vacuity Detection in Temporal Model Checking -- Formal Methods and Industrial Applications -- Using Symbolic Model Checking to Verify the Railway Stations of Hoorn-Kersenboogerd and Heerhugowaard -- Practical Application of Formal Verification Techniques on a Frame Mux/Demux Chip from Nortel Semiconductors -- Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics -- Abstraction and Compositional Techniques -- From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking -- Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction -- Abstract BDDs: A Technique for Using Abstraction in Model Checking -- Theorem Proving Related Approaches -- Formal Synthesis at the Algorithmic Level -- Xs Are for Trajectory Evaluation, Booleans Are for Theorem Proving -- Verification of Infinite State Systems by Compositional Model Checking -- Symbolic Simulation/Symbolic Traversal -- Formal Verification of Designs with Complex Control by Symbolic Simulation -- Hints to Accelerate Symbolic Traversal -- Specification Languages and Methodologies -- Modeling and Checking Networks of Communicating Real-Time Processes -- ”Have I Written Enough Properties?” - A Method of Comparison Between Specification and Implementation -- Program Slicing of Hardware Description Languages -- Posters -- Results of the Verification of a Complex Pipelined Machine Model -- Hazard—Freedom Checking in Speed—Independent Systems -- Yet Another Look at LTL Model Checking -- Verification of Finite-State-Machine Refinements Using a Symbolic Methodology -- Refinement and Property Checking in High-Level Synthesis Using Attribute Grammars -- A Systematic Incrementalization Technique and Its Application to Hardware Design -- Bisimulation and Model Checking -- Circular Compositional Reasoning about Liveness -- Symbolic Simulation of Microprocessor Models Using Type Classes in Haskell -- Exploiting Retiming in a Guided Simulation Based Validation Methodology -- Fault Models for Embedded Systems -- Validation of Object-Oriented Concurrent Designs by Model Checking.
Record Nr.	UNINA-9910143647603321