Advanced interconnects for ULSI technology [[electronic resource] /] / edited by Mikhail Baklanov, Paul S. Ho and Ehrenfried Zschech
| Advanced interconnects for ULSI technology [[electronic resource] /] / edited by Mikhail Baklanov, Paul S. Ho and Ehrenfried Zschech |
| Edizione | [2nd ed.] |
| Pubbl/distr/stampa | Chichester, West Susex, : Wiley, 2012 |
| Descrizione fisica | 1 online resource (615 p.) |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
BaklanovMikhail
HoP. S ZschechEhrenfried |
| Soggetto topico |
Integrated circuits - Ultra large scale integration
Interconnects (Integrated circuit technology) |
| ISBN |
1-119-96686-8
1-119-96367-2 1-280-59080-7 9786613620637 1-119-96324-9 |
| Classificazione | TEC008050 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Advanced Interconnects for ULSI Technology; Contents; About the Editors; List of Contributors; Preface; Abbreviations; Section I Low-k Materials; 1 Low-k Materials: Recent Advances; 1.1 Introduction; 1.2 Integration Challenges; 1.2.1 Process-Induced Damage; 1.2.2 Mechanical Properties; 1.3 Processing Approaches to Existing Integration Issues; 1.3.1 Post-deposition Treatments; 1.3.2 Prevention or Repair of Plasma-Induced Processing Damage; 1.3.3 Multilayer Structures; 1.4 Material Advances to Overcome Current Limitations; 1.4.1 Silica Zeolites; 1.4.2 Hybrid Organic-Inorganic: Oxycarbosilanes
1.5 ConclusionReferences; 2 Ultra-Low-k by CVD: Deposition and Curing; 2.1 Introduction; 2.2 Porogen Approach by PECVD; 2.2.1 Precursors and Deposition Conditions; 2.2.2 Mystery Still Unsolved: From Porogens to Pores; 2.3 UV Curing; 2.3.1 General Overview of Curing; 2.3.2 UV Curing Mechanisms; 2.4 Impact of Curing on Structure and Physical Properties: Benefits of UV Curing; 2.4.1 Porosity; 2.4.2 Chemical Structure and Mechanical Properties; 2.4.3 Electrical Properties; 2.5 Limit/Issues with the Porogen Approach; 2.5.1 Porosity Creation Limit; 2.5.2 Porogen Residues; 2.6 Future of CVD Low-k 2.6.1 New Matrix Precursor2.6.2 Other Deposition Strategies; 2.6.3 New Deposition Techniques; 2.7 Material Engineering: Adaptation to Integration Schemes; 2.8 Conclusion; References; 3 Plasma Processing of Low-k Dielectrics; 3.1 Introduction; 3.2 Materials and Equipment; 3.3 Process Results Characterization; 3.4 Interaction of Low-k Dielectrics with Plasma; 3.4.1 Low-k Etch Chemistries; 3.4.2 Patterning Strategies and Masking Materials; 3.4.3 Etch Mechanisms; 3.5 Mechanisms of Plasma Damage; 3.5.1 Gap Structure Studies; 3.5.2 Effect of Radical Density; 3.5.3 Effect of Ion Energy 3.5.4 Effect of Photon Energy and Intensity3.5.5 Plasma Damage by Oxidative Radicals; 3.5.6 Hydrogen-Based Plasma; 3.5.7 Minimization of Plasma Damage; 3.6 Dielectric Recovery; 3.6.1 CH4 Beam Treatment; 3.6.2 Dielectric Recovery by Silylation; 3.6.3 UV Radiation; 3.7 Conclusions; References; 4 Wet Clean Applications in Porous Low-k Patterning Processes; 4.1 Introduction; 4.2 Silica and Porous Hybrid Dielectric Materials; 4.3 Impact of Plasma and Subsequent Wet Clean Processes on the Stability of Porous Low-k Dielectrics; 4.3.1 Stability in Pure Chemical Solutions 4.3.2 Stability in Commercial Chemistries4.3.3 Hydrophobicity of Hybrid Low-k Materials; 4.4 Removal of Post-Etch Residues and Copper Surface Cleaning; 4.5 Plasma Modification and Removal of Post-Etch 193 nm Photoresist; 4.5.1 Modification of 193 nm Photoresist by Plasma Etch; 4.5.2 Wet Removal of 193 nm Photoresist; Acknowledgments; References; Section II Conductive Layers and Barriers; 5 Copper Electroplating for On-Chip Metallization; 5.1 Introduction; 5.2 Copper Electroplating Techniques; 5.3 Copper Electroplating Superfill; 5.3.1 The Role of Accelerator; 5.3.2 The Role of Suppressor 5.3.3 The Role of Leveler |
| Record Nr. | UNINA-9910141346803321 |
| Chichester, West Susex, : Wiley, 2012 | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Advanced interconnects for ULSI technology / / edited by Mikhail Baklanov, Paul S. Ho and Ehrenfried Zschech
| Advanced interconnects for ULSI technology / / edited by Mikhail Baklanov, Paul S. Ho and Ehrenfried Zschech |
| Edizione | [2nd ed.] |
| Pubbl/distr/stampa | Chichester, West Susex, : Wiley, 2012 |
| Descrizione fisica | 1 online resource (615 p.) |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
BaklanovMikhail
HoP. S ZschechEhrenfried |
| Soggetto topico |
Integrated circuits - Ultra large scale integration
Interconnects (Integrated circuit technology) |
| ISBN |
9786613620637
9781119966869 1119966868 9781119963677 1119963672 9781280590801 1280590807 9781119963240 1119963249 |
| Classificazione | TEC008050 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Advanced Interconnects for ULSI Technology; Contents; About the Editors; List of Contributors; Preface; Abbreviations; Section I Low-k Materials; 1 Low-k Materials: Recent Advances; 1.1 Introduction; 1.2 Integration Challenges; 1.2.1 Process-Induced Damage; 1.2.2 Mechanical Properties; 1.3 Processing Approaches to Existing Integration Issues; 1.3.1 Post-deposition Treatments; 1.3.2 Prevention or Repair of Plasma-Induced Processing Damage; 1.3.3 Multilayer Structures; 1.4 Material Advances to Overcome Current Limitations; 1.4.1 Silica Zeolites; 1.4.2 Hybrid Organic-Inorganic: Oxycarbosilanes
1.5 ConclusionReferences; 2 Ultra-Low-k by CVD: Deposition and Curing; 2.1 Introduction; 2.2 Porogen Approach by PECVD; 2.2.1 Precursors and Deposition Conditions; 2.2.2 Mystery Still Unsolved: From Porogens to Pores; 2.3 UV Curing; 2.3.1 General Overview of Curing; 2.3.2 UV Curing Mechanisms; 2.4 Impact of Curing on Structure and Physical Properties: Benefits of UV Curing; 2.4.1 Porosity; 2.4.2 Chemical Structure and Mechanical Properties; 2.4.3 Electrical Properties; 2.5 Limit/Issues with the Porogen Approach; 2.5.1 Porosity Creation Limit; 2.5.2 Porogen Residues; 2.6 Future of CVD Low-k 2.6.1 New Matrix Precursor2.6.2 Other Deposition Strategies; 2.6.3 New Deposition Techniques; 2.7 Material Engineering: Adaptation to Integration Schemes; 2.8 Conclusion; References; 3 Plasma Processing of Low-k Dielectrics; 3.1 Introduction; 3.2 Materials and Equipment; 3.3 Process Results Characterization; 3.4 Interaction of Low-k Dielectrics with Plasma; 3.4.1 Low-k Etch Chemistries; 3.4.2 Patterning Strategies and Masking Materials; 3.4.3 Etch Mechanisms; 3.5 Mechanisms of Plasma Damage; 3.5.1 Gap Structure Studies; 3.5.2 Effect of Radical Density; 3.5.3 Effect of Ion Energy 3.5.4 Effect of Photon Energy and Intensity3.5.5 Plasma Damage by Oxidative Radicals; 3.5.6 Hydrogen-Based Plasma; 3.5.7 Minimization of Plasma Damage; 3.6 Dielectric Recovery; 3.6.1 CH4 Beam Treatment; 3.6.2 Dielectric Recovery by Silylation; 3.6.3 UV Radiation; 3.7 Conclusions; References; 4 Wet Clean Applications in Porous Low-k Patterning Processes; 4.1 Introduction; 4.2 Silica and Porous Hybrid Dielectric Materials; 4.3 Impact of Plasma and Subsequent Wet Clean Processes on the Stability of Porous Low-k Dielectrics; 4.3.1 Stability in Pure Chemical Solutions 4.3.2 Stability in Commercial Chemistries4.3.3 Hydrophobicity of Hybrid Low-k Materials; 4.4 Removal of Post-Etch Residues and Copper Surface Cleaning; 4.5 Plasma Modification and Removal of Post-Etch 193 nm Photoresist; 4.5.1 Modification of 193 nm Photoresist by Plasma Etch; 4.5.2 Wet Removal of 193 nm Photoresist; Acknowledgments; References; Section II Conductive Layers and Barriers; 5 Copper Electroplating for On-Chip Metallization; 5.1 Introduction; 5.2 Copper Electroplating Techniques; 5.3 Copper Electroplating Superfill; 5.3.1 The Role of Accelerator; 5.3.2 The Role of Suppressor 5.3.3 The Role of Leveler |
| Record Nr. | UNINA-9910825297303321 |
| Chichester, West Susex, : Wiley, 2012 | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Analysis and design of digital integrated circuits : in deep submicron technology / David A. Hodges, Horace G. Jackson, Resve A. Saleh
| Analysis and design of digital integrated circuits : in deep submicron technology / David A. Hodges, Horace G. Jackson, Resve A. Saleh |
| Autore | Hodges, David A., 1937- |
| Edizione | [3rd ed.] |
| Pubbl/distr/stampa | Boston : McGraw-Hill Higher Education, 2004 |
| Descrizione fisica | xix, 580 p. : ill. ; 24 cm. |
| Disciplina | 621.3815 |
| Altri autori (Persone) |
Jackson, Horace G.
Saleh, Resve A., 1957- |
| Collana | McGraw-Hill series in electrical engineering |
| Soggetto topico |
Digital integrated circuits - Design and construction
Integrated circuits - Ultra large scale integration Electric circuit analysis |
| ISBN | 0072283653 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISALENTO-991003001019707536 |
Hodges, David A., 1937-
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||
| Boston : McGraw-Hill Higher Education, 2004 | ||
| Lo trovi qui: Univ. del Salento | ||
| ||
Electromigration in ULSI interconnections [[electronic resource] /] / Cher Ming Tan
| Electromigration in ULSI interconnections [[electronic resource] /] / Cher Ming Tan |
| Autore | Tan Cher Ming <1959-> |
| Pubbl/distr/stampa | Hackensack, N.J., : World Scientific, c2010 |
| Descrizione fisica | 1 online resource (312 p.) |
| Disciplina | 621.395 |
| Collana | International series on advances in solid state electronics and technology (ASSET) |
| Soggetto topico |
Integrated circuits - Ultra large scale integration
Electrodiffusion |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-283-14371-2
9786613143716 981-4273-33-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Preface; Contents; 1. Introduction; 2. History of Electromigration; 3. Experimental Studies of Al Interconnections; 4. Experimental Studies of Cu Interconnections; 5. Numerical Modeling of Electromigration; 6. Future Challenges; Index; Biography |
| Record Nr. | UNINA-9910456216003321 |
Tan Cher Ming <1959->
|
||
| Hackensack, N.J., : World Scientific, c2010 | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electromigration in ULSI interconnections [[electronic resource] /] / Cher Ming Tan
| Electromigration in ULSI interconnections [[electronic resource] /] / Cher Ming Tan |
| Autore | Tan Cher Ming <1959-> |
| Pubbl/distr/stampa | Hackensack, N.J., : World Scientific, c2010 |
| Descrizione fisica | 1 online resource (312 p.) |
| Disciplina | 621.395 |
| Collana | International series on advances in solid state electronics and technology (ASSET) |
| Soggetto topico |
Integrated circuits - Ultra large scale integration
Electrodiffusion |
| ISBN |
1-283-14371-2
9786613143716 981-4273-33-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Preface; Contents; 1. Introduction; 2. History of Electromigration; 3. Experimental Studies of Al Interconnections; 4. Experimental Studies of Cu Interconnections; 5. Numerical Modeling of Electromigration; 6. Future Challenges; Index; Biography |
| Record Nr. | UNINA-9910780711903321 |
Tan Cher Ming <1959->
|
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| Hackensack, N.J., : World Scientific, c2010 | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ULSI semiconductor technology atlas / / Chih-Hang Tung, George T.T. Sheng, Chih-Yuan Lu [[electronic resource]]
| ULSI semiconductor technology atlas / / Chih-Hang Tung, George T.T. Sheng, Chih-Yuan Lu [[electronic resource]] |
| Autore | Tung Chih-Hang <1963-> |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley, c2003 |
| Descrizione fisica | 1 online resource (xii, 666 p. ) : ill. ; |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
ShengGeorge T. T
LuChih-Yuan <1950-> |
| Soggetto topico |
Integrated circuits - Ultra large scale integration
Electron microscopy Electrical Engineering Electrical & Computer Engineering Engineering & Applied Sciences |
| Soggetto genere / forma | Electronic books |
| ISBN |
1-280-55680-3
9786610556809 0-471-66878-8 0-470-35744-4 0-471-66879-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910146058303321 |
Tung Chih-Hang <1963->
|
||
| Hoboken, NJ, : John Wiley, c2003 | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ULSI semiconductor technology atlas / / Chih-Hang Tung, George T.T. Sheng, Chih-Yuan Lu [[electronic resource]]
| ULSI semiconductor technology atlas / / Chih-Hang Tung, George T.T. Sheng, Chih-Yuan Lu [[electronic resource]] |
| Autore | Tung Chih-Hang <1963-> |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley, c2003 |
| Descrizione fisica | 1 online resource (xii, 666 p. ) : ill. ; |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
ShengGeorge T. T
LuChih-Yuan <1950-> |
| Soggetto topico |
Integrated circuits - Ultra large scale integration
Electron microscopy Electrical Engineering Electrical & Computer Engineering Engineering & Applied Sciences |
| ISBN |
1-280-55680-3
9786610556809 0-471-66878-8 0-470-35744-4 0-471-66879-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910830177003321 |
Tung Chih-Hang <1963->
|
||
| Hoboken, NJ, : John Wiley, c2003 | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ULSI semiconductor technology atlas / / Chih-Hang Tung, George T.T. Sheng, Chih-Yuan Lu [[electronic resource]]
| ULSI semiconductor technology atlas / / Chih-Hang Tung, George T.T. Sheng, Chih-Yuan Lu [[electronic resource]] |
| Autore | Tung Chih-Hang <1963-> |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley, c2003 |
| Descrizione fisica | 1 online resource (xii, 666 p. ) : ill. ; |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
ShengGeorge T. T
LuChih-Yuan <1950-> |
| Soggetto topico |
Integrated circuits - Ultra large scale integration
Electron microscopy Electrical Engineering Electrical & Computer Engineering Engineering & Applied Sciences |
| ISBN |
1-280-55680-3
9786610556809 0-471-66878-8 0-470-35744-4 0-471-66879-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9911019117403321 |
Tung Chih-Hang <1963->
|
||
| Hoboken, NJ, : John Wiley, c2003 | ||
| Lo trovi qui: Univ. Federico II | ||
| ||