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ESD [[electronic resource] ] : design and synthesis / / Steven H. Voldman
| ESD [[electronic resource] ] : design and synthesis / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K., : Wiley, 2011 |
| Descrizione fisica | 1 online resource (292 p.) |
| Disciplina | 621.3815/2 |
| Collana | ESD series |
| Soggetto topico |
Semiconductors - Protection
Integrated circuits - Protection Electrostatics Analog electronic systems - Design and construction |
| ISBN |
1-283-40527-X
9786613405272 1-119-99114-5 1-119-99113-7 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD Design and Synthesis; Contents; About the Author; Preface; Acknowledgments; 1 ESD Design Synthesis; 1.1 ESD DESIGN SYNTHESIS AND ARCHITECTURE FLOW; 1.1.1 Top-Down ESD Design; 1.1.2 Bottom-Up ESD Design; 1.1.3 Top-Down ESD Design - Memory Semiconductor Chips; 1.1.4 Top-Down ESD Design - ASIC Design System; 1.2 ESD DESIGN - THE SIGNAL PATH AND THE ALTERNATE CURRENT PATH; 1.3 ESD ELECTRICAL CIRCUIT AND SCHEMATIC ARCHITECTURE CONCEPTS; 1.3.1 The Ideal ESD Network and the Current-Voltage DC Design Window; 1.3.2 The ESD Design Window
1.3.3 The Ideal ESD Networks in the Frequency Domain Design Window1.4 MAPPING SEMICONDUCTOR CHIPS AND ESD DESIGNS; 1.4.1 Mapping Across Semiconductor Fabricators; 1.4.2 ESD Design Mapping Across Technology Generations; 1.4.3 Mapping from Bipolar Technology to CMOS Technology; 1.4.4 Mapping from Digital CMOS Technology to Mixed Signal Analog-Digital CMOS Technology; 1.4.5 Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI); 1.4.6 ESD Design - Mapping CMOS to RF CMOS Technology; 1.5 ESD CHIP ARCHITECTURE, AND ESD TEST STANDARDS; 1.5.1 ESD Chip Architecture and ESD Testing 1.6 ESD TESTING1.6.1 ESD Qualification Testing; 1.6.2 ESD Test Models; 1.6.3 ESD Characterization Testing; 1.6.4 TLP Testing; 1.7 ESD CHIP ARCHITECTURE AND ESD ALTERNATIVE CURRENT PATHS; 1.7.1 ESD Circuits, I/O, and Cores; 1.7.2 ESD Signal Pin Circuits; 1.7.3 ESD Power Clamp Networks; 1.7.4 ESD Rail-to-Rail Circuits; 1.7.5 ESD Design and Noise; 1.7.6 Internal Signal Path ESD Networks; 1.7.7 Cross-Domain ESD Networks; 1.8 ESD NETWORKS, SEQUENCING, AND CHIP ARCHITECTURE; 1.9 ESD DESIGN SYNTHESIS - LATCHUP-FREE ESD NETWORKS; 1.10 ESD DESIGN CONCEPTS - BUFFERING - INTER-DEVICE 1.11 ESD DESIGN CONCEPTS - BALLASTING - INTER-DEVICE1.12 ESD DESIGN CONCEPTS - BALLASTING - INTRA-DEVICE; 1.13 ESD DESIGN CONCEPTS - DISTRIBUTED LOAD TECHNIQUES; 1.14 ESD DESIGN CONCEPTS - DUMMY CIRCUITS; 1.15 ESD DESIGN CONCEPTS - POWER SUPPLY DE-COUPLING; 1.16 ESD DESIGN CONCEPTS - FEEDBACK LOOP DE-COUPLING; 1.17 ESD LAYOUT AND FLOORPLAN-RELATED CONCEPTS; 1.17.1 Design Symmetry; 1.17.2 Design Segmentation; 1.17.3 ESD Design Concepts - Utilization of Empty Space; 1.17.4 ESD Design Synthesis - Across Chip Line Width Variation (ACLV); 1.17.5 ESD Design Concepts - Dummy Shapes 1.17.6 ESD Design Concepts - Dummy Masks1.17.7 ESD Design Concepts - Adjacency; 1.18 ESD DESIGN CONCEPTS - ANALOG CIRCUIT TECHNIQUES; 1.19 ESD DESIGN CONCEPTS - WIRE BONDS; 1.20 DESIGN RULES; 1.20.1 ESD Design Rule Checking (DRC); 1.20.2 ESD Layout vs. Schematic (LVS); 1.20.3 Electrical Resistance Checking (ERC); 1.21 SUMMARY AND CLOSING COMMENTS; PROBLEMS; REFERENCES; 2 ESD Architecture and Floorplanning; 2.1 ESD DESIGN FLOORPLAN; 2.2 PERIPHERAL I/O DESIGN; 2.2.1 Pad-Limited Peripheral I/O Design Architecture; 2.2.2 Pad-Limited Peripheral I/O Design Architecture - Staggered I/O 2.2.3 Core-Limited Peripheral I/O Design Architecture |
| Record Nr. | UNINA-9910131049403321 |
Voldman Steven H
|
||
| Chichester, West Sussex, U.K., : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD : design and synthesis / / Steven H. Voldman
| ESD : design and synthesis / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K., : Wiley, 2011 |
| Descrizione fisica | 1 online resource (292 p.) |
| Disciplina | 621.3815/2 |
| Collana | ESD series |
| Soggetto topico |
Semiconductors - Protection
Integrated circuits - Protection Electrostatics Analog electronic systems - Design and construction |
| ISBN |
1-283-40527-X
9786613405272 1-119-99114-5 1-119-99113-7 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD Design and Synthesis; Contents; About the Author; Preface; Acknowledgments; 1 ESD Design Synthesis; 1.1 ESD DESIGN SYNTHESIS AND ARCHITECTURE FLOW; 1.1.1 Top-Down ESD Design; 1.1.2 Bottom-Up ESD Design; 1.1.3 Top-Down ESD Design - Memory Semiconductor Chips; 1.1.4 Top-Down ESD Design - ASIC Design System; 1.2 ESD DESIGN - THE SIGNAL PATH AND THE ALTERNATE CURRENT PATH; 1.3 ESD ELECTRICAL CIRCUIT AND SCHEMATIC ARCHITECTURE CONCEPTS; 1.3.1 The Ideal ESD Network and the Current-Voltage DC Design Window; 1.3.2 The ESD Design Window
1.3.3 The Ideal ESD Networks in the Frequency Domain Design Window1.4 MAPPING SEMICONDUCTOR CHIPS AND ESD DESIGNS; 1.4.1 Mapping Across Semiconductor Fabricators; 1.4.2 ESD Design Mapping Across Technology Generations; 1.4.3 Mapping from Bipolar Technology to CMOS Technology; 1.4.4 Mapping from Digital CMOS Technology to Mixed Signal Analog-Digital CMOS Technology; 1.4.5 Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI); 1.4.6 ESD Design - Mapping CMOS to RF CMOS Technology; 1.5 ESD CHIP ARCHITECTURE, AND ESD TEST STANDARDS; 1.5.1 ESD Chip Architecture and ESD Testing 1.6 ESD TESTING1.6.1 ESD Qualification Testing; 1.6.2 ESD Test Models; 1.6.3 ESD Characterization Testing; 1.6.4 TLP Testing; 1.7 ESD CHIP ARCHITECTURE AND ESD ALTERNATIVE CURRENT PATHS; 1.7.1 ESD Circuits, I/O, and Cores; 1.7.2 ESD Signal Pin Circuits; 1.7.3 ESD Power Clamp Networks; 1.7.4 ESD Rail-to-Rail Circuits; 1.7.5 ESD Design and Noise; 1.7.6 Internal Signal Path ESD Networks; 1.7.7 Cross-Domain ESD Networks; 1.8 ESD NETWORKS, SEQUENCING, AND CHIP ARCHITECTURE; 1.9 ESD DESIGN SYNTHESIS - LATCHUP-FREE ESD NETWORKS; 1.10 ESD DESIGN CONCEPTS - BUFFERING - INTER-DEVICE 1.11 ESD DESIGN CONCEPTS - BALLASTING - INTER-DEVICE1.12 ESD DESIGN CONCEPTS - BALLASTING - INTRA-DEVICE; 1.13 ESD DESIGN CONCEPTS - DISTRIBUTED LOAD TECHNIQUES; 1.14 ESD DESIGN CONCEPTS - DUMMY CIRCUITS; 1.15 ESD DESIGN CONCEPTS - POWER SUPPLY DE-COUPLING; 1.16 ESD DESIGN CONCEPTS - FEEDBACK LOOP DE-COUPLING; 1.17 ESD LAYOUT AND FLOORPLAN-RELATED CONCEPTS; 1.17.1 Design Symmetry; 1.17.2 Design Segmentation; 1.17.3 ESD Design Concepts - Utilization of Empty Space; 1.17.4 ESD Design Synthesis - Across Chip Line Width Variation (ACLV); 1.17.5 ESD Design Concepts - Dummy Shapes 1.17.6 ESD Design Concepts - Dummy Masks1.17.7 ESD Design Concepts - Adjacency; 1.18 ESD DESIGN CONCEPTS - ANALOG CIRCUIT TECHNIQUES; 1.19 ESD DESIGN CONCEPTS - WIRE BONDS; 1.20 DESIGN RULES; 1.20.1 ESD Design Rule Checking (DRC); 1.20.2 ESD Layout vs. Schematic (LVS); 1.20.3 Electrical Resistance Checking (ERC); 1.21 SUMMARY AND CLOSING COMMENTS; PROBLEMS; REFERENCES; 2 ESD Architecture and Floorplanning; 2.1 ESD DESIGN FLOORPLAN; 2.2 PERIPHERAL I/O DESIGN; 2.2.1 Pad-Limited Peripheral I/O Design Architecture; 2.2.2 Pad-Limited Peripheral I/O Design Architecture - Staggered I/O 2.2.3 Core-Limited Peripheral I/O Design Architecture |
| Record Nr. | UNINA-9910813763203321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, U.K., : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD [[electronic resource] ] : failure mechanisms and models / / Steven H. Voldman
| ESD [[electronic resource] ] : failure mechanisms and models / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K. ; ; Hoboken, NJ, : J. Wiley, 2009 |
| Descrizione fisica | 1 online resource (410 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Semiconductors - Failures
Integrated circuits - Protection Integrated circuits - Testing Integrated circuits - Reliability Electric discharges Electrostatics |
| ISBN |
1-282-23713-6
9786612237133 0-470-74725-0 0-470-74726-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD Failure Mechanisms and Models; Contents; About the Author; Preface; Acknowledgments; 1 Failure Analysis and ESD; 1.1 INTRODUCTION; 1.1.1 FA Techniques for Evaluation of ESD Events; 1.1.2 Fundamental Concepts of ESD FA Methods and Practices; 1.1.3 ESD Failure: Why Do Semiconductor Chips Fail?; 1.1.4 How to Use FA to Design ESD Robust Technologies; 1.1.5 How to Use FA to Design ESD Robust Circuits; 1.1.6 How to Use FA for Temperature Prediction; 1.1.7 How to Use Failure Models for Power Prediction; 1.1.8 FA Methods, Design Rules, and ESD Ground Rules
1.1.9 FA and Semiconductor Process-Induced ESD Design Asymmetry 1.1.10 FA Methodology and Electro-thermal Simulation; 1.1.11 FA and ESD Testing Methodology; 1.1.12 FA Methodology for Evaluation of ESD Parasitics; 1.1.13 FA Methods and ESD Device Operation Verification; 1.1.14 FA Methodology to Evaluate Inter-power Rail Electrical Connectivity; 1.1.15 How to Use FA to Eliminate Failure Mechanisms; 1.2 ESD FAILURE: HOW DO MICRO-ELECTRONIC DEVICES FAIL?; 1.2.1 ESD Failure: How Do Metallurgical Junctions Fail?; 1.2.2 ESD Failure: How Do Insulators Fail?; 1.2.3 ESD Failure: How Do Metals Fail? 1.3 SENSITIVITY OF SEMICONDUCTOR COMPONENTS 1.3.1 ESD Sensitivity as a Function of Materials; 1.3.2 ESD Sensitivity as a Function of Semiconductor Devices; 1.3.3 ESD Sensitivity as a Function of Product Type; 1.3.4 ESD and Technology Scaling; 1.3.5 ESD Technology Roadmap; 1.4 HOW DO SEMICONDUCTOR CHIPS FAIL--ARE THE FAILURES RANDOM OR SYSTEMATIC?; 1.5 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 2 Failure Analysis Tools, Models, and Physics of Failure; 2.1 FA TECHNIQUES FOR EVALUATION OF ESD EVENTS; 2.2 FA TOOLS; 2.2.1 Optical Microscope; 2.2.2 Scanning Electron Microscope 2.2.3 Transmission Electron Microscope 2.2.4 Emission Microscope; 2.2.5 Thermally Induced Voltage Alteration; 2.2.6 Superconducting Quantum Interference Device Microscope; 2.2.7 Atomic Force Microscope; 2.2.8 The 2-D AFM; 2.2.9 Picosecond Current Analysis Tool; 2.2.10 Transmission Line Pulse--Pico second Current Analysis Tool; 2.3 ESD SIMULATION: ESD PULSE MODELS; 2.3.1 Human Body Model; 2.3.2 Machine Model; 2.3.3 Cassette Model; 2.3.4 Socketed Device Model; 2.3.5 Charged Board Model; 2.3.6 Cable Discharge Event; 2.3.7 IEC System-Level Pulse Model; 2.3.8 Human Metal Model 2.3.9 Transmission Line Pulse Testing 2.3.10 Very Fast Transmission Line Pulse (VF-TLP) Model; 2.3.11 Ultra-fast Transmission Line Pulse (UF-TLP) Model; 2.4 ELECTRO-THERMAL PHYSICAL MODELS; 2.4.1 Tasca Model; 2.4.2 Wunsch-Bell Model; 2.4.3 Smith-Littau Model; 2.4.4 Ash Model; 2.4.5 Arkihpov, Astvatsaturyan, Godovosyn, and Rudenko Model; 2.4.6 Dwyer, Franklin, and Campbell Model; 2.4.7 Vlasov-Sinkevitch Model; 2.5 STATISTICAL MODELS FOR ESD PREDICTION; 2.6 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 3 CMOS Failure Mechanisms; 3.1 TABLES OF CMOS ESD FAILURE MECHANISMS 3.2 LOCOS ISOLATION-DEFINED CMOS |
| Record Nr. | UNINA-9910139802703321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, U.K. ; ; Hoboken, NJ, : J. Wiley, 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD : failure mechanisms and models / / Steven H. Voldman
| ESD : failure mechanisms and models / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K. ; ; Hoboken, NJ, : J. Wiley, 2009 |
| Descrizione fisica | 1 online resource (410 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Semiconductors - Failures
Integrated circuits - Protection Integrated circuits - Testing Integrated circuits - Reliability Electric discharges Electrostatics |
| ISBN |
1-282-23713-6
9786612237133 0-470-74725-0 0-470-74726-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD Failure Mechanisms and Models; Contents; About the Author; Preface; Acknowledgments; 1 Failure Analysis and ESD; 1.1 INTRODUCTION; 1.1.1 FA Techniques for Evaluation of ESD Events; 1.1.2 Fundamental Concepts of ESD FA Methods and Practices; 1.1.3 ESD Failure: Why Do Semiconductor Chips Fail?; 1.1.4 How to Use FA to Design ESD Robust Technologies; 1.1.5 How to Use FA to Design ESD Robust Circuits; 1.1.6 How to Use FA for Temperature Prediction; 1.1.7 How to Use Failure Models for Power Prediction; 1.1.8 FA Methods, Design Rules, and ESD Ground Rules
1.1.9 FA and Semiconductor Process-Induced ESD Design Asymmetry 1.1.10 FA Methodology and Electro-thermal Simulation; 1.1.11 FA and ESD Testing Methodology; 1.1.12 FA Methodology for Evaluation of ESD Parasitics; 1.1.13 FA Methods and ESD Device Operation Verification; 1.1.14 FA Methodology to Evaluate Inter-power Rail Electrical Connectivity; 1.1.15 How to Use FA to Eliminate Failure Mechanisms; 1.2 ESD FAILURE: HOW DO MICRO-ELECTRONIC DEVICES FAIL?; 1.2.1 ESD Failure: How Do Metallurgical Junctions Fail?; 1.2.2 ESD Failure: How Do Insulators Fail?; 1.2.3 ESD Failure: How Do Metals Fail? 1.3 SENSITIVITY OF SEMICONDUCTOR COMPONENTS 1.3.1 ESD Sensitivity as a Function of Materials; 1.3.2 ESD Sensitivity as a Function of Semiconductor Devices; 1.3.3 ESD Sensitivity as a Function of Product Type; 1.3.4 ESD and Technology Scaling; 1.3.5 ESD Technology Roadmap; 1.4 HOW DO SEMICONDUCTOR CHIPS FAIL--ARE THE FAILURES RANDOM OR SYSTEMATIC?; 1.5 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 2 Failure Analysis Tools, Models, and Physics of Failure; 2.1 FA TECHNIQUES FOR EVALUATION OF ESD EVENTS; 2.2 FA TOOLS; 2.2.1 Optical Microscope; 2.2.2 Scanning Electron Microscope 2.2.3 Transmission Electron Microscope 2.2.4 Emission Microscope; 2.2.5 Thermally Induced Voltage Alteration; 2.2.6 Superconducting Quantum Interference Device Microscope; 2.2.7 Atomic Force Microscope; 2.2.8 The 2-D AFM; 2.2.9 Picosecond Current Analysis Tool; 2.2.10 Transmission Line Pulse--Pico second Current Analysis Tool; 2.3 ESD SIMULATION: ESD PULSE MODELS; 2.3.1 Human Body Model; 2.3.2 Machine Model; 2.3.3 Cassette Model; 2.3.4 Socketed Device Model; 2.3.5 Charged Board Model; 2.3.6 Cable Discharge Event; 2.3.7 IEC System-Level Pulse Model; 2.3.8 Human Metal Model 2.3.9 Transmission Line Pulse Testing 2.3.10 Very Fast Transmission Line Pulse (VF-TLP) Model; 2.3.11 Ultra-fast Transmission Line Pulse (UF-TLP) Model; 2.4 ELECTRO-THERMAL PHYSICAL MODELS; 2.4.1 Tasca Model; 2.4.2 Wunsch-Bell Model; 2.4.3 Smith-Littau Model; 2.4.4 Ash Model; 2.4.5 Arkihpov, Astvatsaturyan, Godovosyn, and Rudenko Model; 2.4.6 Dwyer, Franklin, and Campbell Model; 2.4.7 Vlasov-Sinkevitch Model; 2.5 STATISTICAL MODELS FOR ESD PREDICTION; 2.6 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 3 CMOS Failure Mechanisms; 3.1 TABLES OF CMOS ESD FAILURE MECHANISMS 3.2 LOCOS ISOLATION-DEFINED CMOS |
| Altri titoli varianti | Electrostatic discharge |
| Record Nr. | UNINA-9910817124503321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, U.K. ; ; Hoboken, NJ, : J. Wiley, 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD [[electronic resource] ] : circuits and devices / / Steven H. Voldman
| ESD [[electronic resource] ] : circuits and devices / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley, 2006 |
| Descrizione fisica | 1 online resource (414 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Integrated circuits - Protection
Electronic apparatus and appliances - Protection Static eliminators Electric discharges Electrostatics |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-118-95448-3
1-118-95449-1 1-118-95447-5 1-280-33967-5 0-470-03347-9 0-470-03006-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Electrostatic discharge -- Design synthesis -- Mosfet ESD design -- ESD design : diode design -- ESD design : passive resistors -- Passives for digital, analog, and RF applications -- Off-chip drivers and ESD -- Receiver circuits -- Silicon on insulator (SOI) ESD design -- ESD circuits : BiCMOS -- ESD power clamps -- Bipolar ESD power clamps -- Silicon-controlled rectifier power clamps. |
| Record Nr. | UNINA-9910143743003321 |
|
Voldman Steven H
|
||
| Hoboken, NJ, : John Wiley, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD : circuits and devices / / Steven H. Voldman
| ESD : circuits and devices / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley, 2006 |
| Descrizione fisica | 1 online resource (414 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Integrated circuits - Protection
Electronic apparatus and appliances - Protection Static eliminators Electric discharges Electrostatics |
| ISBN |
1-118-95448-3
1-118-95449-1 1-118-95447-5 1-280-33967-5 0-470-03347-9 0-470-03006-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Electrostatic discharge -- Design synthesis -- Mosfet ESD design -- ESD design : diode design -- ESD design : passive resistors -- Passives for digital, analog, and RF applications -- Off-chip drivers and ESD -- Receiver circuits -- Silicon on insulator (SOI) ESD design -- ESD circuits : BiCMOS -- ESD power clamps -- Bipolar ESD power clamps -- Silicon-controlled rectifier power clamps. |
| Altri titoli varianti | Circuits and devices |
| Record Nr. | UNINA-9910824563303321 |
|
Voldman Steven H
|
||
| Hoboken, NJ, : John Wiley, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD : circuits and devices / / Steven H. Voldman
| ESD : circuits and devices / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley, 2006 |
| Descrizione fisica | 1 online resource (422 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Integrated circuits - Protection
Electronic apparatus and appliances - Protection Static eliminators Electric discharges Electrostatics |
| ISBN |
1-280-28748-9
9786610287482 0-470-01350-8 0-470-01290-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD; Contents; About the Author; Preface; Acknowledgements; 1 Electrostatics and Electrothermal Physics; 1.1 Introduction; 1.2 A Time Constant Approach; 1.2.1 ESD Time Constants; 1.2.2 Time Constant Hierarchy; 1.2.3 Thermal Time Constant; 1.2.4 Thermal Diffusion; 1.2.5 Adiabatic, Thermal Diffusion Time Scale and Steady State; 1.2.6 Electroquasistatics and Magnetoquasistatics; 1.3 Instability; 1.3.1 Electrical Instability; 1.3.2 Electrothermal Instability; 1.3.3 Spatial Instability and Current Constriction; 1.4 Breakdown; 1.4.1 Paschen's Breakdown Theory; 1.4.2 Townsend's Concept
1.4.3 Toepler's Law1.5 Avalanche Breakdown; 1.5.1 Breakdown in Air; 1.5.2 Air Breakdown and Peak Currents; 1.5.3 Air Breakdown and Rise Times; 1.5.4 Mesoplasmas and Microplasmas; 1.5.5 Mesoplasma Phenomena; Problems; References; 2 Electrothermal Methods and ESD Models; 2.1 Electrothermal Methods; 2.1.1 Green's Function and Method of Images; 2.1.2 Integral Transforms of the Heat Conduction Equation; 2.1.3 Flux Potential Transfer Relations Matrix Methodology; 2.1.4 Heat Equation with Variable Conductivity; 2.1.5 Duhamel Formulation; 2.2 Electrothermal Models; 2.2.1 Tasca Model 2.2.2 Wunsch-Bell Model2.2.3 Smith-Littau Model; 2.2.4 Arkihpov-Astvatsaturyan-Godovosyn-Rudenko Model; 2.2.5 Vlasov-Sinkevitch Model; 2.2.6 Dwyer-Franklin-Campbell Model; 2.2.7 Greve Model; 2.2.8 Negative Differential Resistance Model; 2.2.9 Ash Model; 2.2.10 Statistical Models; Problems; References; 3 Semiconductor Devices and ESD; 3.1 Device Physics; 3.1.1 Nonisothermal Simulation; 3.2 Diodes; 3.2.1 Diode Equation; 3.2.2 Recombination and Generation Mechanisms; 3.3 Bipolar High-current Device Physics; 3.3.1 Bipolar Transistor Equation; 3.3.2 Kirk Effect; 3.3.3 Johnson Limit 3.4 Silicon-Controlled Rectifiers3.4.1 Regenerative Feedback; 3.5 Resistors; 3.6 MOSFET High-current Device Physics; 3.6.1 Parasitic Bipolar Transistor Equation; 3.6.2 Avalanche Breakdown and Snapback; 3.6.3 Instability and Current Constriction Model; 3.6.4 Dielectric Breakdown; 3.6.5 Gate Induced Drain Leakage (GIDL); Problems; References; 4 Substrates and ESD; 4.1 Methods of Substrate Analysis; 4.2 Substrate as a Semi-infinite Domain; 4.3 Substrate as a Stratified Medium Using the Transfer Matrix Approach; 4.4 Substrate Transmission Line Model; 4.5 Substrate Lossy Transmission Line Models 4.6 Substrate Absorption, Reflection and Transmission4.7 Substrate Electrical and Thermal Discretization; 4.8 Substrate Effects: Electrical Transfer Resistance; 4.9 Substrate Effects: Thermal Transfer Resistance; 4.10 Substrate Thermal Resistance Models; 4.10.1 Variable Cross-section Model; 4.10.2 Variable Elliptical Cross-section Model; 4.10.3 Back-surface Substrate Lumped Analytical Model; 4.11 Heavily Doped Substrates; 4.12 Low-doped Substrates; Problems; References; 5 Wells, Sub-collectors and ESD; 5.1 Diffused Wells; 5.2 Retrograde and Vertically Modulated Wells; 5.2.1 Retrograde Wells 5.2.2 Retrograde Well Substrate Modulation |
| Altri titoli varianti | Circuits and devices |
| Record Nr. | UNINA-9910876513903321 |
|
Voldman Steven H
|
||
| Hoboken, NJ, : John Wiley, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD in silicon integrated circuits
| ESD in silicon integrated circuits |
| Autore | Amerasekera E. A |
| Edizione | [2nd ed.] |
| Pubbl/distr/stampa | [Place of publication not identified], : J Wiley, 2002 |
| Descrizione fisica | 1 online resource (421 pages) |
| Disciplina | 621.3815/2 |
| Soggetto topico |
Semiconductors - Protection
Integrated circuits - Protection Electrostatics Static eliminators Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
1-280-55472-X
9786610554720 0-470-85212-7 0-470-84605-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910146249503321 |
|
Amerasekera E. A
|
||
| [Place of publication not identified], : J Wiley, 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
System level ESD co-design / / edited by Charvaka Duvvury, Harald Gossner
| System level ESD co-design / / edited by Charvaka Duvvury, Harald Gossner |
| Pubbl/distr/stampa | West Sussex, England : , : Wiley-IEEE Press, , 2015 |
| Descrizione fisica | 1 online resource (533 p.) |
| Disciplina | 537/.2 |
| Collana | Wiley - IEEE |
| Soggetto topico |
Shielding (Electricity)
Electronic apparatus and appliances - Design and construction Integrated circuits - Design and construction Integrated circuits - Protection Electrostatics Static eliminators |
| ISBN |
1-118-86188-4
1-118-86184-1 9781118861899 |
| Classificazione | TEC031000 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Machine generated contents note: Chapter 1 Introduction Charvaka Duvvury Chapter 2 Component Versus System Level ESD Charvaka Duvvury and Harald Gossner Chapter 3 System Level Testing for ESD Susceptibility Michael Hopkins Chapter 4 PCB/IC Co-Design Concepts for SEED Harald Gossner and Charvaka Duvvury Chapter 5 Hard Fails & PCB Protection Devices Robert Ashton Chapter 6 Soft Fail and PCB design measures David Pommerenke and Pratik Maheshwari Chapter 7 ESD in Mobile Devices Matti Uusimaki Chapter 8 ESD for Automotive Applications Wolfgang Reinprecht Chapter 9 Futire Applications of SEED Methodology Harald Gossner and Charvaka Duvvury Chapter 10 Co-Design Tradeoffs: Balancing Robustness, Performance and Cost Jeffery C. Dunnihoo Index . |
| Record Nr. | UNINA-9910166633803321 |
| West Sussex, England : , : Wiley-IEEE Press, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
System level ESD co-design / / edited by Charvaka Duvvury, Harald Gossner
| System level ESD co-design / / edited by Charvaka Duvvury, Harald Gossner |
| Pubbl/distr/stampa | West Sussex, England : , : Wiley-IEEE Press, , 2015 |
| Descrizione fisica | 1 online resource (533 p.) |
| Disciplina | 537/.2 |
| Collana | Wiley - IEEE |
| Soggetto topico |
Shielding (Electricity)
Electronic apparatus and appliances - Design and construction Integrated circuits - Design and construction Integrated circuits - Protection Electrostatics Static eliminators |
| ISBN |
1-118-86188-4
1-118-86184-1 9781118861899 |
| Classificazione | TEC031000 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Machine generated contents note: Chapter 1 Introduction Charvaka Duvvury Chapter 2 Component Versus System Level ESD Charvaka Duvvury and Harald Gossner Chapter 3 System Level Testing for ESD Susceptibility Michael Hopkins Chapter 4 PCB/IC Co-Design Concepts for SEED Harald Gossner and Charvaka Duvvury Chapter 5 Hard Fails & PCB Protection Devices Robert Ashton Chapter 6 Soft Fail and PCB design measures David Pommerenke and Pratik Maheshwari Chapter 7 ESD in Mobile Devices Matti Uusimaki Chapter 8 ESD for Automotive Applications Wolfgang Reinprecht Chapter 9 Futire Applications of SEED Methodology Harald Gossner and Charvaka Duvvury Chapter 10 Co-Design Tradeoffs: Balancing Robustness, Performance and Cost Jeffery C. Dunnihoo Index . |
| Record Nr. | UNINA-9910807341103321 |
| West Sussex, England : , : Wiley-IEEE Press, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
