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Design recipes for FPGAs [[electronic resource] /] / Peter R. Wilson
| Design recipes for FPGAs [[electronic resource] /] / Peter R. Wilson |
| Autore | Wilson Peter R (Peter Robert), <1939-> |
| Pubbl/distr/stampa | Amsterdam ; ; Boston ; ; London, : Newnes, 2007 |
| Descrizione fisica | xxii, 289 p. : ill |
| Disciplina | 621.395 |
| Soggetto topico |
Field programmable gate arrays - Design and construction
Gate array circuits |
| Soggetto genere / forma | Electronic books. |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910464419503321 |
Wilson Peter R (Peter Robert), <1939->
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| Amsterdam ; ; Boston ; ; London, : Newnes, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Design recipes for FPGAs [[electronic resource] /] / Peter R. Wilson
| Design recipes for FPGAs [[electronic resource] /] / Peter R. Wilson |
| Autore | Wilson Peter R (Peter Robert), <1939-> |
| Pubbl/distr/stampa | Amsterdam ; ; Boston ; ; London, : Newnes, 2007 |
| Descrizione fisica | xxii, 289 p. : ill |
| Disciplina | 621.395 |
| Soggetto topico |
Field programmable gate arrays - Design and construction
Gate array circuits |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910789492703321 |
|
Wilson Peter R (Peter Robert), <1939->
|
||
| Amsterdam ; ; Boston ; ; London, : Newnes, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Design recipes for FPGAs / / Peter R. Wilson
| Design recipes for FPGAs / / Peter R. Wilson |
| Autore | Wilson Peter R (Peter Robert), <1939-> |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston ; ; London, : Newnes, 2007 |
| Descrizione fisica | xxii, 289 p. : ill |
| Disciplina | 621.395 |
| Soggetto topico |
Field programmable gate arrays - Design and construction
Gate array circuits |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front cover -- Design Recipes for FPGAs -- Copyright page -- Contents -- Acknowledgements -- Preface -- List of Figures -- Part 1 Overview -- Chapter 1 Introduction -- Why FPGAs? -- Chapter 2 An FPGA Primer -- Introduction -- FPGA evolution -- Programmable logic devices -- Field programmable gate arrays -- FPGA design techniques -- Design constraints using FPGAs -- Summary -- Chapter 3 A VHDL Primer The Essentials -- Introduction -- Entity: model interface -- Architecture: model behavior -- Process: basic functional unit in VHDL -- Basic variable types and operators -- Decisions and loops -- Hierarchical design -- Debugging models -- Basic data types -- Summary -- Chapter 4 Design Automation and Testing for FPGAs -- Simulation -- Libraries -- Synthesis -- Physical design flow -- Place and route -- Timing analysis -- Design pitfalls -- VHDL issues for FPGA design -- Summary -- Part 2 Applications -- Chapter 5 Images and High-Speed Processing -- Introduction -- The camera link interface -- Getting started -- Specifying the interfaces -- Defining the top level design -- System block definitions and interfaces -- The cameralink interface -- The PC interface -- Summary -- Chapter 6 Embedded Processors -- Introduction -- A simple embedded processor -- Soft core processors on an FPGA -- Summary -- Part 3 Designer's Toolbox -- Chapter 7 Serial Communications -- Introduction -- Manchester encoding and decoding -- NRZ coding and decoding -- NRZI coding and decoding -- RS-232 -- Universal Serial Bus -- Summary -- Chapter 8 Digital Filters -- Introduction -- Converting S-domain to Z-domain -- Implementing Z-domain functions in VHDL -- Basic low pass filter model -- FIR filters -- IIR filters -- Summary -- Chapter 9 Secure Systems -- Introduction to block ciphers -- Feistel lattice structures -- The Data Encryption Standard -- Advanced Encryption Standard.
Implementing AES in VHDL -- Summary -- Chapter 10 Memory -- Introduction -- Modeling memory in VHDL -- Read Only Memory -- Random Access Memory -- Synchronous RAM -- FLASH memory -- Summary -- Chapter 11 PS/2 Mouse Interface -- Introduction -- PS/2 mouse basics -- PS/2 mouse commands -- PS/2 mouse data packets -- PS/2 operation modes -- PS/2 mouse with wheel -- Basic PS/2 mouse handler VHDL -- Modified PS/2 mouse handler VHDL -- Summary -- Chapter 12 PS/2 Keyboard Interface -- Introduction -- PS/2 keyboard basics -- PS/2 keyboard commands -- PS/2 keyboard data packets -- PS/2 keyboard operation modes -- Summary -- Chapter 13 A Simple VGA Interface -- Introduction -- Basic pixel timing -- Image handling -- VGA interface VHDL -- Horizontal sync -- Vertical sync -- Horizontal and vertical blanking pulses -- Calculating the correct pixel data -- Summary -- Part 4 Optimizing Designs -- Chapter 14 Synthesis -- Introduction -- VHDL supported in RTL synthesis -- Some interesting cases where synthesis may fail -- What is being synthesized? -- Summary -- Chapter 15 Behavioral Modeling in VHDL -- Introduction -- How to go from RTL to behavioral VHDL -- Summary -- Chapter 16 Design Optimization -- Introduction -- Techniques for logic optimization -- Improving performance -- Critical path analysis -- Summary -- Chapter 17 VHDL-AMS -- Introduction -- Introduction to VHDL-AMS -- Analog pins: TERMINALS -- Mixed-domain modeling -- Analog variables: quantities -- Simultaneous equations in VHDL-AMS -- A VHDL-AMS example -- Differential equations in VHDL-AMS -- Mixed-signal modeling with VHDL-AMS -- A basic switch model -- Basic VHDL-AMS comparator model -- Multiple domain modeling -- Summary -- Chapter 18 Design Optimization Example: DES -- Introduction -- The DES -- Moods -- Initial design -- Initial synthesis -- Optimizing the data path -- Final optimization. Results -- Triple DES -- Comparing the approaches -- Summary -- Part 5 Fundamental Techniques -- Chapter 19 Counters -- Introduction -- Basic binary counter -- Synthesized simple binary counter -- Shift register -- The Johnson counter -- BCD counter -- Summary -- Chapter 20 Latches, Flip-Flops and Registers -- Introduction -- Latches -- Flip-flops -- Registers -- Summary -- Chapter 21 Serial to Parallel & -- Parallel to Serial Conversion -- Serial to Parallel Conversion -- Parallel to Serial Conversion -- Summary -- Chapter 22 ALU Functions -- Introduction -- Logic functions -- 1-bit adder -- Structural n-bit addition -- Configurable n-bit addition -- Twos complement -- Summary -- Chapter 23 Decoders and Multiplexers -- Decoders -- Multiplexers -- Summary -- Chapter 24 Finite State Machines in VHDL -- Introduction -- State transition diagrams -- Implementing FSM in VHDL -- Summary -- Chapter 25 Fixed Point Arithmetic in VHDL -- Introduction -- Basic fixed point types -- Fixed point functions -- Testing the fixed point function -- Summary -- Chapter 26 Binary Multiplication -- Introduction -- Basic binary multiplication -- VHDL unsigned multiplier -- Synthesis of the multiplication function -- 'Simple' multiplication -- Summary -- Chapter 27 Bibliography -- Introduction -- Useful texts for VHDL -- Useful Texts for FPGAs -- General Digital Design Books -- Index -- A -- B -- C -- D -- E -- F -- L -- M -- P -- R -- S -- V -- Z. |
| Record Nr. | UNINA-9910811745003321 |
|
Wilson Peter R (Peter Robert), <1939->
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||
| Amsterdam ; ; Boston ; ; London, : Newnes, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
The design warrior's guide to FPGAs [[electronic resource] ] : devices, tools, and flows / / Clive "Max" Maxfield
| The design warrior's guide to FPGAs [[electronic resource] ] : devices, tools, and flows / / Clive "Max" Maxfield |
| Autore | Maxfield Clive <1957-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; London, : Newnes, c2004 |
| Descrizione fisica | 1 online resource (561 p.) |
| Disciplina | 621.395 |
| Soggetto topico |
Field programmable gate arrays
Gate array circuits |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-74598-3
9786610745982 0-08-047713-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Copyright; Table of Contents; Preface; Acknowledgments; 1. Introduction; 2. Fundamental Concepts; 3. The Origin of FPGAs; 4. Alternative FPGA Architectures; 5. Programming SConfiguringw an FPGA; 6. Who Are All the Players?; 7. FPGA Versus ASIC Design Styles; 8. Schematic-Based Design Flows; 9. HDL-Based Design Flows; 10. Silicon Virtual Prototyping for FPGAs; 11. C/Cbb etc.-Based Design Flows; 12. DSPIBased Design Flows; 13. Embedded Processor-Based Design Flows; 14. Modular and Incremental Design; 15. High-Speed Design and Other PCB Considerations
16. Observing Internal Nodes in an FPGA17. Intellectual Property; 18. Migrating ASIC Designs to FPGAs and Vice Versa; 19. SimulationI SynthesisI VerificationI etcB Design Tools; 20. Choosing the Right Device; 21. Gigabit Transceivers; 22. Reconfigurable Computing; 23. Field-Programmable Node Arrays; 24. Independent Design Tools; 25. Creating an Open-Source-Based Design Flow; 26. Future FPGA Developments; Appendix A: Signal Integrity 101; Appendix B: Deep-Submicron Delay Effects 101; Appendix C: Linear Feedback Shift Registers 101; Glossary; About the Author; Index |
| Record Nr. | UNINA-9910450547703321 |
|
Maxfield Clive <1957->
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||
| Amsterdam ; ; London, : Newnes, c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
The design warrior's guide to FPGAs [[electronic resource] ] : devices, tools, and flows / / Clive "Max" Maxfield
| The design warrior's guide to FPGAs [[electronic resource] ] : devices, tools, and flows / / Clive "Max" Maxfield |
| Autore | Maxfield Clive <1957-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; London, : Newnes, c2004 |
| Descrizione fisica | 1 online resource (561 p.) |
| Disciplina | 621.395 |
| Soggetto topico |
Field programmable gate arrays
Gate array circuits |
| ISBN |
1-280-74598-3
9786610745982 0-08-047713-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Copyright; Table of Contents; Preface; Acknowledgments; 1. Introduction; 2. Fundamental Concepts; 3. The Origin of FPGAs; 4. Alternative FPGA Architectures; 5. Programming SConfiguringw an FPGA; 6. Who Are All the Players?; 7. FPGA Versus ASIC Design Styles; 8. Schematic-Based Design Flows; 9. HDL-Based Design Flows; 10. Silicon Virtual Prototyping for FPGAs; 11. C/Cbb etc.-Based Design Flows; 12. DSPIBased Design Flows; 13. Embedded Processor-Based Design Flows; 14. Modular and Incremental Design; 15. High-Speed Design and Other PCB Considerations
16. Observing Internal Nodes in an FPGA17. Intellectual Property; 18. Migrating ASIC Designs to FPGAs and Vice Versa; 19. SimulationI SynthesisI VerificationI etcB Design Tools; 20. Choosing the Right Device; 21. Gigabit Transceivers; 22. Reconfigurable Computing; 23. Field-Programmable Node Arrays; 24. Independent Design Tools; 25. Creating an Open-Source-Based Design Flow; 26. Future FPGA Developments; Appendix A: Signal Integrity 101; Appendix B: Deep-Submicron Delay Effects 101; Appendix C: Linear Feedback Shift Registers 101; Glossary; About the Author; Index |
| Record Nr. | UNINA-9910783136003321 |
|
Maxfield Clive <1957->
|
||
| Amsterdam ; ; London, : Newnes, c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
The design warrior's guide to FPGAs : devices, tools, and flows / / Clive "Max" Maxfield
| The design warrior's guide to FPGAs : devices, tools, and flows / / Clive "Max" Maxfield |
| Autore | Maxfield Clive <1957-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; London, : Newnes, c2004 |
| Descrizione fisica | 1 online resource (561 p.) |
| Disciplina | 621.395 |
| Soggetto topico |
Field programmable gate arrays
Gate array circuits |
| ISBN |
1-280-74598-3
9786610745982 0-08-047713-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Copyright; Table of Contents; Preface; Acknowledgments; 1. Introduction; 2. Fundamental Concepts; 3. The Origin of FPGAs; 4. Alternative FPGA Architectures; 5. Programming SConfiguringw an FPGA; 6. Who Are All the Players?; 7. FPGA Versus ASIC Design Styles; 8. Schematic-Based Design Flows; 9. HDL-Based Design Flows; 10. Silicon Virtual Prototyping for FPGAs; 11. C/Cbb etc.-Based Design Flows; 12. DSPIBased Design Flows; 13. Embedded Processor-Based Design Flows; 14. Modular and Incremental Design; 15. High-Speed Design and Other PCB Considerations
16. Observing Internal Nodes in an FPGA17. Intellectual Property; 18. Migrating ASIC Designs to FPGAs and Vice Versa; 19. SimulationI SynthesisI VerificationI etcB Design Tools; 20. Choosing the Right Device; 21. Gigabit Transceivers; 22. Reconfigurable Computing; 23. Field-Programmable Node Arrays; 24. Independent Design Tools; 25. Creating an Open-Source-Based Design Flow; 26. Future FPGA Developments; Appendix A: Signal Integrity 101; Appendix B: Deep-Submicron Delay Effects 101; Appendix C: Linear Feedback Shift Registers 101; Glossary; About the Author; Index |
| Record Nr. | UNINA-9910817698503321 |
|
Maxfield Clive <1957->
|
||
| Amsterdam ; ; London, : Newnes, c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Extended abstracts of International Workshop on Gate Insulator : IWGI 2001 : November 1-2, 2001, Tokyo, Japan / / sponsored by JSAP--The Japan Society of Applied Physics ... [et al.]
| Extended abstracts of International Workshop on Gate Insulator : IWGI 2001 : November 1-2, 2001, Tokyo, Japan / / sponsored by JSAP--The Japan Society of Applied Physics ... [et al.] |
| Pubbl/distr/stampa | IEEE |
| Disciplina | 621.3815/2 |
| Soggetto topico |
Electric insulators and insulation
Gate array circuits Dielectrics |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | Extended Abstracts of International Workshop on Gate Insulator. IWGI 2001 |
| Record Nr. | UNISA-996206542003316 |
| IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Extended abstracts of International Workshop on Gate Insulator : IWGI 2001 : November 1-2, 2001, Tokyo, Japan / / sponsored by JSAP--The Japan Society of Applied Physics ... [et al.]
| Extended abstracts of International Workshop on Gate Insulator : IWGI 2001 : November 1-2, 2001, Tokyo, Japan / / sponsored by JSAP--The Japan Society of Applied Physics ... [et al.] |
| Pubbl/distr/stampa | IEEE |
| Disciplina | 621.3815/2 |
| Soggetto topico |
Electric insulators and insulation
Gate array circuits Dielectrics |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | Extended Abstracts of International Workshop on Gate Insulator. IWGI 2001 |
| Record Nr. | UNINA-9910872931403321 |
| IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Extended abstracts of International Workshop on Gate Insulator 2003 IWGI 2003 : November 6-7, 2003, Tokyo, Japan
| Extended abstracts of International Workshop on Gate Insulator 2003 IWGI 2003 : November 6-7, 2003, Tokyo, Japan |
| Pubbl/distr/stampa | Piscataway N J, : Business Center for Academic Societies Japan, 2003 |
| Disciplina | 621.3815/2 |
| Soggetto topico |
Electric insulators and insulation
Gate array circuits Dielectrics Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996206245403316 |
| Piscataway N J, : Business Center for Academic Societies Japan, 2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Extended abstracts of International Workshop on Gate Insulator 2003 IWGI 2003 : November 6-7, 2003, Tokyo, Japan
| Extended abstracts of International Workshop on Gate Insulator 2003 IWGI 2003 : November 6-7, 2003, Tokyo, Japan |
| Pubbl/distr/stampa | Piscataway N J, : Business Center for Academic Societies Japan, 2003 |
| Disciplina | 621.3815/2 |
| Soggetto topico |
Electric insulators and insulation
Gate array circuits Dielectrics Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910872558803321 |
| Piscataway N J, : Business Center for Academic Societies Japan, 2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
