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Advanced FPGA design : architecture, implementation, and optimization / / Steve Kilts
| Advanced FPGA design : architecture, implementation, and optimization / / Steve Kilts |
| Autore | Kilts Steve <1978-> |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : Wiley : , c2007 |
| Descrizione fisica | 1 online resource (354 p.) |
| Disciplina | 621.395 |
| Soggetto topico | Field programmable gate arrays - Design and construction |
| ISBN |
1-280-91682-6
9786610916825 0-470-12789-9 0-470-12788-0 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Preface -- Acknowledgments -- Chapter 1. Architecting Speed -- High Throughput -- Low Latency -- Timing -- Add Register Layers -- Parallel Structures -- Flatten Logic Structures -- Register Balancing -- Reorder Paths -- Summary of Key Points -- Chapter 2. Architecting Area -- Rolling-up the Pipeline -- Control Based Logic Reuse -- Resource Sharing -- Impact of Reset on Area -- Resources without Reset -- Resources without Set -- Resources without Asynchronous Reset -- Resetting RAM -- Utilizing Set/Reset Flip-Flop Pins -- Summary of Key Points -- Chapter 3. Architecting Power -- Clock Gating -- Clock Skew -- Managing Skew -- Gated Domains -- Input Control -- Reducing the Voltage Supply -- Dual-Edge Triggered Flip-Flops -- Modifying Terminations -- Summary of Key Points -- Chapter 4. Example Design: The Advanced Encryption Standard -- AES Architectures -- Compact Architecture -- Partially Pipelined Architecture -- Fully Pipelined Architecture -- Performance versus Area -- Other Optimizations -- Chapter 5. High Level Design -- Abstract Design Techniques -- Graphical State Machines -- DSP Design -- Software/Hardware Co-Design -- Summary of Key Points -- Chapter 6. Clock Domains -- Crossing Clock Domains -- Metastability -- Solution 1: Phase Control -- Solution 2: Double-flopping -- Solution 3: FIFO Structure -- Partitioning Synchronizer Blocks -- Gated Clocks in ASIC Prototypes -- Clocks Module -- Gating Removal -- Summary of Key Points -- Chapter 7. Example Design: I2S versus SPDIF -- I2S -- Protocol -- Hardware Architecture -- Analysis -- SPDIF -- Protocol -- Hardware Architecture -- Analysis -- Chapter 8. Implementing Math Functions -- Hardware Division -- Multiply and Shift -- Iterative Division -- The Goldschmidt Method -- Taylor and Maclaurin Series Expansion -- The CORDIC Algorithm -- Summary of Key Points -- Chapter 9. Example Design: Floating Point Unit -- Floating Point Formats -- Pipelined Architecture.
Verilog Implementation -- Resources and Performance -- Chapter 10. Reset Circuits -- Asynchronous versus Synchronous -- Problems with Fully Asynchronous Resets -- Fully Synchronized Resets -- Asynchronous Assertion, Synchronous Deassertion -- Mixing Reset Types -- Non-Resetable Flip-Flops -- Internally Generated Resets -- Multiple Clock Domains -- Summary of Key Points -- Chapter 11. Advanced Simulation -- Testbench Architecture -- Testbench Components -- Testbench Flow -- Main Thread -- Clocks and Resets -- Testcases -- System Stimulus -- Matlab -- Bus-functional Models -- Code Coverage -- Gate Level Simulations -- Toggle Coverage -- Run-Time Traps -- Timescale -- Glitch Rejection -- Combinatorial Delay Modeling -- Summary of Key Points -- Chapter 12. Coding for Synthesis -- Decision Trees -- Priority versus Parallel -- Full Conditions -- Multiple Control Branches -- Traps -- Blocking versus Nonblocking -- For Loops -- Combinatorial Loops -- Inferred Latches -- Functions -- Design Organization -- Partitioning -- Datapath versus Control -- Clock and Reset Structures -- Multiple Instantiations -- Parameterization -- Definitions -- Parameters -- Parameters in Verilog-2001 -- Summary of Key Points -- Chapter 13. Example Design: The Secure Hash Algorithm -- SHA-1 Architecture -- Implementation Results -- Chapter 14. Synthesis Optimization -- Speed versus Area -- Resource Sharing -- Pipelining, Retiming, and Register Balancing -- The Effect of Reset on Register Balancing -- Resynchronization Registers -- FSM Compilation -- Removal of Unreachable States -- Black Boxes -- Physical Synthesis -- Forward versus Back-Annotation -- Graph Based Physical Synthesis -- Summary of Key Points -- Chapter 15. Floorplanning -- Design Partitioning -- Critical Path Floorplanning -- Floorplanning Dangers -- Optimal Floorplanning -- Data Path -- High Fan-Out -- Device Structure -- Reusability -- Reducing Power Dissipation. Summary of Key Points -- Chapter 16. Place and Route Optimization -- Optimal Constraints -- Relationship between Placement and Routing -- Logic Replication -- Optimization across Hierarchy -- I/O Registers -- Pack Factor -- Mapping Logic into RAM -- Register Ordering -- Placement Seed -- Guided Place and Route -- Summary of Key Points -- Chapter 17. Example Design: Microprocessor -- SRC Architecture -- Synthesis Optimizations -- Speed versus Area -- Pipelining -- Physical Synthesis -- Floorplan Optimizations -- Partitioned Floorplan -- Critical Path Floorplan: Abstraction 1 -- Critical Path Floorplan: Abstraction 2 -- Chapter 18. Static Timing Analysis -- Standard Analysis -- Latches -- Asynchronous Circuits -- Combinatorial Feedback -- Event Driven Clocks -- Summary of Key Points -- Chapter 19. PCB Issues -- Power Supply -- Supply Requirements -- Regulation -- Decoupling Capacitors -- Concept -- Calculating Values -- Capacitor Placement -- Power Planes -- Modeling Signal Reflections -- Spice Simulations -- Configuration -- Debug -- Code Modifications -- FPGA Editor -- Placement -- Properties -- Routing -- ChipScope -- Identify -- Summary of Key Points -- Appendix A -- Appendix B -- Bibliography -- Index. |
| Record Nr. | UNINA-9910143694203321 |
Kilts Steve <1978->
|
||
| Hoboken, New Jersey : , : Wiley : , c2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Advanced FPGA design : architecture, implementation, and optimization / / Steve Kilts
| Advanced FPGA design : architecture, implementation, and optimization / / Steve Kilts |
| Autore | Kilts Steve <1978-> |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : Wiley : , c2007 |
| Descrizione fisica | 1 online resource (354 p.) |
| Disciplina | 621.395 |
| Soggetto topico | Field programmable gate arrays - Design and construction |
| ISBN |
1-280-91682-6
9786610916825 0-470-12789-9 0-470-12788-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Preface -- Acknowledgments -- Chapter 1. Architecting Speed -- High Throughput -- Low Latency -- Timing -- Add Register Layers -- Parallel Structures -- Flatten Logic Structures -- Register Balancing -- Reorder Paths -- Summary of Key Points -- Chapter 2. Architecting Area -- Rolling-up the Pipeline -- Control Based Logic Reuse -- Resource Sharing -- Impact of Reset on Area -- Resources without Reset -- Resources without Set -- Resources without Asynchronous Reset -- Resetting RAM -- Utilizing Set/Reset Flip-Flop Pins -- Summary of Key Points -- Chapter 3. Architecting Power -- Clock Gating -- Clock Skew -- Managing Skew -- Gated Domains -- Input Control -- Reducing the Voltage Supply -- Dual-Edge Triggered Flip-Flops -- Modifying Terminations -- Summary of Key Points -- Chapter 4. Example Design: The Advanced Encryption Standard -- AES Architectures -- Compact Architecture -- Partially Pipelined Architecture -- Fully Pipelined Architecture -- Performance versus Area -- Other Optimizations -- Chapter 5. High Level Design -- Abstract Design Techniques -- Graphical State Machines -- DSP Design -- Software/Hardware Co-Design -- Summary of Key Points -- Chapter 6. Clock Domains -- Crossing Clock Domains -- Metastability -- Solution 1: Phase Control -- Solution 2: Double-flopping -- Solution 3: FIFO Structure -- Partitioning Synchronizer Blocks -- Gated Clocks in ASIC Prototypes -- Clocks Module -- Gating Removal -- Summary of Key Points -- Chapter 7. Example Design: I2S versus SPDIF -- I2S -- Protocol -- Hardware Architecture -- Analysis -- SPDIF -- Protocol -- Hardware Architecture -- Analysis -- Chapter 8. Implementing Math Functions -- Hardware Division -- Multiply and Shift -- Iterative Division -- The Goldschmidt Method -- Taylor and Maclaurin Series Expansion -- The CORDIC Algorithm -- Summary of Key Points -- Chapter 9. Example Design: Floating Point Unit -- Floating Point Formats -- Pipelined Architecture.
Verilog Implementation -- Resources and Performance -- Chapter 10. Reset Circuits -- Asynchronous versus Synchronous -- Problems with Fully Asynchronous Resets -- Fully Synchronized Resets -- Asynchronous Assertion, Synchronous Deassertion -- Mixing Reset Types -- Non-Resetable Flip-Flops -- Internally Generated Resets -- Multiple Clock Domains -- Summary of Key Points -- Chapter 11. Advanced Simulation -- Testbench Architecture -- Testbench Components -- Testbench Flow -- Main Thread -- Clocks and Resets -- Testcases -- System Stimulus -- Matlab -- Bus-functional Models -- Code Coverage -- Gate Level Simulations -- Toggle Coverage -- Run-Time Traps -- Timescale -- Glitch Rejection -- Combinatorial Delay Modeling -- Summary of Key Points -- Chapter 12. Coding for Synthesis -- Decision Trees -- Priority versus Parallel -- Full Conditions -- Multiple Control Branches -- Traps -- Blocking versus Nonblocking -- For Loops -- Combinatorial Loops -- Inferred Latches -- Functions -- Design Organization -- Partitioning -- Datapath versus Control -- Clock and Reset Structures -- Multiple Instantiations -- Parameterization -- Definitions -- Parameters -- Parameters in Verilog-2001 -- Summary of Key Points -- Chapter 13. Example Design: The Secure Hash Algorithm -- SHA-1 Architecture -- Implementation Results -- Chapter 14. Synthesis Optimization -- Speed versus Area -- Resource Sharing -- Pipelining, Retiming, and Register Balancing -- The Effect of Reset on Register Balancing -- Resynchronization Registers -- FSM Compilation -- Removal of Unreachable States -- Black Boxes -- Physical Synthesis -- Forward versus Back-Annotation -- Graph Based Physical Synthesis -- Summary of Key Points -- Chapter 15. Floorplanning -- Design Partitioning -- Critical Path Floorplanning -- Floorplanning Dangers -- Optimal Floorplanning -- Data Path -- High Fan-Out -- Device Structure -- Reusability -- Reducing Power Dissipation. Summary of Key Points -- Chapter 16. Place and Route Optimization -- Optimal Constraints -- Relationship between Placement and Routing -- Logic Replication -- Optimization across Hierarchy -- I/O Registers -- Pack Factor -- Mapping Logic into RAM -- Register Ordering -- Placement Seed -- Guided Place and Route -- Summary of Key Points -- Chapter 17. Example Design: Microprocessor -- SRC Architecture -- Synthesis Optimizations -- Speed versus Area -- Pipelining -- Physical Synthesis -- Floorplan Optimizations -- Partitioned Floorplan -- Critical Path Floorplan: Abstraction 1 -- Critical Path Floorplan: Abstraction 2 -- Chapter 18. Static Timing Analysis -- Standard Analysis -- Latches -- Asynchronous Circuits -- Combinatorial Feedback -- Event Driven Clocks -- Summary of Key Points -- Chapter 19. PCB Issues -- Power Supply -- Supply Requirements -- Regulation -- Decoupling Capacitors -- Concept -- Calculating Values -- Capacitor Placement -- Power Planes -- Modeling Signal Reflections -- Spice Simulations -- Configuration -- Debug -- Code Modifications -- FPGA Editor -- Placement -- Properties -- Routing -- ChipScope -- Identify -- Summary of Key Points -- Appendix A -- Appendix B -- Bibliography -- Index. |
| Record Nr. | UNINA-9910830731003321 |
|
Kilts Steve <1978->
|
||
| Hoboken, New Jersey : , : Wiley : , c2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Advanced FPGA design : architecture, implementation, and optimization / / Steve Kilts
| Advanced FPGA design : architecture, implementation, and optimization / / Steve Kilts |
| Autore | Kilts Steve <1978-> |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, : IEEE, c2007 |
| Descrizione fisica | 1 online resource (354 p.) |
| Disciplina | 621.39/5 |
| Soggetto topico | Field programmable gate arrays - Design and construction |
| ISBN |
1-280-91682-6
9786610916825 0-470-12789-9 0-470-12788-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Preface -- Acknowledgments -- Chapter 1. Architecting Speed -- High Throughput -- Low Latency -- Timing -- Add Register Layers -- Parallel Structures -- Flatten Logic Structures -- Register Balancing -- Reorder Paths -- Summary of Key Points -- Chapter 2. Architecting Area -- Rolling-up the Pipeline -- Control Based Logic Reuse -- Resource Sharing -- Impact of Reset on Area -- Resources without Reset -- Resources without Set -- Resources without Asynchronous Reset -- Resetting RAM -- Utilizing Set/Reset Flip-Flop Pins -- Summary of Key Points -- Chapter 3. Architecting Power -- Clock Gating -- Clock Skew -- Managing Skew -- Gated Domains -- Input Control -- Reducing the Voltage Supply -- Dual-Edge Triggered Flip-Flops -- Modifying Terminations -- Summary of Key Points -- Chapter 4. Example Design: The Advanced Encryption Standard -- AES Architectures -- Compact Architecture -- Partially Pipelined Architecture -- Fully Pipelined Architecture -- Performance versus Area -- Other Optimizations -- Chapter 5. High Level Design -- Abstract Design Techniques -- Graphical State Machines -- DSP Design -- Software/Hardware Co-Design -- Summary of Key Points -- Chapter 6. Clock Domains -- Crossing Clock Domains -- Metastability -- Solution 1: Phase Control -- Solution 2: Double-flopping -- Solution 3: FIFO Structure -- Partitioning Synchronizer Blocks -- Gated Clocks in ASIC Prototypes -- Clocks Module -- Gating Removal -- Summary of Key Points -- Chapter 7. Example Design: I2S versus SPDIF -- I2S -- Protocol -- Hardware Architecture -- Analysis -- SPDIF -- Protocol -- Hardware Architecture -- Analysis -- Chapter 8. Implementing Math Functions -- Hardware Division -- Multiply and Shift -- Iterative Division -- The Goldschmidt Method -- Taylor and Maclaurin Series Expansion -- The CORDIC Algorithm -- Summary of Key Points -- Chapter 9. Example Design: Floating Point Unit -- Floating Point Formats -- Pipelined Architecture.
Verilog Implementation -- Resources and Performance -- Chapter 10. Reset Circuits -- Asynchronous versus Synchronous -- Problems with Fully Asynchronous Resets -- Fully Synchronized Resets -- Asynchronous Assertion, Synchronous Deassertion -- Mixing Reset Types -- Non-Resetable Flip-Flops -- Internally Generated Resets -- Multiple Clock Domains -- Summary of Key Points -- Chapter 11. Advanced Simulation -- Testbench Architecture -- Testbench Components -- Testbench Flow -- Main Thread -- Clocks and Resets -- Testcases -- System Stimulus -- Matlab -- Bus-functional Models -- Code Coverage -- Gate Level Simulations -- Toggle Coverage -- Run-Time Traps -- Timescale -- Glitch Rejection -- Combinatorial Delay Modeling -- Summary of Key Points -- Chapter 12. Coding for Synthesis -- Decision Trees -- Priority versus Parallel -- Full Conditions -- Multiple Control Branches -- Traps -- Blocking versus Nonblocking -- For Loops -- Combinatorial Loops -- Inferred Latches -- Functions -- Design Organization -- Partitioning -- Datapath versus Control -- Clock and Reset Structures -- Multiple Instantiations -- Parameterization -- Definitions -- Parameters -- Parameters in Verilog-2001 -- Summary of Key Points -- Chapter 13. Example Design: The Secure Hash Algorithm -- SHA-1 Architecture -- Implementation Results -- Chapter 14. Synthesis Optimization -- Speed versus Area -- Resource Sharing -- Pipelining, Retiming, and Register Balancing -- The Effect of Reset on Register Balancing -- Resynchronization Registers -- FSM Compilation -- Removal of Unreachable States -- Black Boxes -- Physical Synthesis -- Forward versus Back-Annotation -- Graph Based Physical Synthesis -- Summary of Key Points -- Chapter 15. Floorplanning -- Design Partitioning -- Critical Path Floorplanning -- Floorplanning Dangers -- Optimal Floorplanning -- Data Path -- High Fan-Out -- Device Structure -- Reusability -- Reducing Power Dissipation. Summary of Key Points -- Chapter 16. Place and Route Optimization -- Optimal Constraints -- Relationship between Placement and Routing -- Logic Replication -- Optimization across Hierarchy -- I/O Registers -- Pack Factor -- Mapping Logic into RAM -- Register Ordering -- Placement Seed -- Guided Place and Route -- Summary of Key Points -- Chapter 17. Example Design: Microprocessor -- SRC Architecture -- Synthesis Optimizations -- Speed versus Area -- Pipelining -- Physical Synthesis -- Floorplan Optimizations -- Partitioned Floorplan -- Critical Path Floorplan: Abstraction 1 -- Critical Path Floorplan: Abstraction 2 -- Chapter 18. Static Timing Analysis -- Standard Analysis -- Latches -- Asynchronous Circuits -- Combinatorial Feedback -- Event Driven Clocks -- Summary of Key Points -- Chapter 19. PCB Issues -- Power Supply -- Supply Requirements -- Regulation -- Decoupling Capacitors -- Concept -- Calculating Values -- Capacitor Placement -- Power Planes -- Modeling Signal Reflections -- Spice Simulations -- Configuration -- Debug -- Code Modifications -- FPGA Editor -- Placement -- Properties -- Routing -- ChipScope -- Identify -- Summary of Key Points -- Appendix A -- Appendix B -- Bibliography -- Index. |
| Record Nr. | UNINA-9910877677303321 |
|
Kilts Steve <1978->
|
||
| Hoboken, N.J., : Wiley, : IEEE, c2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Design recipes for FPGAs / / Peter Wilson
| Design recipes for FPGAs / / Peter Wilson |
| Autore | Wilson Peter |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Amsterdam, Netherlands : , : Newnes, , 2016 |
| Descrizione fisica | 1 online resource (352 p.) |
| Disciplina | 621.395 |
| Soggetto topico |
Field programmable gate arrays - Design and construction
Field programmable gate arrays - Energy consumption |
| ISBN |
9786611120238
0-08-097129-6 1-281-12023-5 0-08-054842-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910789494403321 |
|
Wilson Peter
|
||
| Amsterdam, Netherlands : , : Newnes, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Design recipes for FPGAs / / Peter Wilson
| Design recipes for FPGAs / / Peter Wilson |
| Autore | Wilson Peter |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Amsterdam, Netherlands : , : Newnes, , 2016 |
| Descrizione fisica | 1 online resource (352 p.) |
| Disciplina | 621.395 |
| Soggetto topico |
Field programmable gate arrays - Design and construction
Field programmable gate arrays - Energy consumption |
| ISBN |
9786611120238
0-08-097129-6 1-281-12023-5 0-08-054842-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910818803503321 |
|
Wilson Peter
|
||
| Amsterdam, Netherlands : , : Newnes, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Design recipes for FPGAs [[electronic resource] /] / Peter R. Wilson
| Design recipes for FPGAs [[electronic resource] /] / Peter R. Wilson |
| Autore | Wilson Peter R (Peter Robert), <1939-> |
| Pubbl/distr/stampa | Amsterdam ; ; Boston ; ; London, : Newnes, 2007 |
| Descrizione fisica | xxii, 289 p. : ill |
| Disciplina | 621.395 |
| Soggetto topico |
Field programmable gate arrays - Design and construction
Gate array circuits |
| Soggetto genere / forma | Electronic books. |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910464419503321 |
|
Wilson Peter R (Peter Robert), <1939->
|
||
| Amsterdam ; ; Boston ; ; London, : Newnes, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Design recipes for FPGAs [[electronic resource] /] / Peter R. Wilson
| Design recipes for FPGAs [[electronic resource] /] / Peter R. Wilson |
| Autore | Wilson Peter R (Peter Robert), <1939-> |
| Pubbl/distr/stampa | Amsterdam ; ; Boston ; ; London, : Newnes, 2007 |
| Descrizione fisica | xxii, 289 p. : ill |
| Disciplina | 621.395 |
| Soggetto topico |
Field programmable gate arrays - Design and construction
Gate array circuits |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910789492703321 |
|
Wilson Peter R (Peter Robert), <1939->
|
||
| Amsterdam ; ; Boston ; ; London, : Newnes, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Design recipes for FPGAs / / Peter R. Wilson
| Design recipes for FPGAs / / Peter R. Wilson |
| Autore | Wilson Peter R (Peter Robert), <1939-> |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston ; ; London, : Newnes, 2007 |
| Descrizione fisica | xxii, 289 p. : ill |
| Disciplina | 621.395 |
| Soggetto topico |
Field programmable gate arrays - Design and construction
Gate array circuits |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front cover -- Design Recipes for FPGAs -- Copyright page -- Contents -- Acknowledgements -- Preface -- List of Figures -- Part 1 Overview -- Chapter 1 Introduction -- Why FPGAs? -- Chapter 2 An FPGA Primer -- Introduction -- FPGA evolution -- Programmable logic devices -- Field programmable gate arrays -- FPGA design techniques -- Design constraints using FPGAs -- Summary -- Chapter 3 A VHDL Primer The Essentials -- Introduction -- Entity: model interface -- Architecture: model behavior -- Process: basic functional unit in VHDL -- Basic variable types and operators -- Decisions and loops -- Hierarchical design -- Debugging models -- Basic data types -- Summary -- Chapter 4 Design Automation and Testing for FPGAs -- Simulation -- Libraries -- Synthesis -- Physical design flow -- Place and route -- Timing analysis -- Design pitfalls -- VHDL issues for FPGA design -- Summary -- Part 2 Applications -- Chapter 5 Images and High-Speed Processing -- Introduction -- The camera link interface -- Getting started -- Specifying the interfaces -- Defining the top level design -- System block definitions and interfaces -- The cameralink interface -- The PC interface -- Summary -- Chapter 6 Embedded Processors -- Introduction -- A simple embedded processor -- Soft core processors on an FPGA -- Summary -- Part 3 Designer's Toolbox -- Chapter 7 Serial Communications -- Introduction -- Manchester encoding and decoding -- NRZ coding and decoding -- NRZI coding and decoding -- RS-232 -- Universal Serial Bus -- Summary -- Chapter 8 Digital Filters -- Introduction -- Converting S-domain to Z-domain -- Implementing Z-domain functions in VHDL -- Basic low pass filter model -- FIR filters -- IIR filters -- Summary -- Chapter 9 Secure Systems -- Introduction to block ciphers -- Feistel lattice structures -- The Data Encryption Standard -- Advanced Encryption Standard.
Implementing AES in VHDL -- Summary -- Chapter 10 Memory -- Introduction -- Modeling memory in VHDL -- Read Only Memory -- Random Access Memory -- Synchronous RAM -- FLASH memory -- Summary -- Chapter 11 PS/2 Mouse Interface -- Introduction -- PS/2 mouse basics -- PS/2 mouse commands -- PS/2 mouse data packets -- PS/2 operation modes -- PS/2 mouse with wheel -- Basic PS/2 mouse handler VHDL -- Modified PS/2 mouse handler VHDL -- Summary -- Chapter 12 PS/2 Keyboard Interface -- Introduction -- PS/2 keyboard basics -- PS/2 keyboard commands -- PS/2 keyboard data packets -- PS/2 keyboard operation modes -- Summary -- Chapter 13 A Simple VGA Interface -- Introduction -- Basic pixel timing -- Image handling -- VGA interface VHDL -- Horizontal sync -- Vertical sync -- Horizontal and vertical blanking pulses -- Calculating the correct pixel data -- Summary -- Part 4 Optimizing Designs -- Chapter 14 Synthesis -- Introduction -- VHDL supported in RTL synthesis -- Some interesting cases where synthesis may fail -- What is being synthesized? -- Summary -- Chapter 15 Behavioral Modeling in VHDL -- Introduction -- How to go from RTL to behavioral VHDL -- Summary -- Chapter 16 Design Optimization -- Introduction -- Techniques for logic optimization -- Improving performance -- Critical path analysis -- Summary -- Chapter 17 VHDL-AMS -- Introduction -- Introduction to VHDL-AMS -- Analog pins: TERMINALS -- Mixed-domain modeling -- Analog variables: quantities -- Simultaneous equations in VHDL-AMS -- A VHDL-AMS example -- Differential equations in VHDL-AMS -- Mixed-signal modeling with VHDL-AMS -- A basic switch model -- Basic VHDL-AMS comparator model -- Multiple domain modeling -- Summary -- Chapter 18 Design Optimization Example: DES -- Introduction -- The DES -- Moods -- Initial design -- Initial synthesis -- Optimizing the data path -- Final optimization. Results -- Triple DES -- Comparing the approaches -- Summary -- Part 5 Fundamental Techniques -- Chapter 19 Counters -- Introduction -- Basic binary counter -- Synthesized simple binary counter -- Shift register -- The Johnson counter -- BCD counter -- Summary -- Chapter 20 Latches, Flip-Flops and Registers -- Introduction -- Latches -- Flip-flops -- Registers -- Summary -- Chapter 21 Serial to Parallel & -- Parallel to Serial Conversion -- Serial to Parallel Conversion -- Parallel to Serial Conversion -- Summary -- Chapter 22 ALU Functions -- Introduction -- Logic functions -- 1-bit adder -- Structural n-bit addition -- Configurable n-bit addition -- Twos complement -- Summary -- Chapter 23 Decoders and Multiplexers -- Decoders -- Multiplexers -- Summary -- Chapter 24 Finite State Machines in VHDL -- Introduction -- State transition diagrams -- Implementing FSM in VHDL -- Summary -- Chapter 25 Fixed Point Arithmetic in VHDL -- Introduction -- Basic fixed point types -- Fixed point functions -- Testing the fixed point function -- Summary -- Chapter 26 Binary Multiplication -- Introduction -- Basic binary multiplication -- VHDL unsigned multiplier -- Synthesis of the multiplication function -- 'Simple' multiplication -- Summary -- Chapter 27 Bibliography -- Introduction -- Useful texts for VHDL -- Useful Texts for FPGAs -- General Digital Design Books -- Index -- A -- B -- C -- D -- E -- F -- L -- M -- P -- R -- S -- V -- Z. |
| Record Nr. | UNINA-9910811745003321 |
|
Wilson Peter R (Peter Robert), <1939->
|
||
| Amsterdam ; ; Boston ; ; London, : Newnes, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Field programmable gate arrays (FPGAs) II / / George Dekoulis, editor
| Field programmable gate arrays (FPGAs) II / / George Dekoulis, editor |
| Pubbl/distr/stampa | London : , : IntechOpen, , 2020 |
| Descrizione fisica | 1 online resource (114 pages) |
| Disciplina | 621.395 |
| Soggetto topico |
Field programmable gate arrays
Field programmable gate arrays - Design and construction |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | Field Programmable Gate Arrays |
| Record Nr. | UNINA-9910688455803321 |
| London : , : IntechOpen, , 2020 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Field programmable gate arrays and applications / / S. S. S. P. Rao
| Field programmable gate arrays and applications / / S. S. S. P. Rao |
| Autore | Rao S. S. S. P. |
| Pubbl/distr/stampa | Oxford, England : , : Alpha Science International Ltd, , 2016 |
| Descrizione fisica | 1 online resource (373 pages) : illustrations |
| Disciplina | 621.395 |
| Soggetto topico | Field programmable gate arrays - Design and construction |
| Soggetto genere / forma | Electronic books. |
| ISBN | 1-78332-324-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910467158903321 |
|
Rao S. S. S. P.
|
||
| Oxford, England : , : Alpha Science International Ltd, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
