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Advanced DPA theory and practice : towards the security limits of secure embedded circuits / / Eric Peeters
| Advanced DPA theory and practice : towards the security limits of secure embedded circuits / / Eric Peeters |
| Autore | Peeters Eric |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | New York, NY, : Springer, c2013 |
| Descrizione fisica | 1 online resource (xvi, 139 pages) : illustrations (some color) |
| Disciplina | 005.8 |
| Collana | Gale eBooks |
| Soggetto topico |
Embedded computer systems - Security measures
Data encryption (Computer science) Cryptography |
| ISBN | 1-4614-6783-7 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | General Introduction -- Side-Channel Cryptanalysis: a brief survey -- CMOS devices: sources and models of emanation -- Measurement of the power consumption -- Electromagnetic Leakage -- Statistical Tools -- Higher Order Attacks -- Towards the Evaluation of an Implementation against Side-Channel Attacks -- General Conclusion and Possible Further Directions. |
| Record Nr. | UNINA-9910438051503321 |
Peeters Eric
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| New York, NY, : Springer, c2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded multimedia security systems : algorithms and architectures / / Amit Pande, Joseph Zambreno
| Embedded multimedia security systems : algorithms and architectures / / Amit Pande, Joseph Zambreno |
| Autore | Pande Amit |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | New York, : Springer, 2013 |
| Descrizione fisica | 1 online resource (152 p.) |
| Disciplina |
005.8
621.39 |
| Altri autori (Persone) | ZambrenoJoseph |
| Soggetto topico |
Embedded computer systems - Security measures
Computer security |
| ISBN |
1-283-62227-0
9786613934727 1-4471-4459-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | pt. 1. Multimedia systems -- pt. 2. Examples. |
| Record Nr. | UNINA-9910437568803321 |
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Pande Amit
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| New York, : Springer, 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Getting started with secure embedded systems : developing IoT systems for micro:bit and Raspberry Pi Pico using Rust and Tock / / Alexandru Radovici and Ioana Culic
| Getting started with secure embedded systems : developing IoT systems for micro:bit and Raspberry Pi Pico using Rust and Tock / / Alexandru Radovici and Ioana Culic |
| Autore | Radovici Alexandru |
| Pubbl/distr/stampa | New York, New York : , : Apress L. P., , [2022] |
| Descrizione fisica | 1 online resource (542 pages) |
| Disciplina | 005.8 |
| Collana | Technology in action |
| Soggetto topico |
Embedded computer systems - Security measures
Internet of things Rust (Computer program language) Software engineering Computer networks |
| ISBN | 1-4842-7789-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1: Embedded Systems and Architectures -- Chapter 2: Embedded Systems Software Development -- Chapter 3: The Tock Architecture System -- Chapter 4: Rust for Tock -- Chapter 5: Getting Started with Tock OS -- Chapter 6: The Structure of a Custom Tock System -- Chapter 7: Userspace Applications Development -- Chapter 8: Writing a Synchronus Syscall Capsule -- Chapter 9: Writing an Asynchronus Syscall Capsule -- Chapter 10: The Implementation of a Service Capsule -- Chapter 12: Tock Userspace Driver -- Chapter 12: Tock Systems Manager. |
| Record Nr. | UNINA-9910523001903321 |
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Radovici Alexandru
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| New York, New York : , : Apress L. P., , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Secure smart embedded devices, platforms and applications / / Konstantinos Markantonakis, Keith Mayes, editors ; foreword by Fred Piper
| Secure smart embedded devices, platforms and applications / / Konstantinos Markantonakis, Keith Mayes, editors ; foreword by Fred Piper |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | New York : , : Springer, , 2014 |
| Descrizione fisica | 1 online resource (xli, 568 pages) : illustrations (some color) |
| Disciplina | 005.8 |
| Collana | Gale eBooks |
| Soggetto topico |
Embedded computer systems - Security measures
Computer security |
| ISBN | 1-4614-7915-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | An Introduction to Smart Cards and RFIDs -- Embedded DSP Devices -- Microprocessors & Microcontrollers Security -- An Introduction to the Trusted Platform Module and Mobile Trusted Module -- Hardware and VLSI Designs -- Information Security Best Practices -- Smart Card Security -- Graphics Processing Units -- A Survey of Recent Results in FPGA Security and Intellectual Property Protection -- Mobile Communication Security Controllers -- Security of Embedded Location Systems -- Automotive Embedded Systems -- Analysis of Potential Vulnerabilities in Payment Terminals -- Wireless Sensor Nodes -- Near Field Communication -- The BIOS and Rootkits -- Hardware Security Modules -- Security Evaluation and Common Criteria -- Physical Security Primitives -- SCADA System Cyber Security -- An Overview of PIC Microcontrollers and their Suitability for Cryptographic Algorithms -- An Introduction to Java Card Programming -- A Practical Example of Mobile Phone Application using SATSA (JSR 177) API -- Wireless Sensors(Languages/Programming/Developments/Tools/Examples). |
| Record Nr. | UNINA-9910298567403321 |
| New York : , : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Security and embedded systems [[electronic resource] /] / edited by Dimitrios N. Serpanos and Ran Giladi
| Security and embedded systems [[electronic resource] /] / edited by Dimitrios N. Serpanos and Ran Giladi |
| Pubbl/distr/stampa | Amsterdam ; ; Washington, D.C., : IOS Press, c2006 |
| Descrizione fisica | 1 online resource (216 p.) |
| Disciplina | 005.8 |
| Altri autori (Persone) |
GiladiRan
SerpanosDimitrios Nikolaou |
| Collana | NATO security through science series. D, Information and communication security |
| Soggetto topico |
Embedded computer systems - Security measures
Computer security |
| Soggetto genere / forma | Electronic books. |
| ISBN |
6610505187
1-280-50518-4 9786610505180 1-4237-9732-9 1-60750-155-4 600-00-0549-0 1-60129-135-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Title page; Preface; Contents; Chaotic Routing as a Method of an Information Conversion; Combinatorial Game Models for Security Systems; Architectural Enhancements for Secure Embedded Processing; Computational Improvements to Differential Side Channel Analysis; A Process Algebra Approach to Authentication and Secrecy; Intellectual Property Protection Using Embedded Systems; Challenges in Deeply Networked System Survivability; Multimedia Watermarking; A Platform for Designing Secure Embedded Systems; Cryptographic Insecurity of the Test & Repeat Paradigm
A Privacy Classification Model Based on Linkability ValuationA Run-Time Reconfigurable Architecture for Embedded Program Flow Verification; Model-Based Validation of Enterprise Access Policies; Research Issues in Homeland Security; Assurance in Autonomous Decentralized Embedded System; Vulnerabilities and Countermeasures for Embedded Processors; Agent-Based Modeling and Simulation of Malefactors' Attacks Against Computer Networks; Current Problems in Security of Military Networks; Multi-Agent Framework for Intrusion Detection and Alert Correlation Securing Home and Building Automation Systems Using the zPnP ApproachREWARD: A Routing Method for Ad-Hoc Networks with Adjustable Security Capability; On the Security of the GSM Cellular Network; Telecommunications Fraud & Electronic Crime in Fix and Mobile Embedded Systems; Author Index |
| Record Nr. | UNINA-9910451053203321 |
| Amsterdam ; ; Washington, D.C., : IOS Press, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Security and embedded systems [[electronic resource] /] / edited by Dimitrios N. Serpanos and Ran Giladi
| Security and embedded systems [[electronic resource] /] / edited by Dimitrios N. Serpanos and Ran Giladi |
| Pubbl/distr/stampa | Amsterdam ; ; Washington, D.C., : IOS Press, c2006 |
| Descrizione fisica | 1 online resource (216 p.) |
| Disciplina | 005.8 |
| Altri autori (Persone) |
GiladiRan
SerpanosDimitrios Nikolaou |
| Collana | NATO security through science series. D, Information and communication security |
| Soggetto topico |
Embedded computer systems - Security measures
Computer security |
| ISBN |
6610505187
1-280-50518-4 9786610505180 1-4237-9732-9 1-60750-155-4 600-00-0549-0 1-60129-135-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Title page; Preface; Contents; Chaotic Routing as a Method of an Information Conversion; Combinatorial Game Models for Security Systems; Architectural Enhancements for Secure Embedded Processing; Computational Improvements to Differential Side Channel Analysis; A Process Algebra Approach to Authentication and Secrecy; Intellectual Property Protection Using Embedded Systems; Challenges in Deeply Networked System Survivability; Multimedia Watermarking; A Platform for Designing Secure Embedded Systems; Cryptographic Insecurity of the Test & Repeat Paradigm
A Privacy Classification Model Based on Linkability ValuationA Run-Time Reconfigurable Architecture for Embedded Program Flow Verification; Model-Based Validation of Enterprise Access Policies; Research Issues in Homeland Security; Assurance in Autonomous Decentralized Embedded System; Vulnerabilities and Countermeasures for Embedded Processors; Agent-Based Modeling and Simulation of Malefactors' Attacks Against Computer Networks; Current Problems in Security of Military Networks; Multi-Agent Framework for Intrusion Detection and Alert Correlation Securing Home and Building Automation Systems Using the zPnP ApproachREWARD: A Routing Method for Ad-Hoc Networks with Adjustable Security Capability; On the Security of the GSM Cellular Network; Telecommunications Fraud & Electronic Crime in Fix and Mobile Embedded Systems; Author Index |
| Record Nr. | UNINA-9910784244203321 |
| Amsterdam ; ; Washington, D.C., : IOS Press, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Security and embedded systems / / edited by Dimitrios N. Serpanos and Ran Giladi
| Security and embedded systems / / edited by Dimitrios N. Serpanos and Ran Giladi |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Amsterdam ; ; Washington, D.C., : IOS Press, c2006 |
| Descrizione fisica | 1 online resource (216 p.) |
| Disciplina | 005.8 |
| Altri autori (Persone) |
GiladiRan
SerpanosDimitrios Nikolaou |
| Collana | NATO security through science series. D, Information and communication security |
| Soggetto topico |
Embedded computer systems - Security measures
Computer security |
| ISBN |
6610505187
1-280-50518-4 9786610505180 1-4237-9732-9 1-60750-155-4 600-00-0549-0 1-60129-135-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Title page; Preface; Contents; Chaotic Routing as a Method of an Information Conversion; Combinatorial Game Models for Security Systems; Architectural Enhancements for Secure Embedded Processing; Computational Improvements to Differential Side Channel Analysis; A Process Algebra Approach to Authentication and Secrecy; Intellectual Property Protection Using Embedded Systems; Challenges in Deeply Networked System Survivability; Multimedia Watermarking; A Platform for Designing Secure Embedded Systems; Cryptographic Insecurity of the Test & Repeat Paradigm
A Privacy Classification Model Based on Linkability ValuationA Run-Time Reconfigurable Architecture for Embedded Program Flow Verification; Model-Based Validation of Enterprise Access Policies; Research Issues in Homeland Security; Assurance in Autonomous Decentralized Embedded System; Vulnerabilities and Countermeasures for Embedded Processors; Agent-Based Modeling and Simulation of Malefactors' Attacks Against Computer Networks; Current Problems in Security of Military Networks; Multi-Agent Framework for Intrusion Detection and Alert Correlation Securing Home and Building Automation Systems Using the zPnP ApproachREWARD: A Routing Method for Ad-Hoc Networks with Adjustable Security Capability; On the Security of the GSM Cellular Network; Telecommunications Fraud & Electronic Crime in Fix and Mobile Embedded Systems; Author Index |
| Record Nr. | UNINA-9910819041103321 |
| Amsterdam ; ; Washington, D.C., : IOS Press, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Self aware security for real time task schedules in reconfigurable hardware platforms / / Krishnendu Guha, Sangeet Saha, Amlan Chakrabarti
| Self aware security for real time task schedules in reconfigurable hardware platforms / / Krishnendu Guha, Sangeet Saha, Amlan Chakrabarti |
| Autore | Guha Krishnendu |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2021] |
| Descrizione fisica | 1 online resource (195 pages) |
| Disciplina | 006.22 |
| Soggetto topico |
Embedded computer systems - Security measures
Adaptive computing systems - Security measures |
| ISBN | 3-030-79701-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Acknowledgements -- Contents -- About the Authors -- Part I Introduction -- 1 Introduction -- 1.1 Introduction -- 1.2 Real-Time Systems -- 1.2.1 Hard Versus Soft Real-Time -- 1.2.2 Important Features of Real-Time Systems -- 1.2.3 Real-Time Tasks and Its Classifications -- 1.3 Field Programmable Gate Arrays (FPGAs)-Its Evolution and Conceptual Background -- 1.3.1 Introduction to FPGAs -- 1.3.2 FPGA Technology: Evolution of Its Conceptual Path -- 1.3.3 FPGA Architectures -- 1.3.4 Heterogeneous FPGAs -- 1.3.5 Closer Look into CLBs -- 1.3.6 FPGA Design Flow -- 1.3.7 Processors Within Re-configurable Targets -- 1.3.8 Dynamic and Partial Reconfiguration -- 1.3.9 Real-Time Hardware Tasks -- 1.3.10 Spatio-temporal Management of Hardware Tasks -- 1.3.11 Various Task Placement Strategies for FPGAs -- 1.3.12 Fragmentations Control Based Placement Strategies -- 1.4 Conclusions -- References -- Part II Scheduling -- 2 Real-Time Scheduling: Background and Trends -- 2.1 Introduction -- 2.2 A Background on Scheduling -- 2.2.1 Resource Constraint -- 2.2.2 Metrics for Scheduling Evaluation -- 2.3 Real-Time Scheduling -- 2.3.1 Offline Versus Online Scheduling -- 2.3.2 Real-Time Scheduling for Uniprocessor Systems -- 2.3.3 Processor Utilization -- 2.3.4 Real-Time Scheduling for Multiprocessor Systems -- 2.4 Fault Tolerance for Real-Time Scheduling -- 2.4.1 Fault Types -- 2.4.2 Fault Detection -- 2.4.3 Fault Tolerance Techniques -- 2.4.4 Fault Tolerance Scheduling -- 2.5 Imprecise Computation Based Real-Time Task -- 2.6 Real-Time Scheduling on FPGA -- 2.6.1 Challenges for FPGA-Based Scheduling -- 2.6.2 Preemption of Hardware Tasks -- 2.6.3 Existing FPGA-based Real-Time Scheduling Techniques -- 2.6.4 Real-Time Preemptive Scheduling: Uniprocessors Versus Multiprocessors Versus FPGAs -- 2.7 Conclusions -- References.
3 Scheduling Algorithms for Reconfigurable Systems -- 3.1 Introduction -- 3.2 Challenge for Devising Real-Time Scheduling Algorithm for FPGAs -- 3.3 System Model and Assumptions -- 3.4 Scheduling Strategies -- 3.4.1 Scheduling Algorithm for Full Reconfigurable Systems -- 3.4.2 Scheduling Algorithm for Partially Reconfigurable Systems -- 3.4.3 Handling Dynamic Tasks -- 3.4.4 For Fully Reconfigurable FPGAs -- 3.4.5 For Runtime Partially Reconfigurable Systems -- 3.5 Experiments and Results -- 3.5.1 Results and Analysis -- 3.6 Hardware Prototype for Multiple Tasks Processing on FPGA -- 3.7 Conclusion -- References -- Part III Security -- 4 Introduction to Hardware Security for FPGA Based Systems -- 4.1 Introduction -- 4.2 Overview of Hardware Threats -- 4.2.1 Hardware Trojan Horses (HTHs) -- 4.2.2 Piracy and Overbuilding -- 4.2.3 Reverse Engineering -- 4.2.4 Counterfeiting -- 4.3 Hardware Trust and Hardware Security -- 4.3.1 Hardware Trust -- 4.3.2 Hardware Security -- 4.4 Life Cycle of FPGA Based System -- 4.4.1 Consumers -- 4.4.2 FPGA Based System Developer -- 4.4.3 Contract Manufacturer -- 4.4.4 FPGA Vendor -- 4.4.5 Off-Shore Foundry -- 4.4.6 Off-Shore Facility -- 4.4.7 Third Party Reconfigurable IP/Bitstream Developers -- 4.4.8 Value Added Reseller (VAR) -- 4.5 Overview of Threats Related to FPGA Based Systems -- 4.5.1 Attacks Related to Bitstreams -- 4.5.2 Attacks Related to FPGAs -- 4.6 Overview of Hardware Security Techniques for FPGA Based Systems -- 4.6.1 Test Time Detection Techniques -- 4.6.2 Protection via Authentication -- 4.6.3 Runtime Mitigation Mechanisms -- 4.7 Present Scope -- 4.8 Conclusion -- References -- 5 Bypassing Passive Attacks -- 5.1 Introduction -- 5.2 System Model -- 5.2.1 Fully Re-configurable Mode -- 5.2.2 Partially Re-configurable Mode -- 5.3 Threat Model -- 5.3.1 Vulnerability Present in Bitstreams. 5.3.2 Vulnerability in FPGA Device -- 5.4 Self Aware Security to Bypass Passive Threats -- 5.4.1 Existing Strategies and Limitations -- 5.4.2 Security Mechanism -- 5.4.3 Working of Self Aware Agent (SAA) -- 5.4.4 Algorithm and Explanation of Proposed Mechanism -- 5.4.5 Demonstration -- 5.5 Experimentation and Results -- 5.5.1 Experimentation -- 5.5.2 Result Analysis -- 5.6 Conclusion -- References -- 6 Counteracting Active Attacks -- 6.1 Introduction -- 6.2 System Model -- 6.2.1 Single FPGA Based System -- 6.2.2 Multi FPGA Based System -- 6.3 Threat Scenario -- 6.3.1 Vulnerability in RIPs/Bitstreams -- 6.3.2 Vulnerability in FPGAs -- 6.4 Redundancy Based Mechanism and Application to Current Context -- 6.4.1 Application for Single FPGA Based Platform -- 6.4.2 Application for Multi FPGA Based Platform -- 6.5 Self Aware Mechanism -- 6.5.1 Offline Phase -- 6.5.2 Online Phase -- 6.5.3 Handling Non-periodic Tasks -- 6.5.4 Fault Handling -- 6.5.5 Demonstration -- 6.6 Experimentation and Results -- 6.6.1 Experimentation -- 6.6.2 Result Analysis -- 6.7 Conclusion -- References -- 7 Handling Power Draining Attacks -- 7.1 Introduction -- 7.2 System Model -- 7.2.1 Working of System Components -- 7.2.2 Nature of Tasks -- 7.3 Threat Model -- 7.3.1 Illustrative Example -- 7.4 Limitations of Existing Techniques -- 7.5 Self Aware Strategy to Handle Power Draining Attacks -- 7.5.1 Periodic Task Handling -- 7.5.2 Determination of Reference Power Dissipation Values of Schedules -- 7.5.3 Mechanism for Detection of Affected Resources -- 7.5.4 Action on Detection of Vulnerability -- 7.5.5 Handling of Non-periodic Tasks -- 7.6 Experimentation and Result Analysis -- 7.6.1 Experimentation -- 7.6.2 Result Analysis for Periodic Tasks -- 7.6.3 Result Analysis for Non-periodic Tasks -- 7.7 Conclusion -- References. Correction to: Scheduling Algorithms for Reconfigurable Systems -- Correction to: Chapter 3 in: K. Guha et al., Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms, https://doi.org/10.1007/978-3-030-79701-03. |
| Record Nr. | UNINA-9910495237903321 |
|
Guha Krishnendu
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||
| Cham, Switzerland : , : Springer, , [2021] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Self aware security for real time task schedules in reconfigurable hardware platforms / / Krishnendu Guha, Sangeet Saha, Amlan Chakrabarti
| Self aware security for real time task schedules in reconfigurable hardware platforms / / Krishnendu Guha, Sangeet Saha, Amlan Chakrabarti |
| Autore | Guha Krishnendu |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2021] |
| Descrizione fisica | 1 online resource (195 pages) |
| Disciplina | 006.22 |
| Soggetto topico |
Embedded computer systems - Security measures
Adaptive computing systems - Security measures |
| ISBN | 3-030-79701-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Acknowledgements -- Contents -- About the Authors -- Part I Introduction -- 1 Introduction -- 1.1 Introduction -- 1.2 Real-Time Systems -- 1.2.1 Hard Versus Soft Real-Time -- 1.2.2 Important Features of Real-Time Systems -- 1.2.3 Real-Time Tasks and Its Classifications -- 1.3 Field Programmable Gate Arrays (FPGAs)-Its Evolution and Conceptual Background -- 1.3.1 Introduction to FPGAs -- 1.3.2 FPGA Technology: Evolution of Its Conceptual Path -- 1.3.3 FPGA Architectures -- 1.3.4 Heterogeneous FPGAs -- 1.3.5 Closer Look into CLBs -- 1.3.6 FPGA Design Flow -- 1.3.7 Processors Within Re-configurable Targets -- 1.3.8 Dynamic and Partial Reconfiguration -- 1.3.9 Real-Time Hardware Tasks -- 1.3.10 Spatio-temporal Management of Hardware Tasks -- 1.3.11 Various Task Placement Strategies for FPGAs -- 1.3.12 Fragmentations Control Based Placement Strategies -- 1.4 Conclusions -- References -- Part II Scheduling -- 2 Real-Time Scheduling: Background and Trends -- 2.1 Introduction -- 2.2 A Background on Scheduling -- 2.2.1 Resource Constraint -- 2.2.2 Metrics for Scheduling Evaluation -- 2.3 Real-Time Scheduling -- 2.3.1 Offline Versus Online Scheduling -- 2.3.2 Real-Time Scheduling for Uniprocessor Systems -- 2.3.3 Processor Utilization -- 2.3.4 Real-Time Scheduling for Multiprocessor Systems -- 2.4 Fault Tolerance for Real-Time Scheduling -- 2.4.1 Fault Types -- 2.4.2 Fault Detection -- 2.4.3 Fault Tolerance Techniques -- 2.4.4 Fault Tolerance Scheduling -- 2.5 Imprecise Computation Based Real-Time Task -- 2.6 Real-Time Scheduling on FPGA -- 2.6.1 Challenges for FPGA-Based Scheduling -- 2.6.2 Preemption of Hardware Tasks -- 2.6.3 Existing FPGA-based Real-Time Scheduling Techniques -- 2.6.4 Real-Time Preemptive Scheduling: Uniprocessors Versus Multiprocessors Versus FPGAs -- 2.7 Conclusions -- References.
3 Scheduling Algorithms for Reconfigurable Systems -- 3.1 Introduction -- 3.2 Challenge for Devising Real-Time Scheduling Algorithm for FPGAs -- 3.3 System Model and Assumptions -- 3.4 Scheduling Strategies -- 3.4.1 Scheduling Algorithm for Full Reconfigurable Systems -- 3.4.2 Scheduling Algorithm for Partially Reconfigurable Systems -- 3.4.3 Handling Dynamic Tasks -- 3.4.4 For Fully Reconfigurable FPGAs -- 3.4.5 For Runtime Partially Reconfigurable Systems -- 3.5 Experiments and Results -- 3.5.1 Results and Analysis -- 3.6 Hardware Prototype for Multiple Tasks Processing on FPGA -- 3.7 Conclusion -- References -- Part III Security -- 4 Introduction to Hardware Security for FPGA Based Systems -- 4.1 Introduction -- 4.2 Overview of Hardware Threats -- 4.2.1 Hardware Trojan Horses (HTHs) -- 4.2.2 Piracy and Overbuilding -- 4.2.3 Reverse Engineering -- 4.2.4 Counterfeiting -- 4.3 Hardware Trust and Hardware Security -- 4.3.1 Hardware Trust -- 4.3.2 Hardware Security -- 4.4 Life Cycle of FPGA Based System -- 4.4.1 Consumers -- 4.4.2 FPGA Based System Developer -- 4.4.3 Contract Manufacturer -- 4.4.4 FPGA Vendor -- 4.4.5 Off-Shore Foundry -- 4.4.6 Off-Shore Facility -- 4.4.7 Third Party Reconfigurable IP/Bitstream Developers -- 4.4.8 Value Added Reseller (VAR) -- 4.5 Overview of Threats Related to FPGA Based Systems -- 4.5.1 Attacks Related to Bitstreams -- 4.5.2 Attacks Related to FPGAs -- 4.6 Overview of Hardware Security Techniques for FPGA Based Systems -- 4.6.1 Test Time Detection Techniques -- 4.6.2 Protection via Authentication -- 4.6.3 Runtime Mitigation Mechanisms -- 4.7 Present Scope -- 4.8 Conclusion -- References -- 5 Bypassing Passive Attacks -- 5.1 Introduction -- 5.2 System Model -- 5.2.1 Fully Re-configurable Mode -- 5.2.2 Partially Re-configurable Mode -- 5.3 Threat Model -- 5.3.1 Vulnerability Present in Bitstreams. 5.3.2 Vulnerability in FPGA Device -- 5.4 Self Aware Security to Bypass Passive Threats -- 5.4.1 Existing Strategies and Limitations -- 5.4.2 Security Mechanism -- 5.4.3 Working of Self Aware Agent (SAA) -- 5.4.4 Algorithm and Explanation of Proposed Mechanism -- 5.4.5 Demonstration -- 5.5 Experimentation and Results -- 5.5.1 Experimentation -- 5.5.2 Result Analysis -- 5.6 Conclusion -- References -- 6 Counteracting Active Attacks -- 6.1 Introduction -- 6.2 System Model -- 6.2.1 Single FPGA Based System -- 6.2.2 Multi FPGA Based System -- 6.3 Threat Scenario -- 6.3.1 Vulnerability in RIPs/Bitstreams -- 6.3.2 Vulnerability in FPGAs -- 6.4 Redundancy Based Mechanism and Application to Current Context -- 6.4.1 Application for Single FPGA Based Platform -- 6.4.2 Application for Multi FPGA Based Platform -- 6.5 Self Aware Mechanism -- 6.5.1 Offline Phase -- 6.5.2 Online Phase -- 6.5.3 Handling Non-periodic Tasks -- 6.5.4 Fault Handling -- 6.5.5 Demonstration -- 6.6 Experimentation and Results -- 6.6.1 Experimentation -- 6.6.2 Result Analysis -- 6.7 Conclusion -- References -- 7 Handling Power Draining Attacks -- 7.1 Introduction -- 7.2 System Model -- 7.2.1 Working of System Components -- 7.2.2 Nature of Tasks -- 7.3 Threat Model -- 7.3.1 Illustrative Example -- 7.4 Limitations of Existing Techniques -- 7.5 Self Aware Strategy to Handle Power Draining Attacks -- 7.5.1 Periodic Task Handling -- 7.5.2 Determination of Reference Power Dissipation Values of Schedules -- 7.5.3 Mechanism for Detection of Affected Resources -- 7.5.4 Action on Detection of Vulnerability -- 7.5.5 Handling of Non-periodic Tasks -- 7.6 Experimentation and Result Analysis -- 7.6.1 Experimentation -- 7.6.2 Result Analysis for Periodic Tasks -- 7.6.3 Result Analysis for Non-periodic Tasks -- 7.7 Conclusion -- References. Correction to: Scheduling Algorithms for Reconfigurable Systems -- Correction to: Chapter 3 in: K. Guha et al., Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms, https://doi.org/10.1007/978-3-030-79701-03. |
| Record Nr. | UNISA-996464419403316 |
|
Guha Krishnendu
|
||
| Cham, Switzerland : , : Springer, , [2021] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Software test attacks to break mobile and embedded devices / / Jon Duncan Hagar
| Software test attacks to break mobile and embedded devices / / Jon Duncan Hagar |
| Autore | Hagar Jon Duncan |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Chapman & Hall/CRC [Imprint], Oct. 2017 |
| Descrizione fisica | 1 online resource (xxxi, 316 pages) : illustrations |
| Disciplina |
005.14
005.8 |
| Collana | Chapman & Hall/CRC Innovations in Software Engineering |
| Soggetto topico |
Penetration testing (Computer security)
Mobile computing - Security measures Embedded computer systems - Security measures |
| ISBN |
1-4987-6014-7
0-429-07191-4 1-138-46844-4 1-4665-7530-1 |
| Classificazione | COM051230COM053000MAT000000 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Contents; Foreword by Dorothy Graham; Foreword by Lisa Crispin; Preface; Acknowledgments; Copyright and Trademarks Declaration Page; Introduction; Author; Chapter 1: Setting the Mobile and Embedded Framework; Chapter 2: Developer Attacks: Taking the Code Head On; Chapter 3: Control System Attacks; Chapter 4: Hardware Software Attacks; Chapter 5: Mobile and Embedded Software Attacks; Chapter 6: Time Attacks: "It's about Time"; Chapter 7: Human User Interface Attacks: "The Limited (and Unlimited) User Interface"; Chapter 8: Smart and/or Mobile Phone Attacks
Chapter 9: Mobile/Embedded SecurityChapter 10: Generic Attacks; Chapter 11: Mobile and Embedded System Labs; Chapter 12: Some Parting Advice; Appendix A: Mobile and Embedded Error Taxonomy: A Software Error Taxonomy (for Testers); Appendix B: Mobile and Embedded Coding Rules; Appendix C: Quality First: "Defending the Source Code So That Attacks Are Not So Easy"; Appendix D: Basic Timing Concepts; Appendix E: Detailed Mapping of Attacks; Appendix F: UI/GUI and Game Evaluation Checklist; Appendix G: Risk Analysis, FMEA, and Brainstorming; References; Glossary; Back Cover |
| Record Nr. | UNINA-9910787572803321 |
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Hagar Jon Duncan
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| Chapman & Hall/CRC [Imprint], Oct. 2017 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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