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Biblioteca

MARC Lista (tabellare)
2014 proceedings of the International Conference on Embedded Software (EMSOFT) : October 12-17, 2014, Jaypee Greens Golf and Spa Resort, New Delhi, India / / sponsoring societies, SIGDA, SIGBED, SIGMICRO, IEEE CEDA ; in cooperation with IEEE Computer Society
2014 proceedings of the International Conference on Embedded Software (EMSOFT) : October 12-17, 2014, Jaypee Greens Golf and Spa Resort, New Delhi, India / / sponsoring societies, SIGDA, SIGBED, SIGMICRO, IEEE CEDA ; in cooperation with IEEE Computer Society
Pubbl/distr/stampa New York : , : ACM, , 2014
Descrizione fisica 1 online resource (301 pages)
Soggetto topico Embedded computer systems - Programming
Computer software - Development
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9910135192603321
New York : , : ACM, , 2014
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
2014 proceedings of the International Conference on Embedded Software (EMSOFT) : October 12-17, 2014, Jaypee Greens Golf and Spa Resort, New Delhi, India / / sponsoring societies, SIGDA, SIGBED, SIGMICRO, IEEE CEDA ; in cooperation with IEEE Computer Society
2014 proceedings of the International Conference on Embedded Software (EMSOFT) : October 12-17, 2014, Jaypee Greens Golf and Spa Resort, New Delhi, India / / sponsoring societies, SIGDA, SIGBED, SIGMICRO, IEEE CEDA ; in cooperation with IEEE Computer Society
Pubbl/distr/stampa New York : , : ACM, , 2014
Descrizione fisica 1 online resource (301 pages)
Soggetto topico Embedded computer systems - Programming
Computer software - Development
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNISA-996280623703316
New York : , : ACM, , 2014
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
The art of software thermal management for embedded systems / / Mark Benson
The art of software thermal management for embedded systems / / Mark Benson
Autore Benson Mark
Edizione [1st ed. 2014.]
Pubbl/distr/stampa New York : , : Springer, , 2014
Descrizione fisica 1 online resource (xvi, 124 pages) : illustrations (some color)
Disciplina 005.1
620
621.381
621.3815
Collana Gale eBooks
Soggetto topico Embedded computer systems - Programming
Embedded computer systems - Cooling
Software engineering
ISBN 1-4939-0298-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction to Software Thermal Management -- Landscape: History, Present Barriers and The Road Forward -- Roots: a Bedrock of Giants -- Techniques: Putting the Silicon to Work -- Frameworks: Choreographing the Parts -- Frontiers: The Future of Software Thermal Management.
Record Nr. UNINA-9910299492603321
Benson Mark  
New York : , : Springer, , 2014
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Blue fox : arm assembly internals and binary analysis of mobile and IOT devices / / Maria Markstedter
Blue fox : arm assembly internals and binary analysis of mobile and IOT devices / / Maria Markstedter
Autore Markstedter Maria
Pubbl/distr/stampa Hoboken, New Jersey : , : John Wiley & Sons, Ltd, , 2023
Descrizione fisica 1 online resource (xi, 219 pages) : illustrations
Disciplina 005.265
Soggetto topico Assembly languages (Electronic computers)
Internet of Things
Embedded computer systems - Programming
ISBN 1-394-18920-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction -- Part I Arm Assembly Internals -- Chapter 1 Introduction to Reverse Engineering -- Introduction to Assembly -- Bits and Bytes -- Character Encoding -- Machine Code and Assembly -- Assembling -- Cross- Assemblers -- High- Level Languages -- Disassembling -- Decompilation -- Chapter 2 ELF File Format Internals -- Program Structure -- High- Level vs. Low- Level Languages -- The Compilation Process -- Cross- Compiling for Other Architectures -- Assembling and Linking -- The ELF File Overview -- The ELF File Header -- The ELF File Header Information Fields -- The Target Platform Fields -- The Entry Point Field -- The Table Location Fields -- ELF Program Headers -- The PHDR Program Header -- The INTERP Program Header -- The LOAD Program Headers -- The DYNAMIC Program Header -- The NOTE Program Header -- The TLS Program Header -- The GNU_EH_FRAME Program Header -- The GNU_STACK Program Header -- The GNU_RELRO Program Header -- ELF Section Headers -- The ELF Meta- Sections -- The String Table Section -- The Symbol Table Section -- The Main ELF Sections -- The .text Section -- The .data Section -- The .bss Section -- The .rodata Section -- The .tdata and .tbss Sections -- Symbols -- Global vs. Local Symbols -- Weak Symbols -- Symbol Versions -- Mapping Symbols -- The Dynamic Section and Dynamic Loading -- Dependency Loading (NEEDED) -- Program Relocations -- Static Relocations -- Dynamic Relocations -- The Global Offset Table (GOT) -- The Procedure Linkage Table (PLT) -- The ELF Program Initialization and Termination Sections -- Initialization and Termination Order -- Thread- Local Storage -- The Local- Exec TLS Access Model -- The Initial- Exec TLS Access Model -- The General- Dynamic TLS Access Model -- The Local- Dynamic TLS Access Model -- Chapter 3 OS Fundamentals -- OS Architecture Overview -- User Mode vs. Kernel Mode -- Processes -- System Calls -- Objects and Handles -- Threads -- Process Memory Management -- Memory Pages -- Memory Protections -- Anonymous and Memory- Mapped Memory -- Memory- Mapped Files and Modules -- Address Space Layout Randomization -- Stack Implementations -- Shared Memory -- Chapter 4 The Arm Architecture -- Architectures and Profiles -- The Armv8- A Architecture -- Exception Levels -- Armv8- A TrustZone Extension -- Exception Level Changes -- Armv8- A Execution States -- The AArch64 Execution State -- The A64 Instruction Set -- AArch64 Registers -- The Program Counter -- The Stack Pointer -- The Zero Register -- The Link Register -- The Frame Pointer -- The Platform Register (x18) -- The Intraprocedural Call Registers -- SIMD and Floating- Point Registers -- System Registers -- PSTATE -- The AArch32 Execution State -- A32 and T32 Instruction Sets -- The A32 Instruction Set -- The T32 Instruction Set -- Switching Between Instruction Sets -- AArch32 Registers -- The Program Counter -- The Stack Pointer -- The Frame Pointer -- The Link Register -- The Intraprocedural Call Register (IP, r12) -- The Current Program Status Register -- The Application Program Status Register -- The Execution State Registers -- The Instruction Set State Register -- The IT Block State Register (ITSTATE) -- Endianness state -- Mode and Exception Mask Bits -- Chapter 5 Data Processing Instructions -- Shift and Rotate Operations -- Logical Shift Left -- Logical Shift Right -- Arithmetic Shift Right -- Rotate Right -- Rotate Right with Extend -- Instruction Forms -- Shift by a Constant Immediate Form -- Shift by Register Form -- Bitfield Manipulation Operations -- Bitfield Move -- Sign- and Zero- Extend Operations -- Bitfield Extract and Insert -- Logical Operations -- Bitwise AND The TST Instruction -- Bitwise Bit Clear -- Bitwise OR Bitwise OR NOT Bitwise Exclusive OR The TEQ instruction Exclusive OR NOT Arithmetic Operations Addition and Subtraction -- Reverse Subtract -- Compare CMP Instruction Operation Behavior -- Multiplication Operations -- Multiplications on A64 -- Multiplications on A32/T32 -- Least Significant Word Multiplications -- Most Significant Word Multiplications -- Halfword Multiplications -- Vector (Dual) Multiplications -- Long (64- Bit) Multiplications -- Division Operations -- Move Operations -- Move Constant Immediate -- Move Immediate and MOVT on A32/T32 -- Move Immediate, MOVZ, and MOVK on A64 -- Move Register -- Move with NOT -- Chapter 6 Memory Access Instructions -- Instructions Overview -- Addressing Modes and Offset Forms -- Offset Addressing -- Constant Immediate Offset -- Register Offsets -- Pre- Indexed Mode -- Pre- Indexed Mode Example -- Post- Indexed Addressing -- Post- Indexed Addressing Example -- Literal (PC- Relative) Addressing -- Loading Constants -- Loading an Address into a Register -- Load and Store Instructions -- Load and Store Word or Doubleword -- Load and Store Halfword or Byte -- Example Using Load and Store -- Load and Store Multiple (A32) -- Example for STM and LDM -- A More Complicated Example Using STM and LDM -- Load and Store Pair (A64) -- Chapter 7 Conditional Execution -- Conditional Execution Overview -- Conditional Codes -- The NZCV Condition Flags -- Signed vs. Unsigned Integer Overflows -- Condition Codes -- Conditional Instructions -- The If- Then (IT) Instruction in Thumb -- Flag- Setting Instructions -- The Instruction "S" Suffix -- The S Suffix on Add and Subtract Instructions -- The S Suffix on Logical Shift Instructions -- The S Suffix on Multiply Instructions -- The S Suffix on Other Instructions -- Test and Comparison Instructions -- Compare (CMP) -- Compare Negative (CMN) -- Test Bits (TST) -- Test Equality (TEQ) -- Conditional Select Instructions -- Conditional Comparison Instructions -- Boolean AND Conditionals Using CCMP -- Boolean OR Conditionals Using CCMP -- Chapter 8 Control Flow -- Branch Instructions -- Conditional Branches and Loops -- Test and Compare Branches -- Table Branches (T32) -- Branch and Exchange -- Subroutine Branches -- Functions and Subroutines -- The Procedure Call Standard -- Volatile vs. Nonvolatile Registers -- Arguments and Return Values -- Passing Larger Values -- Leaf and Nonleaf Functions -- Leaf Functions -- Nonleaf Functions -- Prologue and Epilogue -- Part II Reverse Engineering -- Chapter 9 Arm Environments -- Arm Boards -- Emulation with QEMU -- QEMU User- Mode Emulation -- QEMU Full- System Emulation -- Firmware Emulation -- Chapter 10 Static Analysis -- Static Analysis Tools -- Command- Line Tools 322 Disassemblers and Decompilers -- Binary Ninja Cloud -- Call- By- Reference Example -- Control Flow Analysis -- Main Function -- Subroutine -- Converting to char if Statement -- Quotient Division for Loop -- Analyzing an Algorithm -- Chapter 11 Dynamic Analysis -- Command- Line Debugging -- GDB Commands -- GDB Multiuser -- GDB Extension: GEF -- Installation -- Interface -- Useful GEF Commands -- Examine Memory -- Watch Memory Regions -- Vulnerability Analyzers -- checksec -- Radare2 -- Debugging -- Remote Debugging -- Radare2 -- IDA Pro -- Debugging a Memory Corruption -- Debugging a Process with GDB -- Chapter 12 Reversing arm64 macOS Malware -- Background -- macOS arm64 Binaries macOS Hello World (arm64) -- Hunting for Malicious arm64 Binaries -- Analyzing arm64 Malware -- Anti- Analysis Techniques -- Anti- Debugging Logic (via ptrace) -- Anti- Debugging Logic (via sysctl) -- Anti- VM Logic (via SIP Status and the Detection of VM Artifacts) -- Conclusion -- Index.
Altri titoli varianti Blue Fox
Record Nr. UNINA-9910829852603321
Markstedter Maria  
Hoboken, New Jersey : , : John Wiley & Sons, Ltd, , 2023
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
CODES+ISSS : 2017 International Conference on Hardware/Software Codesign and System Synthesis / / Institute of Electrical and Electronics Engineers
CODES+ISSS : 2017 International Conference on Hardware/Software Codesign and System Synthesis / / Institute of Electrical and Electronics Engineers
Pubbl/distr/stampa Piscataway, New Jersey : , : IEEE, , 2017
Descrizione fisica 1 online resource : illustrations
Disciplina 005.1
Soggetto topico Computer software - Development
Embedded computer systems - Programming
System design
ISBN 1-4503-5185-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNISA-996279680203316
Piscataway, New Jersey : , : IEEE, , 2017
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
CODES+ISSS : 2017 International Conference on Hardware/Software Codesign and System Synthesis / / Institute of Electrical and Electronics Engineers
CODES+ISSS : 2017 International Conference on Hardware/Software Codesign and System Synthesis / / Institute of Electrical and Electronics Engineers
Pubbl/distr/stampa Piscataway, New Jersey : , : IEEE, , 2017
Descrizione fisica 1 online resource : illustrations
Disciplina 005.1
Soggetto topico Computer software - Development
Embedded computer systems - Programming
System design
ISBN 1-4503-5185-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9910228955803321
Piscataway, New Jersey : , : IEEE, , 2017
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Communicating embedded systems [[electronic resource] ] : software and design : formal methods / / edited by Claude Jard, Olivier H. Roux
Communicating embedded systems [[electronic resource] ] : software and design : formal methods / / edited by Claude Jard, Olivier H. Roux
Edizione [1st edition]
Pubbl/distr/stampa London, : ISTE
Descrizione fisica 1 online resource (275 p.)
Disciplina 621.39/2
Altri autori (Persone) JardClaude
RouxOlivier H
Collana ISTE
Soggetto topico Embedded computer systems - Programming
Embedded computer systems - Design and construction
Computer software - Development
Formal methods (Computer science)
ISBN 1-118-55818-9
1-118-60009-6
1-118-60012-6
1-299-18745-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Cover; Communicating Embedded Systems; Title Page; Copyright Page; Table of Contents; Preface; Chapter 1. Models for Real-Time Embedded Systems; 1.1. Introduction; 1.1.1. Model-checking and control problems; 1.1.2. Timed models; 1.2. Notations, languages and timed transition systems; 1.3. Timed models; 1.3.1. Timed Automata; 1.3.2. Time Petri nets; 1.3.2.1. T-time Petri nets; 1.3.2.2. Timed-arc petri nets; 1.3.3. Compared expressiveness of several classes of timed models; 1.3.3.1. Bisimulation and expressiveness of timed models; 1.3.3.2. Compared expressiveness of different classes of TPN
1.3.3.3. Compared expressiveness of TA, TPN, and TAPN1.4. Models with stopwatches; 1.4.1. Formal models for scheduling aspects; 1.4.1.1. Automata and scheduling; 1.4.1.2. Time Petri nets and scheduling; 1.4.2. Stopwatch automata; 1.4.3. Scheduling time Petri nets; 1.4.4. Decidability results for stopwatch models; 1.5. Conclusion; 1.6. Bibliography; Chapter 2. Timed Model-Checking; 2.1. Introduction; 2.2. Timed models; 2.2.1. Timed transition system; 2.2.2. Timed automata; 2.2.3. Other models; 2.3. Timed logics; 2.3.1. Temporal logics CTL and LTL; 2.3.2. Timed extensions; 2.3.2.1. Timed CTL
2.3.2.2. Timed LTL2.4. Timed model-checking; 2.4.1. Model-checking LTL and CTL (untimed case); 2.4.2. Region automaton; 2.4.3. Model-checking TCTL; 2.4.4. Model-checking MTL; 2.4.5. Efficient model-checking; 2.4.6. Model-checking in practice; 2.5. Conclusion; 2.6. Bibliography; Chapter 3. Control of Timed Systems; 3.1. Introduction; 3.1.1. Verification of timed systems; 3.1.2. The controller synthesis problem; 3.1.3. From control to game; 3.1.4. Game objectives; 3.1.5. Varieties of untimed games; 3.2. Timed games; 3.2.1. Timed game automata; 3.2.2. Strategies and course of the game
3.2.2.1. The course of a timed game3.2.2.2. Strategies; 3.3. Computation of winning states and strategies; 3.3.1. Controllable predecessors; 3.3.2. Symbolic operators; 3.3.3. Symbolic computation of winning states; 3.3.4. Synthesis of winning strategies; 3.4. Zeno strategies; 3.5. Implementability; 3.5.1. Hybrid automata; 3.5.2. On the existence of non-implementable continuous controllers; 3.5.3. Recent results and open problems; 3.6. Specification of control objectives; 3.7. Optimal control; 3.7.1. TA with costs; 3.7.2. Optimal cost in timed games; 3.7.3. Computation of the optimal cost
3.7.4. Recent results and open problems3.8. Efficient algorithms for controller synthesis; 3.8.1. On-the-fly algorithms; 3.8.2. Recent results and open problems; 3.9. Partial observation; 3.10. Changing game rules...; 3.11. Bibliography; Chapter 4. Fault Diagnosis of Timed Systems; 4.1. Introduction; 4.2. Notations; 4.2.1. Timed words and timed languages; 4.2.2. Timed automata; 4.2.3. Region graph of a TA; 4.2.4. Product of TA; 4.2.5. Timed automata with faults; 4.3. Fault diagnosis problems; 4.3.1. Diagnoser; 4.3.2. The problems; 4.3.3. Necessary and sufficient condition for diagnosability
4.4. Fault diagnosis for discrete event systems
Record Nr. UNINA-9910138854403321
London, : ISTE
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Communicating embedded systems [[electronic resource] ] : software and design : formal methods / / edited by Claude Jard, Olivier H. Roux
Communicating embedded systems [[electronic resource] ] : software and design : formal methods / / edited by Claude Jard, Olivier H. Roux
Edizione [1st edition]
Pubbl/distr/stampa London, : ISTE
Descrizione fisica 1 online resource (275 p.)
Disciplina 621.39/2
Altri autori (Persone) JardClaude
RouxOlivier H
Collana ISTE
Soggetto topico Embedded computer systems - Programming
Embedded computer systems - Design and construction
Computer software - Development
Formal methods (Computer science)
ISBN 1-118-55818-9
1-118-60009-6
1-118-60012-6
1-299-18745-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Cover; Communicating Embedded Systems; Title Page; Copyright Page; Table of Contents; Preface; Chapter 1. Models for Real-Time Embedded Systems; 1.1. Introduction; 1.1.1. Model-checking and control problems; 1.1.2. Timed models; 1.2. Notations, languages and timed transition systems; 1.3. Timed models; 1.3.1. Timed Automata; 1.3.2. Time Petri nets; 1.3.2.1. T-time Petri nets; 1.3.2.2. Timed-arc petri nets; 1.3.3. Compared expressiveness of several classes of timed models; 1.3.3.1. Bisimulation and expressiveness of timed models; 1.3.3.2. Compared expressiveness of different classes of TPN
1.3.3.3. Compared expressiveness of TA, TPN, and TAPN1.4. Models with stopwatches; 1.4.1. Formal models for scheduling aspects; 1.4.1.1. Automata and scheduling; 1.4.1.2. Time Petri nets and scheduling; 1.4.2. Stopwatch automata; 1.4.3. Scheduling time Petri nets; 1.4.4. Decidability results for stopwatch models; 1.5. Conclusion; 1.6. Bibliography; Chapter 2. Timed Model-Checking; 2.1. Introduction; 2.2. Timed models; 2.2.1. Timed transition system; 2.2.2. Timed automata; 2.2.3. Other models; 2.3. Timed logics; 2.3.1. Temporal logics CTL and LTL; 2.3.2. Timed extensions; 2.3.2.1. Timed CTL
2.3.2.2. Timed LTL2.4. Timed model-checking; 2.4.1. Model-checking LTL and CTL (untimed case); 2.4.2. Region automaton; 2.4.3. Model-checking TCTL; 2.4.4. Model-checking MTL; 2.4.5. Efficient model-checking; 2.4.6. Model-checking in practice; 2.5. Conclusion; 2.6. Bibliography; Chapter 3. Control of Timed Systems; 3.1. Introduction; 3.1.1. Verification of timed systems; 3.1.2. The controller synthesis problem; 3.1.3. From control to game; 3.1.4. Game objectives; 3.1.5. Varieties of untimed games; 3.2. Timed games; 3.2.1. Timed game automata; 3.2.2. Strategies and course of the game
3.2.2.1. The course of a timed game3.2.2.2. Strategies; 3.3. Computation of winning states and strategies; 3.3.1. Controllable predecessors; 3.3.2. Symbolic operators; 3.3.3. Symbolic computation of winning states; 3.3.4. Synthesis of winning strategies; 3.4. Zeno strategies; 3.5. Implementability; 3.5.1. Hybrid automata; 3.5.2. On the existence of non-implementable continuous controllers; 3.5.3. Recent results and open problems; 3.6. Specification of control objectives; 3.7. Optimal control; 3.7.1. TA with costs; 3.7.2. Optimal cost in timed games; 3.7.3. Computation of the optimal cost
3.7.4. Recent results and open problems3.8. Efficient algorithms for controller synthesis; 3.8.1. On-the-fly algorithms; 3.8.2. Recent results and open problems; 3.9. Partial observation; 3.10. Changing game rules...; 3.11. Bibliography; Chapter 4. Fault Diagnosis of Timed Systems; 4.1. Introduction; 4.2. Notations; 4.2.1. Timed words and timed languages; 4.2.2. Timed automata; 4.2.3. Region graph of a TA; 4.2.4. Product of TA; 4.2.5. Timed automata with faults; 4.3. Fault diagnosis problems; 4.3.1. Diagnoser; 4.3.2. The problems; 4.3.3. Necessary and sufficient condition for diagnosability
4.4. Fault diagnosis for discrete event systems
Record Nr. UNINA-9910820091003321
London, : ISTE
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Compilation and synthesis for embedded reconfigurable systems : an aspect-oriented approach / / Joao Manuel Paiva Cardoso, Pedro C. Diniz, Jose Gabriel de Figueiredo Coutinho, Zlatko Marinov Petrov, editors
Compilation and synthesis for embedded reconfigurable systems : an aspect-oriented approach / / Joao Manuel Paiva Cardoso, Pedro C. Diniz, Jose Gabriel de Figueiredo Coutinho, Zlatko Marinov Petrov, editors
Edizione [1st ed. 2013.]
Pubbl/distr/stampa New York : , : Springer, , 2013
Descrizione fisica 1 online resource (xii, 203 pages) : illustrations (some color)
Disciplina 005.1
Collana Gale eBooks
Soggetto topico Embedded computer systems - Programming
Aspect-oriented programming
ISBN 1-4614-4894-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction -- The REFLECT Design-Flow -- The LARA Language -- Aspect-Based Source to Source Transformations -- Hardware/Software Compilation -- LARA Experiments -- Related Work -- Conclusions.
Record Nr. UNINA-9910438059003321
New York : , : Springer, , 2013
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Embedded Linux development with Yocto project : develop fascinating Linux-based projects using the groundbreaking Yocto project tools / / Otavio Salvador, Daiane Angolini ; cover image by Jarek Blaminsky
Embedded Linux development with Yocto project : develop fascinating Linux-based projects using the groundbreaking Yocto project tools / / Otavio Salvador, Daiane Angolini ; cover image by Jarek Blaminsky
Autore Salvador Otavio
Pubbl/distr/stampa Birmingham, England : , : Packt Publishing, , 2014
Descrizione fisica 1 online resource (142 p.)
Disciplina 005.432
Collana Community Experience Distilled
Soggetto topico Embedded computer systems - Programming
Operating systems (Computers)
Soggetto genere / forma Electronic books.
ISBN 1-78328-234-7
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Cover; Copyright; Credits; About the Authors; About the Reviewers; www.PacktPub.com; Table of Contents; Preface; Chapter 1: Meeting the Yocto Project; What is the Yocto Project?; Delineating the Yocto Project; Understanding Poky; Using BitBake; OpenEmbedded-Core; Metadata; The alliance of OpenEmbedded Project and Yocto Project; Summary; Chapter 2: Baking Our Poky-based System; Configuring a host system; Installing Poky on Debian; Installing Poky on Fedora; Downloading the Poky source code; Preparing the build environment; Knowing the local.conf file; Building a target image
Running images in QEMUSummary; Chapter 3: Using Hob to Bake an Image; Building an image using Hob; Customizing an image with Hob; Summary; Chapter 4: Grasping the BitBake Tool; Understanding the BitBake tool; Exploring metadata; Parsing metadata; Dependencies; Preferring and providing recipes; Fetching the source code; Remote file downloads; Git repositories; Other repositories; Optimizing the source code download; Disabling network access; Understanding BitBake's tasks; Extending tasks; Generating a root filesystem image; Summary; Chapter 5: Detailing the Temporary Build Directory
Detailing the build directoryConstructing the build directory; Exploring the temporary build directory; Understanding the work directory; Understanding the sysroot directories; Summary; Chapter 6: Assimilating Packaging Support; Using supported package formats; List of supported package formats; Choosing a package format; Running code during package installation; Understanding shared state cache; Explaining package versioning; Package feeds; Using package feeds; Summary; Chapter 7: Diving into BitBake Metadata; Using metadata; Working with metadata; The basic variable setting
Variable expansionSetting a default value using ?=; Setting a default value using ??=; Immediate variable expansion; Appending and prepending; Conditional metadata set; Conditional appending; File inclusion; Python variable expansion; Defining executable metadata; Defining Python functions in the global namespace; The inheritance system; Summary; Chapter 8: Developing with the Yocto Project; Deciphering the software development kit; Working with the Poky SDK; Using an image-based SDK; Generic SDK - meta-toolchain; Using a SDK; Developing applications on the target; Integrating with Eclipse
SummaryChapter 9: Debugging with the Yocto Project; Differentiating metadata and application debugging; Tracking image, package, and SDK contents; Debugging packaging; Logging information during task execution; Utilizing Development Shell; Using the GNU Project Debugger for debugging; Summary; Chapter 10: Exploring External Layers; Powering flexibility with layers; Detailing the layer's source code; Adding meta layers; Summary; Chapter 11: Creating Custom Layers; Making a new layer; Adding metadata to the layer; Creating an image; Adding a package recipe; Writing a machine definition
Using a custom distribution
Record Nr. UNINA-9910458488103321
Salvador Otavio  
Birmingham, England : , : Packt Publishing, , 2014
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui