ESD testing : from components to systems / / Steven H. Voldman |
Autore | Voldman Steven H. |
Pubbl/distr/stampa | Chichester, West Sussex, England : , : Wiley, , 2017 |
Descrizione fisica | 1 online resource (324 pages) : illustrations |
Disciplina | 621.3815/4 |
Collana | ESD series |
Soggetto topico |
Electronic circuits - Effect of radiation on
Electronic apparatus and appliances - Testing Electric discharges - Detection Electric discharges - Measurement Electrostatics |
Soggetto genere / forma | Electronic books. |
ISBN |
1-118-70715-X
1-118-70712-5 1-118-70714-1 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Human body model -- Machine model -- Charged device model -- Transmission line pulse (TLP) -- Very fast transmission line pulse (VF-TLP) -- IEC 61000-4-2 -- Human metal model (HMM) -- IEC 61000-4-5 -- Cable discharge event (CDE) -- Latchup -- Electrical overstress (EOS) -- Electromagnetic compatibility (EMC) testing. |
Record Nr. | UNINA-9910270916903321 |
Voldman Steven H. | ||
Chichester, West Sussex, England : , : Wiley, , 2017 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
ESD testing : from components to systems / / Steven H. Voldman |
Autore | Voldman Steven H. |
Pubbl/distr/stampa | Chichester, West Sussex, England : , : Wiley, , 2017 |
Descrizione fisica | 1 online resource (324 pages) : illustrations |
Disciplina | 621.3815/4 |
Collana | ESD series |
Soggetto topico |
Electronic circuits - Effect of radiation on
Electronic apparatus and appliances - Testing Electric discharges - Detection Electric discharges - Measurement Electrostatics |
ISBN |
1-118-70715-X
1-118-70712-5 1-118-70714-1 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto | Human body model -- Machine model -- Charged device model -- Transmission line pulse (TLP) -- Very fast transmission line pulse (VF-TLP) -- IEC 61000-4-2 -- Human metal model (HMM) -- IEC 61000-4-5 -- Cable discharge event (CDE) -- Latchup -- Electrical overstress (EOS) -- Electromagnetic compatibility (EMC) testing. |
Record Nr. | UNINA-9910830687703321 |
Voldman Steven H. | ||
Chichester, West Sussex, England : , : Wiley, , 2017 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
Radiation effects and soft errors in integrated circuits and electronic devices [[electronic resource] /] / editors, R.D. Schrimpf, D.M. Fleetwood |
Pubbl/distr/stampa | Singapore ; ; New Jersey, : World Scientific Pub., c2004 |
Descrizione fisica | 1 online resource (349 p.) |
Disciplina | 621.3815 |
Altri autori (Persone) |
SchrimpfRonald Donald
FleetwoodD. M (Dan M.) |
Collana | Selected topics in electronics and systems |
Soggetto topico |
Electronic circuits - Effect of radiation on
Integrated circuits - Effect of radiation on |
Soggetto genere / forma | Electronic books. |
ISBN |
1-281-93459-3
9786611934590 981-279-470-0 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto |
CONTENTS ; Preface ; Single Event Effects in Avionics and on the Ground ; 1. Introduction ; 2. Similarities between SEE in Avionics and on the Ground ; 3. Differences Between SEE in Avionics and on the Ground ; 4. Atmospheric and Ground Level Environments ; 5. SEE Data in devices
6. Summary Soft Errors in Commercial Integrated Circuits ; 1. Introduction ; 2. Scaling trends for memory devices ; 3. Seating trend for peripheral logic devices ; 4. Conclusion ; Single-Event Effects in lll-V Semiconductor Electronics ; 1. Introduction 2. Single-Event Effects in lll-V Electronic Devices 3. Summary and Conclusions ; Investigation of Single-Event Transients in Fast Integrated Circuits with a Pulsed Laser ; 1. Basic Mechanisms of a SET ; 2. SET Laser Testing ; 3. Experimental set-up for SET laser testing ; 4. Results 5. Conclusions System Level Single Event Upset Mitigation Strategies ; 1. Introduction ; 2. Systems Engineering for Energetic Particle Environment Compatibility ; 3. Fault Tolerant Systems Strategies ; Radiation-Tolerant Design for High Performance Mixed-Signal Circuits 1. Introduction 2. Radiation Mechanisms in Mixed-Signal Integrated Circuits ; 3. Process Component and Layout Choices for Hardened-by-Design Circuits ; 4. Total Dose Hardening ; 5. Single-Event Effect Hardening ; 6. Dose-Rate Effect Hardening ; 7. Conclusion A Total-Dose Hardening-By-Design Approach for High-Speed Mixed-Signal CMOS Integrated Circuits |
Record Nr. | UNINA-9910454319803321 |
Singapore ; ; New Jersey, : World Scientific Pub., c2004 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
Radiation effects and soft errors in integrated circuits and electronic devices [[electronic resource] /] / editors, R.D. Schrimpf, D.M. Fleetwood |
Pubbl/distr/stampa | Singapore ; ; New Jersey, : World Scientific Pub., c2004 |
Descrizione fisica | 1 online resource (349 p.) |
Disciplina | 621.3815 |
Altri autori (Persone) |
SchrimpfRonald Donald
FleetwoodD. M (Dan M.) |
Collana | Selected topics in electronics and systems |
Soggetto topico |
Electronic circuits - Effect of radiation on
Integrated circuits - Effect of radiation on |
ISBN |
1-281-93459-3
9786611934590 981-279-470-0 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto |
CONTENTS ; Preface ; Single Event Effects in Avionics and on the Ground ; 1. Introduction ; 2. Similarities between SEE in Avionics and on the Ground ; 3. Differences Between SEE in Avionics and on the Ground ; 4. Atmospheric and Ground Level Environments ; 5. SEE Data in devices
6. Summary Soft Errors in Commercial Integrated Circuits ; 1. Introduction ; 2. Scaling trends for memory devices ; 3. Seating trend for peripheral logic devices ; 4. Conclusion ; Single-Event Effects in lll-V Semiconductor Electronics ; 1. Introduction 2. Single-Event Effects in lll-V Electronic Devices 3. Summary and Conclusions ; Investigation of Single-Event Transients in Fast Integrated Circuits with a Pulsed Laser ; 1. Basic Mechanisms of a SET ; 2. SET Laser Testing ; 3. Experimental set-up for SET laser testing ; 4. Results 5. Conclusions System Level Single Event Upset Mitigation Strategies ; 1. Introduction ; 2. Systems Engineering for Energetic Particle Environment Compatibility ; 3. Fault Tolerant Systems Strategies ; Radiation-Tolerant Design for High Performance Mixed-Signal Circuits 1. Introduction 2. Radiation Mechanisms in Mixed-Signal Integrated Circuits ; 3. Process Component and Layout Choices for Hardened-by-Design Circuits ; 4. Total Dose Hardening ; 5. Single-Event Effect Hardening ; 6. Dose-Rate Effect Hardening ; 7. Conclusion A Total-Dose Hardening-By-Design Approach for High-Speed Mixed-Signal CMOS Integrated Circuits |
Record Nr. | UNINA-9910782122603321 |
Singapore ; ; New Jersey, : World Scientific Pub., c2004 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
Radiation effects and soft errors in integrated circuits and electronic devices / / editors, R.D. Schrimpf, D.M. Fleetwood |
Edizione | [1st ed.] |
Pubbl/distr/stampa | Singapore ; ; New Jersey, : World Scientific Pub., c2004 |
Descrizione fisica | 1 online resource (349 p.) |
Disciplina | 621.3815 |
Altri autori (Persone) |
SchrimpfRonald Donald
FleetwoodD. M (Dan M.) |
Collana | Selected topics in electronics and systems |
Soggetto topico |
Electronic circuits - Effect of radiation on
Integrated circuits - Effect of radiation on |
ISBN |
1-281-93459-3
9786611934590 981-279-470-0 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto |
CONTENTS ; Preface ; Single Event Effects in Avionics and on the Ground ; 1. Introduction ; 2. Similarities between SEE in Avionics and on the Ground ; 3. Differences Between SEE in Avionics and on the Ground ; 4. Atmospheric and Ground Level Environments ; 5. SEE Data in devices
6. Summary Soft Errors in Commercial Integrated Circuits ; 1. Introduction ; 2. Scaling trends for memory devices ; 3. Seating trend for peripheral logic devices ; 4. Conclusion ; Single-Event Effects in lll-V Semiconductor Electronics ; 1. Introduction 2. Single-Event Effects in lll-V Electronic Devices 3. Summary and Conclusions ; Investigation of Single-Event Transients in Fast Integrated Circuits with a Pulsed Laser ; 1. Basic Mechanisms of a SET ; 2. SET Laser Testing ; 3. Experimental set-up for SET laser testing ; 4. Results 5. Conclusions System Level Single Event Upset Mitigation Strategies ; 1. Introduction ; 2. Systems Engineering for Energetic Particle Environment Compatibility ; 3. Fault Tolerant Systems Strategies ; Radiation-Tolerant Design for High Performance Mixed-Signal Circuits 1. Introduction 2. Radiation Mechanisms in Mixed-Signal Integrated Circuits ; 3. Process Component and Layout Choices for Hardened-by-Design Circuits ; 4. Total Dose Hardening ; 5. Single-Event Effect Hardening ; 6. Dose-Rate Effect Hardening ; 7. Conclusion A Total-Dose Hardening-By-Design Approach for High-Speed Mixed-Signal CMOS Integrated Circuits |
Record Nr. | UNINA-9910816750703321 |
Singapore ; ; New Jersey, : World Scientific Pub., c2004 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
Terrestrial radiation effects in ULSI devices and electronic systems / / Eishi H. Ibe |
Autore | Ibe Eishi H. |
Pubbl/distr/stampa | Singapore : , : John Wiley & Sons Inc., , 2015 |
Descrizione fisica | 1 online resource (565 p.) |
Disciplina | 621.3815 |
Soggetto topico |
Electronic circuits - Effect of radiation on
Integrated circuits - Ultra large scale integration - Reliability Integrated circuits - Effect of radiation on |
ISBN |
1-118-47932-7
1-118-47931-9 1-118-47930-0 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto |
About the Author xiii -- Preface xv -- Acknowledgements xvii -- Acronyms xix -- 1 Introduction 1 -- 1.1 Basic Knowledge on Terrestrial Secondary Particles 1 -- 1.2 CMOS Semiconductor Devices and Systems 4 -- 1.3 Two Major Fault Modes: Charge Collection and Bipolar Action 7 -- 1.4 Four Hierarchies in Faulty Conditions in Electronic Systems: Fault - Error - Hazard - Failure 12 -- 1.5 Historical Background of Soft-Error Research 14 -- 1.6 General Scope of This Book 18 -- References 18 -- 2 Terrestrial Radiation Fields 23 -- 2.1 General Sources of Radiation 23 -- 2.2 Backgrounds for Selection of Terrestrial High-Energy Particles 23 -- 2.3 Spectra at the Avionics Altitude 25 -- 2.4 Radioisotopes in the Field 28 -- 2.5 Summary of Chapter 2 31 -- References 31 -- 3 Fundamentals of Radiation Effects 33 -- 3.1 General Description of Radiation Effects 33 -- 3.2 Definition of Cross Section 35 -- 3.3 Radiation Effects by Photons (Gamma-ray and X-ray) 36 -- 3.4 Radiation Effects by Electrons (Beta-ray) 37 -- 3.5 Radiation Effects by Muons 39 -- 3.6 Radiation Effects by Protons 40 -- 3.7 Radiation Effects by Alpha-Particles 43 -- 3.8 Radiation Effects by Low-Energy Neutrons 43 -- 3.9 Radiation Effects by High-Energy Neutrons 45 -- 3.10 Radiation Effects by Heavy Ions 45 -- 3.11 Summary of Chapter 3 46 -- References 46 -- 4 Fundamentals of Electronic Devices and Systems 49 -- 4.1 Fundamentals of Electronic Components 49 -- 4.1.1 DRAM (Dynamic Random Access Memory) 49 -- 4.1.2 CMOS Inverter 49 -- 4.1.3 SRAM (Static Random Access Memory) 51 -- 4.1.4 Floating Gate Memory (Flash Memory) 51 -- 4.1.5 Sequential Logic Devices 53 -- 4.1.6 Combinational Logic Devices 54 -- 4.2 Fundamentals of Electronic Systems 55 -- 4.2.1 FPGA (Field Programmable Gate Array) 55 -- 4.2.2 Processor 56 -- 4.3 Summary of Chapter 4 58 -- References 58 -- 5 Irradiation Test Methods for Single Event Effects 61 -- 5.1 Field Test 61 -- 5.2 Alpha Ray SEE Test 64 -- 5.3 Heavy Ion Particle Irradiation Test 66 -- 5.4 Proton Beam Test 71.
5.5 Muon Test Method 75 -- 5.6 Thermal/Cold Neutron Test Methods 78 -- 5.7 High-Energy Neutron Test 80 -- 5.7.1 Medium-Energy Neutron Source by Using Radioisotopes 80 -- 5.7.2 Monoenergetic Neutron Test 80 -- 5.7.3 Quasi-Monoenergetic Neutron Test 84 -- 5.7.4 Spallation Neutron Test 90 -- 5.7.5 Attenuation of Neutron Flux and Energy 92 -- 5.8 Testing Conditions and Matters That Require Attention 94 -- 5.8.1 Memories 94 -- 5.8.2 Circuits 94 -- 5.9 Summary of Chapter 5 96 -- References 96 -- 6 Integrated Device Level Simulation Techniques 107 -- 6.1 Overall Multi-scale and Multi-physics Soft-Error Analysis System 107 -- 6.2 Relativistic Binary Collision and Nuclear Reaction Models 112 -- 6.2.1 Energy Bin Setting for a Particle Energy Spectrum 112 -- 6.2.2 Relativistic Binary Collision Model 113 -- 6.2.3 ALS (Absolute Laboratory System) and ALLS (Aligned Laboratory System) 115 -- 6.3 Intra-nuclear Cascade (INC) Model for High-Energy Neutrons and Protons 119 -- 6.3.1 Penetration of a Nucleon into a Target Nucleus 119 -- 6.3.2 Calculation of Probability of Binary Collision between Two -- Nucleons in the Target Nucleus 121 -- 6.3.3 Determination of Condition in Nucleon-Nucleon Collision 121 -- 6.4 Evaporation Model for High-Energy Neutrons and Protons 122 -- 6.5 Generalised Evaporation Model (GEM) for Inverse Reaction Cross Sections 125 -- 6.6 Neutron Capture Reaction Model 128 -- 6.7 Automated Device Modelling 129 -- 6.8 Setting of Random Position of Spallation Reaction Point in a Component 131 -- 6.9 Algorithms for Ion Tracking 133 -- 6.10 Fault Mode Models 135 -- 6.11 Calculation of Cross Section 141 -- 6.12 Prediction for Scaling Effects of Soft Error Down to 22 nm Design Rule in SRAMs 142 -- 6.13 Evaluation of Effects of Heavy Elements in Semiconductor Devices by Nuclear Spallation Reaction 144 -- 6.14 Upper Bound Fault Simulation Model 146 -- 6.15 Upper Bound Fault Simulation Results 147 -- 6.15.1 Electrons 147 -- 6.15.2 Muons 148 -- 6.15.3 Direct Ionisation by Proton 149. 6.15.4 Proton Spallation 149 -- 6.15.5 Low-Energy Neutron 151 -- 6.15.6 High-Energy Neutron Spallation 151 -- 6.15.7 Comparison of Secondary Cosmic Rays 151 -- 6.16 Upper Bound Simulation Method for SOC (System On Chip) 151 -- 6.17 Summary of Chapter 6 154 -- References 154 -- 7 Prediction, Detection and Classification Techniques of Faults, Errors and Failures 157 -- 7.1 Overview of Failures in the Field 157 -- 7.2 Prediction and Estimation of Faulty Conditions due to SEE 159 -- 7.2.1 Substrate/Well/Device Level 159 -- 7.2.2 Circuit Level 162 -- 7.2.3 Chip/Processor Level 164 -- 7.2.4 Board Level 166 -- 7.2.5 Operating System Level 167 -- 7.2.6 Application Level 167 -- 7.3 In-situ Detection of Faulty Conditions due to SEE 168 -- 7.3.1 Substrate/Well Level 168 -- 7.3.2 Device Level 170 -- 7.3.3 Circuit Level 170 -- 7.3.4 Chip/Processor Level 171 -- 7.3.5 Board/OS/Application Level 174 -- 7.4 Classification of Faulty Conditions 175 -- 7.4.1 Classification of Faults 175 -- 7.4.2 Classification of Errors in Time Domain 175 -- 7.4.3 MCU Classification Techniques of Memories in Topological Space Domain 177 -- 7.4.4 Classification of Errors in Sequential Logic Devices 183 -- 7.4.5 Classification of Failures: Chip/Board Level Partial/Full Irradiation Test 183 -- 7.5 Faulty Modes in Each Hierarchy 183 -- 7.5.1 Fault Modes 183 -- 7.5.2 Error Modes 186 -- 7.5.3 Failure Modes 189 -- 7.6 Summary of Chapter 7 193 -- References 195 -- 8 Mitigation Techniques of Failures in Electronic Components and Systems 207 -- 8.1 Conventional Stack-layer Based Mitigation Techniques, Their Limitations and Improvements 207 -- 8.1.1 Substrate/Device Level 207 -- 8.1.2 Circuit/Chip/Processor Layer 211 -- 8.1.3 Multi-core Processor 225 -- 8.1.4 Board/OS/Application Level 227 -- 8.1.5 Real-Time Systems: Automotives and Avionics 229 -- 8.1.6 Limitations and Improvements 230 -- 8.2 Challenges for Hyper Mitigation Techniques 232 -- 8.2.1 Co-operation of Hardware and Software 232 -- 8.2.2 Mitigation of Failures under Variations in SEE Responses 232. 8.2.3 Cross-Layer Reliability (CLR) /Inter-Layer Built-In Reliability (LABIR) 235 -- 8.2.4 Symptom-Driven System Resilient Techniques 236 -- 8.2.5 Comparison of Mitigation Strategies for System Failure 238 -- 8.2.6 Challenges in the Near Future 238 -- 8.3 Summary of Chapter 8 240 -- References 240 -- 9 Summary 249 -- 9.1 Summary of Terrestrial Radiation Effects on ULSI Devices and Electronic Systems 249 -- 9.2 Directions and Challenges in the Future 250 -- Appendices 251 -- A.1 Hamming Code 251 -- A.2 Marching Algorithms 252 -- A.3 Why VB Is Used For Simulation? 253 -- A.4 Basic Knowledge of Visual Basic 253 -- A.5 Database Handling by Visual Basic and SQL 253 -- A.6 Algorithms in Text Handling and Sample Codes 254 -- A.7 How to Make a Self-Consistent Calculation 255 -- A.8 Sample Code for Random Selection of Hit Points in a Triangle 256 -- Index 259. |
Record Nr. | UNINA-9910132310403321 |
Ibe Eishi H. | ||
Singapore : , : John Wiley & Sons Inc., , 2015 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|
Terrestrial radiation effects in ULSI devices and electronic systems / / Eishi H. Ibe |
Autore | Ibe Eishi H. |
Pubbl/distr/stampa | Singapore : , : John Wiley & Sons Inc., , 2015 |
Descrizione fisica | 1 online resource (565 p.) |
Disciplina | 621.3815 |
Soggetto topico |
Electronic circuits - Effect of radiation on
Integrated circuits - Ultra large scale integration - Reliability Integrated circuits - Effect of radiation on |
ISBN |
1-118-47932-7
1-118-47931-9 1-118-47930-0 |
Formato | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione | eng |
Nota di contenuto |
About the Author xiii -- Preface xv -- Acknowledgements xvii -- Acronyms xix -- 1 Introduction 1 -- 1.1 Basic Knowledge on Terrestrial Secondary Particles 1 -- 1.2 CMOS Semiconductor Devices and Systems 4 -- 1.3 Two Major Fault Modes: Charge Collection and Bipolar Action 7 -- 1.4 Four Hierarchies in Faulty Conditions in Electronic Systems: Fault - Error - Hazard - Failure 12 -- 1.5 Historical Background of Soft-Error Research 14 -- 1.6 General Scope of This Book 18 -- References 18 -- 2 Terrestrial Radiation Fields 23 -- 2.1 General Sources of Radiation 23 -- 2.2 Backgrounds for Selection of Terrestrial High-Energy Particles 23 -- 2.3 Spectra at the Avionics Altitude 25 -- 2.4 Radioisotopes in the Field 28 -- 2.5 Summary of Chapter 2 31 -- References 31 -- 3 Fundamentals of Radiation Effects 33 -- 3.1 General Description of Radiation Effects 33 -- 3.2 Definition of Cross Section 35 -- 3.3 Radiation Effects by Photons (Gamma-ray and X-ray) 36 -- 3.4 Radiation Effects by Electrons (Beta-ray) 37 -- 3.5 Radiation Effects by Muons 39 -- 3.6 Radiation Effects by Protons 40 -- 3.7 Radiation Effects by Alpha-Particles 43 -- 3.8 Radiation Effects by Low-Energy Neutrons 43 -- 3.9 Radiation Effects by High-Energy Neutrons 45 -- 3.10 Radiation Effects by Heavy Ions 45 -- 3.11 Summary of Chapter 3 46 -- References 46 -- 4 Fundamentals of Electronic Devices and Systems 49 -- 4.1 Fundamentals of Electronic Components 49 -- 4.1.1 DRAM (Dynamic Random Access Memory) 49 -- 4.1.2 CMOS Inverter 49 -- 4.1.3 SRAM (Static Random Access Memory) 51 -- 4.1.4 Floating Gate Memory (Flash Memory) 51 -- 4.1.5 Sequential Logic Devices 53 -- 4.1.6 Combinational Logic Devices 54 -- 4.2 Fundamentals of Electronic Systems 55 -- 4.2.1 FPGA (Field Programmable Gate Array) 55 -- 4.2.2 Processor 56 -- 4.3 Summary of Chapter 4 58 -- References 58 -- 5 Irradiation Test Methods for Single Event Effects 61 -- 5.1 Field Test 61 -- 5.2 Alpha Ray SEE Test 64 -- 5.3 Heavy Ion Particle Irradiation Test 66 -- 5.4 Proton Beam Test 71.
5.5 Muon Test Method 75 -- 5.6 Thermal/Cold Neutron Test Methods 78 -- 5.7 High-Energy Neutron Test 80 -- 5.7.1 Medium-Energy Neutron Source by Using Radioisotopes 80 -- 5.7.2 Monoenergetic Neutron Test 80 -- 5.7.3 Quasi-Monoenergetic Neutron Test 84 -- 5.7.4 Spallation Neutron Test 90 -- 5.7.5 Attenuation of Neutron Flux and Energy 92 -- 5.8 Testing Conditions and Matters That Require Attention 94 -- 5.8.1 Memories 94 -- 5.8.2 Circuits 94 -- 5.9 Summary of Chapter 5 96 -- References 96 -- 6 Integrated Device Level Simulation Techniques 107 -- 6.1 Overall Multi-scale and Multi-physics Soft-Error Analysis System 107 -- 6.2 Relativistic Binary Collision and Nuclear Reaction Models 112 -- 6.2.1 Energy Bin Setting for a Particle Energy Spectrum 112 -- 6.2.2 Relativistic Binary Collision Model 113 -- 6.2.3 ALS (Absolute Laboratory System) and ALLS (Aligned Laboratory System) 115 -- 6.3 Intra-nuclear Cascade (INC) Model for High-Energy Neutrons and Protons 119 -- 6.3.1 Penetration of a Nucleon into a Target Nucleus 119 -- 6.3.2 Calculation of Probability of Binary Collision between Two -- Nucleons in the Target Nucleus 121 -- 6.3.3 Determination of Condition in Nucleon-Nucleon Collision 121 -- 6.4 Evaporation Model for High-Energy Neutrons and Protons 122 -- 6.5 Generalised Evaporation Model (GEM) for Inverse Reaction Cross Sections 125 -- 6.6 Neutron Capture Reaction Model 128 -- 6.7 Automated Device Modelling 129 -- 6.8 Setting of Random Position of Spallation Reaction Point in a Component 131 -- 6.9 Algorithms for Ion Tracking 133 -- 6.10 Fault Mode Models 135 -- 6.11 Calculation of Cross Section 141 -- 6.12 Prediction for Scaling Effects of Soft Error Down to 22 nm Design Rule in SRAMs 142 -- 6.13 Evaluation of Effects of Heavy Elements in Semiconductor Devices by Nuclear Spallation Reaction 144 -- 6.14 Upper Bound Fault Simulation Model 146 -- 6.15 Upper Bound Fault Simulation Results 147 -- 6.15.1 Electrons 147 -- 6.15.2 Muons 148 -- 6.15.3 Direct Ionisation by Proton 149. 6.15.4 Proton Spallation 149 -- 6.15.5 Low-Energy Neutron 151 -- 6.15.6 High-Energy Neutron Spallation 151 -- 6.15.7 Comparison of Secondary Cosmic Rays 151 -- 6.16 Upper Bound Simulation Method for SOC (System On Chip) 151 -- 6.17 Summary of Chapter 6 154 -- References 154 -- 7 Prediction, Detection and Classification Techniques of Faults, Errors and Failures 157 -- 7.1 Overview of Failures in the Field 157 -- 7.2 Prediction and Estimation of Faulty Conditions due to SEE 159 -- 7.2.1 Substrate/Well/Device Level 159 -- 7.2.2 Circuit Level 162 -- 7.2.3 Chip/Processor Level 164 -- 7.2.4 Board Level 166 -- 7.2.5 Operating System Level 167 -- 7.2.6 Application Level 167 -- 7.3 In-situ Detection of Faulty Conditions due to SEE 168 -- 7.3.1 Substrate/Well Level 168 -- 7.3.2 Device Level 170 -- 7.3.3 Circuit Level 170 -- 7.3.4 Chip/Processor Level 171 -- 7.3.5 Board/OS/Application Level 174 -- 7.4 Classification of Faulty Conditions 175 -- 7.4.1 Classification of Faults 175 -- 7.4.2 Classification of Errors in Time Domain 175 -- 7.4.3 MCU Classification Techniques of Memories in Topological Space Domain 177 -- 7.4.4 Classification of Errors in Sequential Logic Devices 183 -- 7.4.5 Classification of Failures: Chip/Board Level Partial/Full Irradiation Test 183 -- 7.5 Faulty Modes in Each Hierarchy 183 -- 7.5.1 Fault Modes 183 -- 7.5.2 Error Modes 186 -- 7.5.3 Failure Modes 189 -- 7.6 Summary of Chapter 7 193 -- References 195 -- 8 Mitigation Techniques of Failures in Electronic Components and Systems 207 -- 8.1 Conventional Stack-layer Based Mitigation Techniques, Their Limitations and Improvements 207 -- 8.1.1 Substrate/Device Level 207 -- 8.1.2 Circuit/Chip/Processor Layer 211 -- 8.1.3 Multi-core Processor 225 -- 8.1.4 Board/OS/Application Level 227 -- 8.1.5 Real-Time Systems: Automotives and Avionics 229 -- 8.1.6 Limitations and Improvements 230 -- 8.2 Challenges for Hyper Mitigation Techniques 232 -- 8.2.1 Co-operation of Hardware and Software 232 -- 8.2.2 Mitigation of Failures under Variations in SEE Responses 232. 8.2.3 Cross-Layer Reliability (CLR) /Inter-Layer Built-In Reliability (LABIR) 235 -- 8.2.4 Symptom-Driven System Resilient Techniques 236 -- 8.2.5 Comparison of Mitigation Strategies for System Failure 238 -- 8.2.6 Challenges in the Near Future 238 -- 8.3 Summary of Chapter 8 240 -- References 240 -- 9 Summary 249 -- 9.1 Summary of Terrestrial Radiation Effects on ULSI Devices and Electronic Systems 249 -- 9.2 Directions and Challenges in the Future 250 -- Appendices 251 -- A.1 Hamming Code 251 -- A.2 Marching Algorithms 252 -- A.3 Why VB Is Used For Simulation? 253 -- A.4 Basic Knowledge of Visual Basic 253 -- A.5 Database Handling by Visual Basic and SQL 253 -- A.6 Algorithms in Text Handling and Sample Codes 254 -- A.7 How to Make a Self-Consistent Calculation 255 -- A.8 Sample Code for Random Selection of Hit Points in a Triangle 256 -- Index 259. |
Record Nr. | UNINA-9910823267303321 |
Ibe Eishi H. | ||
Singapore : , : John Wiley & Sons Inc., , 2015 | ||
Materiale a stampa | ||
Lo trovi qui: Univ. Federico II | ||
|