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Analysis and design of digital integrated circuits : in deep submicron technology / David A. Hodges, Horace G. Jackson, Resve A. Saleh
| Analysis and design of digital integrated circuits : in deep submicron technology / David A. Hodges, Horace G. Jackson, Resve A. Saleh |
| Autore | Hodges, David A., 1937- |
| Edizione | [3rd ed.] |
| Pubbl/distr/stampa | Boston : McGraw-Hill Higher Education, 2004 |
| Descrizione fisica | xix, 580 p. : ill. ; 24 cm. |
| Disciplina | 621.3815 |
| Altri autori (Persone) |
Jackson, Horace G.
Saleh, Resve A., 1957- |
| Collana | McGraw-Hill series in electrical engineering |
| Soggetto topico |
Digital integrated circuits - Design and construction
Integrated circuits - Ultra large scale integration Electric circuit analysis |
| ISBN | 0072283653 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISALENTO-991003001019707536 |
Hodges, David A., 1937-
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| Boston : McGraw-Hill Higher Education, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Salento | ||
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A Baker's dozen [[electronic resource] ] : real analog solutions for digital designers / / by Bonnie Baker
| A Baker's dozen [[electronic resource] ] : real analog solutions for digital designers / / by Bonnie Baker |
| Autore | Baker Bonnie |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Newnes, 2005 |
| Descrizione fisica | 1 online resource (362 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Digital integrated circuits - Design and construction
Logic design |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-00994-6
9786611009946 0-08-047599-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Prelims; Contents; Preface; Acknowledgments; About the author; Chapter 1: Bridging the Gap Between Analog and Digital; Try to Measure Temperature Digitally; Road Blocks Abound; The Ultimate Key to Analog Success; How Analog and Digital Design Differ; Time and Its Inversion; Organizing Your Toolbox; Set Your Foundation and Move On, Out of the Box; Chapter 1 References; Chapter 2: The Basics Behind Analog-to-Digital Converters; The Key Specifications of Your ADC; Successive Approximation Register (SAR) Converters; Sigma-Delta (S-?) Converters; Conclusion; Chapter 2 References
Chapter 3: The Right ADC for the Right ApplicationClasses of Input Signals; Using an RTD for Temperature Sensing: SAR Converter or Sigma-Delta Solution?; RTD Signal Conditioning Path Using the Sigma-Delta ADC; Measuring Pressure: SAR Converter or Sigma-Delta Solution?; The Pressure Sensor Signal Conditioning Path Using a SAR ADC; Pressure Sensor Signal Conditioning Path Using a Sigma-Delta ADC; Photodiode Applications; Photosensing Signal Conditioning Path Using a SAR ADC; Photosensing Signal Conditioning Path Using a Sigma-Delta ADC; Motor Control Solutions; Conclusion; Chapter 3 References Chapter 4: Do I Filter Now, Later or Never?Key Low-Pass Analog Filter Design Parameters; Anti-Aliasing Filter Theory; Analog Filter Realization; How to Pick Your Operational Amplifier; Anti-Aliasing Filters for Near DC Analog Signals; Multiplexed Systems; Continuous Analog Signals; Matching the Anti-Aliasing Filter to the System; Chapter 4 References; Chapter 5: Finding the Perfect Op Amp for Your Perfect Circuit; Choose the Technology Wisely; Fundamental Operational Amplifier Circuits; Using these Fundamentals; Amplifier Design Pitfalls; Chapter 5 References Chapter 6: Putting the Amp Into a Linear SystemThe Basics of Amplifier DC Operation; Every Amplifier is Waiting to Oscillate, and Every Oscillator is Waiting to Amplify; Determining System Stability; Time Domain Performance; Go Forth; Chapter 6 References; Chapter 7: SPICE of Life; The Old Pencil and Paper Design Process; Is Your Simulation Fundamentally Valid?; Macromodels: What Can They Do?; Concluding Remarks; Chapter 7 References; Chapter 8: Working the Analog Problem From the Digital Domain; Pulse Width Modulators (PWM) Used as a Digital-to-Analog Converter Using the Comparator for Analog ConversionsWindow Comparator; Combining the Comparator with a Timer; Using the Timer and Comparator to Build a Sigma-Delta A/D Converter; Conclusion; Chapter 8 References; Chapter 9: Systems Where Analog and Digital Work Together; Selecting the Right Battery Chemistry for Your Application; Taking the Battery Voltage to a Useful System Voltage; Defining Power Supply Efficiency; Comparing The Three Power Devices; What is the Best Solution for Battery-Operated Systems?; Designing Low-Power Microcontroller Systems is a State of Mind; Conclusion Chapter 9 References |
| Record Nr. | UNINA-9910457300003321 |
|
Baker Bonnie
|
||
| Amsterdam ; ; Boston, : Elsevier/Newnes, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
A Baker's dozen [[electronic resource] ] : real analog solutions for digital designers / / by Bonnie Baker
| A Baker's dozen [[electronic resource] ] : real analog solutions for digital designers / / by Bonnie Baker |
| Autore | Baker Bonnie |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Newnes, 2005 |
| Descrizione fisica | 1 online resource (362 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Digital integrated circuits - Design and construction
Logic design |
| ISBN |
1-281-00994-6
9786611009946 0-08-047599-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Prelims; Contents; Preface; Acknowledgments; About the author; Chapter 1: Bridging the Gap Between Analog and Digital; Try to Measure Temperature Digitally; Road Blocks Abound; The Ultimate Key to Analog Success; How Analog and Digital Design Differ; Time and Its Inversion; Organizing Your Toolbox; Set Your Foundation and Move On, Out of the Box; Chapter 1 References; Chapter 2: The Basics Behind Analog-to-Digital Converters; The Key Specifications of Your ADC; Successive Approximation Register (SAR) Converters; Sigma-Delta (S-?) Converters; Conclusion; Chapter 2 References
Chapter 3: The Right ADC for the Right ApplicationClasses of Input Signals; Using an RTD for Temperature Sensing: SAR Converter or Sigma-Delta Solution?; RTD Signal Conditioning Path Using the Sigma-Delta ADC; Measuring Pressure: SAR Converter or Sigma-Delta Solution?; The Pressure Sensor Signal Conditioning Path Using a SAR ADC; Pressure Sensor Signal Conditioning Path Using a Sigma-Delta ADC; Photodiode Applications; Photosensing Signal Conditioning Path Using a SAR ADC; Photosensing Signal Conditioning Path Using a Sigma-Delta ADC; Motor Control Solutions; Conclusion; Chapter 3 References Chapter 4: Do I Filter Now, Later or Never?Key Low-Pass Analog Filter Design Parameters; Anti-Aliasing Filter Theory; Analog Filter Realization; How to Pick Your Operational Amplifier; Anti-Aliasing Filters for Near DC Analog Signals; Multiplexed Systems; Continuous Analog Signals; Matching the Anti-Aliasing Filter to the System; Chapter 4 References; Chapter 5: Finding the Perfect Op Amp for Your Perfect Circuit; Choose the Technology Wisely; Fundamental Operational Amplifier Circuits; Using these Fundamentals; Amplifier Design Pitfalls; Chapter 5 References Chapter 6: Putting the Amp Into a Linear SystemThe Basics of Amplifier DC Operation; Every Amplifier is Waiting to Oscillate, and Every Oscillator is Waiting to Amplify; Determining System Stability; Time Domain Performance; Go Forth; Chapter 6 References; Chapter 7: SPICE of Life; The Old Pencil and Paper Design Process; Is Your Simulation Fundamentally Valid?; Macromodels: What Can They Do?; Concluding Remarks; Chapter 7 References; Chapter 8: Working the Analog Problem From the Digital Domain; Pulse Width Modulators (PWM) Used as a Digital-to-Analog Converter Using the Comparator for Analog ConversionsWindow Comparator; Combining the Comparator with a Timer; Using the Timer and Comparator to Build a Sigma-Delta A/D Converter; Conclusion; Chapter 8 References; Chapter 9: Systems Where Analog and Digital Work Together; Selecting the Right Battery Chemistry for Your Application; Taking the Battery Voltage to a Useful System Voltage; Defining Power Supply Efficiency; Comparing The Three Power Devices; What is the Best Solution for Battery-Operated Systems?; Designing Low-Power Microcontroller Systems is a State of Mind; Conclusion Chapter 9 References |
| Record Nr. | UNINA-9910784361003321 |
|
Baker Bonnie
|
||
| Amsterdam ; ; Boston, : Elsevier/Newnes, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
A Baker's dozen : real analog solutions for digital designers / / by Bonnie Baker
| A Baker's dozen : real analog solutions for digital designers / / by Bonnie Baker |
| Autore | Baker Bonnie |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Newnes, 2005 |
| Descrizione fisica | 1 online resource (362 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Digital integrated circuits - Design and construction
Logic design |
| ISBN |
9786611009946
9781281009944 1281009946 9780080475998 008047599X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Prelims; Contents; Preface; Acknowledgments; About the author; Chapter 1: Bridging the Gap Between Analog and Digital; Try to Measure Temperature Digitally; Road Blocks Abound; The Ultimate Key to Analog Success; How Analog and Digital Design Differ; Time and Its Inversion; Organizing Your Toolbox; Set Your Foundation and Move On, Out of the Box; Chapter 1 References; Chapter 2: The Basics Behind Analog-to-Digital Converters; The Key Specifications of Your ADC; Successive Approximation Register (SAR) Converters; Sigma-Delta (S-?) Converters; Conclusion; Chapter 2 References
Chapter 3: The Right ADC for the Right ApplicationClasses of Input Signals; Using an RTD for Temperature Sensing: SAR Converter or Sigma-Delta Solution?; RTD Signal Conditioning Path Using the Sigma-Delta ADC; Measuring Pressure: SAR Converter or Sigma-Delta Solution?; The Pressure Sensor Signal Conditioning Path Using a SAR ADC; Pressure Sensor Signal Conditioning Path Using a Sigma-Delta ADC; Photodiode Applications; Photosensing Signal Conditioning Path Using a SAR ADC; Photosensing Signal Conditioning Path Using a Sigma-Delta ADC; Motor Control Solutions; Conclusion; Chapter 3 References Chapter 4: Do I Filter Now, Later or Never?Key Low-Pass Analog Filter Design Parameters; Anti-Aliasing Filter Theory; Analog Filter Realization; How to Pick Your Operational Amplifier; Anti-Aliasing Filters for Near DC Analog Signals; Multiplexed Systems; Continuous Analog Signals; Matching the Anti-Aliasing Filter to the System; Chapter 4 References; Chapter 5: Finding the Perfect Op Amp for Your Perfect Circuit; Choose the Technology Wisely; Fundamental Operational Amplifier Circuits; Using these Fundamentals; Amplifier Design Pitfalls; Chapter 5 References Chapter 6: Putting the Amp Into a Linear SystemThe Basics of Amplifier DC Operation; Every Amplifier is Waiting to Oscillate, and Every Oscillator is Waiting to Amplify; Determining System Stability; Time Domain Performance; Go Forth; Chapter 6 References; Chapter 7: SPICE of Life; The Old Pencil and Paper Design Process; Is Your Simulation Fundamentally Valid?; Macromodels: What Can They Do?; Concluding Remarks; Chapter 7 References; Chapter 8: Working the Analog Problem From the Digital Domain; Pulse Width Modulators (PWM) Used as a Digital-to-Analog Converter Using the Comparator for Analog ConversionsWindow Comparator; Combining the Comparator with a Timer; Using the Timer and Comparator to Build a Sigma-Delta A/D Converter; Conclusion; Chapter 8 References; Chapter 9: Systems Where Analog and Digital Work Together; Selecting the Right Battery Chemistry for Your Application; Taking the Battery Voltage to a Useful System Voltage; Defining Power Supply Efficiency; Comparing The Three Power Devices; What is the Best Solution for Battery-Operated Systems?; Designing Low-Power Microcontroller Systems is a State of Mind; Conclusion Chapter 9 References |
| Record Nr. | UNINA-9910962287803321 |
|
Baker Bonnie
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| Amsterdam ; ; Boston, : Elsevier/Newnes, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital Integrated Circuits : Analysis and Design, Second Edition / / John E. Ayers
| Digital Integrated Circuits : Analysis and Design, Second Edition / / John E. Ayers |
| Autore | Ayers John E. |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Boca Raton, FL : , : CRC Press, , 2011 |
| Descrizione fisica | 1 online resource (xiv, 597 pages) : illustrations |
| Disciplina | 621.3815 |
| Soggetto topico | Digital integrated circuits - Design and construction |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-315-27535-X
1-4398-9495-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | chapter 1 Introduction -- chapter 2 Fabrication -- chapter 3 Semiconductors and p-n Junctions -- chapter 4 The MOS Transistor -- chapter 5 MOS Gate Circuits -- chapter 6 Static CMOS -- chapter 7 Interconnect -- chapter 8 Dynamic CMOS -- chapter 9 Low-Power CMOS -- chapter 10 Bistable Circuits -- chapter 11 Digital Memories -- chapter 12 Input/Output and Interface Circuits. |
| Record Nr. | UNINA-9910466893103321 |
|
Ayers John E.
|
||
| Boca Raton, FL : , : CRC Press, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital Integrated Circuits : Analysis and Design, Second Edition / / John E. Ayers
| Digital Integrated Circuits : Analysis and Design, Second Edition / / John E. Ayers |
| Autore | Ayers John E. |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Boca Raton, FL : , : CRC Press, , 2011 |
| Descrizione fisica | 1 online resource (xiv, 597 pages) : illustrations |
| Disciplina | 621.3815 |
| Soggetto topico | Digital integrated circuits - Design and construction |
| ISBN |
1-000-05506-X
1-315-27535-X 1-4398-9495-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | chapter 1 Introduction -- chapter 2 Fabrication -- chapter 3 Semiconductors and p-n Junctions -- chapter 4 The MOS Transistor -- chapter 5 MOS Gate Circuits -- chapter 6 Static CMOS -- chapter 7 Interconnect -- chapter 8 Dynamic CMOS -- chapter 9 Low-Power CMOS -- chapter 10 Bistable Circuits -- chapter 11 Digital Memories -- chapter 12 Input/Output and Interface Circuits. |
| Record Nr. | UNINA-9910796752203321 |
|
Ayers John E.
|
||
| Boca Raton, FL : , : CRC Press, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital Integrated Circuits : Analysis and Design, Second Edition / / John E. Ayers
| Digital Integrated Circuits : Analysis and Design, Second Edition / / John E. Ayers |
| Autore | Ayers John E. |
| Edizione | [Second edition.] |
| Pubbl/distr/stampa | Boca Raton, FL : , : CRC Press, , 2011 |
| Descrizione fisica | 1 online resource (xiv, 597 pages) : illustrations |
| Disciplina | 621.3815 |
| Soggetto topico | Digital integrated circuits - Design and construction |
| ISBN |
1-000-05506-X
1-315-27535-X 1-4398-9495-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | chapter 1 Introduction -- chapter 2 Fabrication -- chapter 3 Semiconductors and p-n Junctions -- chapter 4 The MOS Transistor -- chapter 5 MOS Gate Circuits -- chapter 6 Static CMOS -- chapter 7 Interconnect -- chapter 8 Dynamic CMOS -- chapter 9 Low-Power CMOS -- chapter 10 Bistable Circuits -- chapter 11 Digital Memories -- chapter 12 Input/Output and Interface Circuits. |
| Record Nr. | UNINA-9910969668203321 |
|
Ayers John E.
|
||
| Boca Raton, FL : , : CRC Press, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Engineering the CMOS library [[electronic resource] ] : enhancing digital design kits for competitive silicon / / David Doman
| Engineering the CMOS library [[electronic resource] ] : enhancing digital design kits for competitive silicon / / David Doman |
| Autore | Doman David |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : John Wiley & Sons, c2012 |
| Descrizione fisica | 1 online resource (343 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Digital integrated circuits - Design and construction
Metal oxide semiconductors, Complementary Industrial efficiency |
| ISBN |
1-280-59206-0
9786613621894 1-118-27313-3 1-118-27314-1 1-118-27311-7 |
| Classificazione | TEC008050 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon; Contents; Preface; Acknowledgments; 1: Introduction; 1.1: Adding Project-Specific Functions, Drive Strengths, Views, and Corners; 1.2: What Is a DDK?; 2: Stdcell Libraries; 2.1: Lesson from the Real World: Manager's Perspective and Engineer's Perspective; 2.2: What Is a Stdcell?; 2.2.1: Combinational Functions; 2.2.2: Sequential Functions; 2.2.3: Clock Functions; 2.3: Extended Library Offerings; 2.3.1: Low-Power Support; 2.4: Boutique Library Offerings; 2.5: Concepts for Further Study; 3: IO Libraries
3.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 3.2: Extension Capable Architectures versus Function Complete Architectures; 3.3: Electrostatic Discharge Considerations; 3.3.1: Footprints; 3.3.2: Custom Design Versus Standard IO Design Comparison; 3.3.3: The Need for Maintaining Multiple IO Footprint Regions on an IC; 3.3.4: Circuit Under Pad; 3.4: Concepts for Further Study; 4: Memory Compilers; 4.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 4.2: Single Ports, Dual Ports, and ROM: The Compiler 4.3: Nonvolatile Memories: The Block 4.4: Special-Purpose Memories: The Custom; 4.5: Concepts for Further Study; 5: Other Functions; 5.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 5.2: Phase-Locked Loops, Power-On Resets, and Other Small-Scale Integration Analogs; 5.3: Low-Power Support Structures; 5.4: Stitching Structures; 5.4.1: Core-Fill Cells; 5.4.2: IO-Fill Cells; 5.4.3: DECAP Cells; 5.4.4: CMP-Fill Cells; 5.4.5: Spare Logic Cells; 5.4.6: Probe-Point Cells; 5.4.7: Antenna Diodes; 5.4.8: Test-Debug Diodes; 5.4.9: Others 5.5: Hard, Firm, and Soft Boxes 5.6: Concepts for Further Study; 6: Physical Views; 6.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 6.2: Picking an Architecture; 6.3: Measuring Density; 6.4: The Need and the Way to Work with Fabrication Houses; 6.5: Concepts for Further Study; 7: SPICE; 7.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 7.2: Why a Tool More Than 40 Years Old Is Still Useful; 7.3: Accuracy, Reality, and Why SPICE Results Must be Viewed with a Wary Eye; 7.4: Sufficient Parasitics 7.5: Concepts for Further Study 8: Timing Views; 8.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 8.2: Performance Limits and Measurement; 8.3: Default Versus Conditional Arcs; 8.4: Break-Point Optimization; 8.5: A Word on Setup and Hold; 8.6: Failure Mechanisms and Roll-Off; 8.7: Supporting Efficient Synthesis; 8.7.1: SPICE, Monotonic Arrays, and Favorite Stdcells; 8.7.2: SPICE, Positive Arrays, and Useful Skew; 8.8: Supporting Efficient Timing Closure; 8.9: Design Corner Specific Timing Views; 8.10: Nonlinear Timing Views are so ""Old Hat"" . . . 8.11: Concepts for Further Study |
| Record Nr. | UNINA-9910141337703321 |
|
Doman David
|
||
| Hoboken, N.J., : John Wiley & Sons, c2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Engineering the CMOS library : enhancing digital design kits for competitive silicon / / David Doman
| Engineering the CMOS library : enhancing digital design kits for competitive silicon / / David Doman |
| Autore | Doman David |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : John Wiley & Sons, c2012 |
| Descrizione fisica | 1 online resource (343 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Digital integrated circuits - Design and construction
Metal oxide semiconductors, Complementary Industrial efficiency |
| ISBN |
9786613621894
9781280592065 1280592060 9781118273135 1118273133 9781118273142 1118273141 9781118273111 1118273117 |
| Classificazione | TEC008050 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon; Contents; Preface; Acknowledgments; 1: Introduction; 1.1: Adding Project-Specific Functions, Drive Strengths, Views, and Corners; 1.2: What Is a DDK?; 2: Stdcell Libraries; 2.1: Lesson from the Real World: Manager's Perspective and Engineer's Perspective; 2.2: What Is a Stdcell?; 2.2.1: Combinational Functions; 2.2.2: Sequential Functions; 2.2.3: Clock Functions; 2.3: Extended Library Offerings; 2.3.1: Low-Power Support; 2.4: Boutique Library Offerings; 2.5: Concepts for Further Study; 3: IO Libraries
3.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 3.2: Extension Capable Architectures versus Function Complete Architectures; 3.3: Electrostatic Discharge Considerations; 3.3.1: Footprints; 3.3.2: Custom Design Versus Standard IO Design Comparison; 3.3.3: The Need for Maintaining Multiple IO Footprint Regions on an IC; 3.3.4: Circuit Under Pad; 3.4: Concepts for Further Study; 4: Memory Compilers; 4.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 4.2: Single Ports, Dual Ports, and ROM: The Compiler 4.3: Nonvolatile Memories: The Block 4.4: Special-Purpose Memories: The Custom; 4.5: Concepts for Further Study; 5: Other Functions; 5.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 5.2: Phase-Locked Loops, Power-On Resets, and Other Small-Scale Integration Analogs; 5.3: Low-Power Support Structures; 5.4: Stitching Structures; 5.4.1: Core-Fill Cells; 5.4.2: IO-Fill Cells; 5.4.3: DECAP Cells; 5.4.4: CMP-Fill Cells; 5.4.5: Spare Logic Cells; 5.4.6: Probe-Point Cells; 5.4.7: Antenna Diodes; 5.4.8: Test-Debug Diodes; 5.4.9: Others 5.5: Hard, Firm, and Soft Boxes 5.6: Concepts for Further Study; 6: Physical Views; 6.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 6.2: Picking an Architecture; 6.3: Measuring Density; 6.4: The Need and the Way to Work with Fabrication Houses; 6.5: Concepts for Further Study; 7: SPICE; 7.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 7.2: Why a Tool More Than 40 Years Old Is Still Useful; 7.3: Accuracy, Reality, and Why SPICE Results Must be Viewed with a Wary Eye; 7.4: Sufficient Parasitics 7.5: Concepts for Further Study 8: Timing Views; 8.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 8.2: Performance Limits and Measurement; 8.3: Default Versus Conditional Arcs; 8.4: Break-Point Optimization; 8.5: A Word on Setup and Hold; 8.6: Failure Mechanisms and Roll-Off; 8.7: Supporting Efficient Synthesis; 8.7.1: SPICE, Monotonic Arrays, and Favorite Stdcells; 8.7.2: SPICE, Positive Arrays, and Useful Skew; 8.8: Supporting Efficient Timing Closure; 8.9: Design Corner Specific Timing Views; 8.10: Nonlinear Timing Views are so ""Old Hat"" . . . 8.11: Concepts for Further Study |
| Altri titoli varianti |
Enhancing digital design kits for competitive silicon
Engineering the complementary metal-oxide-semiconductor library |
| Record Nr. | UNINA-9910808850803321 |
|
Doman David
|
||
| Hoboken, N.J., : John Wiley & Sons, c2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Synchronization and arbitration in digital systems [[electronic resource] /] / David Kinniment
| Synchronization and arbitration in digital systems [[electronic resource] /] / David Kinniment |
| Autore | Kinniment D. J (David John) |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, NJ, : J. Wiley & Sons, 2007 |
| Descrizione fisica | 1 online resource (282 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Timing circuits - Design and construction
Digital integrated circuits - Design and construction Synchronization |
| ISBN |
1-281-31822-1
9786611318222 0-470-51714-X 0-470-51713-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Synchronization and Arbitration in Digital Systems; Contents; Preface; List of Contributors; Acknowledgements; 1 Synchronization, Arbitration and Choice; 1.1 INTRODUCTION; 1.2 THE PROBLEM OF CHOICE; 1.3 CHOICE IN ELECTRONICS; 1.4 ARBITRATION; 1.5 CONTINUOUS AND DISCRETE QUANTITIES; 1.6 TIMING; 1.7 BOOK STRUCTURE; Part I; 2 Modelling Metastability; 2.1 THE SYNCHRONIZER; 2.2 LATCH MODEL; 2.3 FAILURE RATES; 2.3.1 Event Histograms and MTBF; 2.4 LATCHES AND FLIP-FLOPS; 2.5 CLOCK BACK EDGE; 3 Circuits; 3.1 LATCHES AND METASTABILITY FILTERS; 3.2 EFFECTS OF FILTERING; 3.3 THE JAMB LATCH
3.3.1 Jamb Latch Flip-. op3.4 LOW COUPLING LATCH; 3.5 THE Q-FLOP; 3.6 THE MUTEX; 3.7 ROBUST SYNCHRONIZER; 3.8 THE TRI-FLOP; 4 Noise and its Effects; 4.1 NOISE; 4.2 EFFECT OF NOISE ON A SYNCHRONIZER; 4.3 MALICIOUS INPUTS; 4.3.1 Synchronous Systems; 4.3.2 Asynchronous Systems; 5 Metastability Measurements; 5.1 CIRCUIT SIMULATION; 5.1.1 Time Step Control; 5.1.2 Long-term τ; 5.1.3 Using Bisection; 5.2 SYNCHRONIZER FLIP-FLOP TESTING; 5.3 RISING AND FALLING EDGES; 5.4 DELAY-BASED MEASUREMENT; 5.5 DEEP METASTABILITY; 5.6 BACK EDGE MEASUREMENT; 5.7 MEASURE AND SELECT; 5.7.1 Failure Measurement 5.7.2 Synchronizer Selection6 Conclusions Part I; Part II; 7 Synchronizers in Systems; 7.1 LATENCY AND THROUGHPUT; 7.2 FIFO SYNCHRONIZER; 7.3 AVOIDING SYNCHRONIZATION; 7.4 PREDICTIVE SYNCHRONIZERS; 7.5 OTHER LOW-LATENCY SYNCHRONIZERS; 7.5.1 Locally Delayed Latching (LDL); 7.5.2 Speculative Synchronization; 7.5.2.1 Synchronization error detection; 7.5.2.2 Pipelining; 7.5.2.3 Recovery; 7.6 ASYNCHRONOUS COMMUNICATION MECHANISMS (ACM); 7.6.1 Slot Mechanisms; 7.6.2 Three-slot Mechanism; 7.6.3 Four-slot Mechanism; 7.6.4 Hardware Design and Metastability; 7.7 SOME COMMON SYNCHRONIZER DESIGN ISSUES 7.7.1 Unsynchronized Paths7.7.1.1 No acknowledge; 7.7.1.2 Unsynchronized reset back edge; 7.7.2 Moving Metastability Out of Sight; 7.7.2.1 Disturbing a metastable latch; 7.7.2.2 The second chance; 7.7.2.3 Metastability blocker; 7.7.3 Multiple Synchronizer Flops; 7.7.3.1 The data synchronizer; 7.7.3.2 The redundant synchronizer; 8 Networks and Interconnects; 8.1 COMMUNICATION ON CHIP; 8.1.1 Comparison of Network Architectures; 8.2 INTERCONNECT LINKS; 8.3 SERIAL LINKS; 8.3.1 Using One Line; 8.3.2 Using Two Lines; 8.4 DIFFERENTIAL SIGNALLING; 8.5 PARALLEL LINKS; 8.5.1 One Hot Codes 8.5.2 Transition Signalling8.5.3 n of m Codes; 8.5.4 Phase Encoding; 8.5.4.1 Phase encoding sender; 8.5.4.2 Receiver; 8.5.5 Time Encoding; 8.6 PARALLEL SERIAL LINKS; 9 Pausible and Stoppable Clocks in GALS; 9.1 GALS CLOCK GENERATORS; 9.2 CLOCK TREE DELAYS; 9.3 A GALS WRAPPER; 10 Conclusions Part II; Part III; 11 Arbitration; 11.1 INTRODUCTION; 11.2 ARBITER DEFINITION; 11.3 ARBITER APPLICATIONS, RESOURCE ALLOCATION POLICIES AND COMMON ARCHITECTURES; 11.4 SIGNAL TRANSITION GRAPHS, OUR MAIN MODELLING LANGUAGE; 12 Simple Two-way Arbiters; 12.1 BASIC CONCEPTS AND CONVENTIONS 12.1.1 Two-phase or Non-return-to-zero (NRZ) Protocols |
| Record Nr. | UNINA-9910145563703321 |
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Kinniment D. J (David John)
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| Hoboken, NJ, : J. Wiley & Sons, 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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