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2010 Formal Methods in Computer-Aided Design
| 2010 Formal Methods in Computer-Aided Design |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2010 |
| Descrizione fisica | 1 online resource (vii, 279 pages) : illustrations |
| Disciplina | 004.0151 |
| Soggetto topico |
Formal methods (Computer science)
Digital integrated circuits - Computer-aided design |
| ISBN | 0-9835678-0-8 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996203486203316 |
| [Place of publication not identified], : IEEE, 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2010 Formal Methods in Computer-Aided Design
| 2010 Formal Methods in Computer-Aided Design |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2010 |
| Descrizione fisica | 1 online resource (vii, 279 pages) : illustrations |
| Disciplina | 004.0151 |
| Soggetto topico |
Formal methods (Computer science)
Digital integrated circuits - Computer-aided design |
| ISBN | 0-9835678-0-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910140988503321 |
| [Place of publication not identified], : IEEE, 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
FMCAD 2009 : proceedings of 9th International Conference 2009 Formal Methods in Computer-Aided Design : 15-18 November 2009, Austin, Texas, USA / / technically sponsored by, IEEE Council on Electronic Design Automation ; in cooperation with ACM SIGDA
| FMCAD 2009 : proceedings of 9th International Conference 2009 Formal Methods in Computer-Aided Design : 15-18 November 2009, Austin, Texas, USA / / technically sponsored by, IEEE Council on Electronic Design Automation ; in cooperation with ACM SIGDA |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2009 |
| Descrizione fisica | 1 online resource (115 pages) |
| Disciplina | 621 |
| Soggetto topico |
Integrated circuits - Verification
Digital integrated circuits - Computer-aided design |
| ISBN | 1-5090-6978-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910332545903321 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
FMCAD 2009 : proceedings of 9th International Conference 2009 Formal Methods in Computer-Aided Design : 15-18 November 2009, Austin, Texas, USA / / technically sponsored by, IEEE Council on Electronic Design Automation ; in cooperation with ACM SIGDA
| FMCAD 2009 : proceedings of 9th International Conference 2009 Formal Methods in Computer-Aided Design : 15-18 November 2009, Austin, Texas, USA / / technically sponsored by, IEEE Council on Electronic Design Automation ; in cooperation with ACM SIGDA |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2009 |
| Descrizione fisica | 1 online resource (115 pages) |
| Disciplina | 621 |
| Soggetto topico |
Integrated circuits - Verification
Digital integrated circuits - Computer-aided design |
| ISBN | 1-5090-6978-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996577835703316 |
| Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
FMCAD 2017 : proceedings of the 17th Conference on Formal Methods in Computer-Aided Design : October 2-6, 2017, TU Wien, Vienna, Austria / / edited by Daryl Stewart and Georg Weissenbacher
| FMCAD 2017 : proceedings of the 17th Conference on Formal Methods in Computer-Aided Design : October 2-6, 2017, TU Wien, Vienna, Austria / / edited by Daryl Stewart and Georg Weissenbacher |
| Pubbl/distr/stampa | New York : , : IEEE, , 2017 |
| Descrizione fisica | 1 online resource (229 pages) |
| Soggetto topico |
Digital integrated circuits - Computer-aided design
Integrated circuits - Verification Formal methods (Computer science) |
| ISBN | 0-9835678-7-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996279680703316 |
| New York : , : IEEE, , 2017 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
FMCAD 2017 : proceedings of the 17th Conference on Formal Methods in Computer-Aided Design : October 2-6, 2017, TU Wien, Vienna, Austria / / edited by Daryl Stewart and Georg Weissenbacher
| FMCAD 2017 : proceedings of the 17th Conference on Formal Methods in Computer-Aided Design : October 2-6, 2017, TU Wien, Vienna, Austria / / edited by Daryl Stewart and Georg Weissenbacher |
| Pubbl/distr/stampa | New York : , : IEEE, , 2017 |
| Descrizione fisica | 1 online resource (229 pages) |
| Soggetto topico |
Digital integrated circuits - Computer-aided design
Integrated circuits - Verification Formal methods (Computer science) |
| ISBN | 0-9835678-7-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910228956503321 |
| New York : , : IEEE, , 2017 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Formal methods in computer-aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings / / Ganesh Gopalakrishnan, Phillip Windley (editors)
| Formal methods in computer-aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings / / Ganesh Gopalakrishnan, Phillip Windley (editors) |
| Edizione | [1st ed. 1998.] |
| Pubbl/distr/stampa | Berlin : , : Springer, , [1998] |
| Descrizione fisica | 1 online resource (X, 538 p.) |
| Disciplina | 621.392 |
| Collana | Lecture notes in computer science |
| Soggetto topico |
Digital integrated circuits - Computer-aided design
Computer engineering - Computer-aided design Integrated circuits - Verification Automatic theorem proving Formal methods (Computer science) |
| ISBN | 3-540-49519-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification -- Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution -- Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking -- Solving Bit-Vector Equations -- The Formal Design of 1M-Gate ASICs -- Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations -- A Tutorial on Stålmarck’s Proof Procedure for Propositional Logic -- Almana: A BDD Minimization Tool Integrating Heuristic and RewritingMethods -- Bisimulation Minimization in an Automata-Theoretic Verification Framework -- Automatic Verification of Mixed-Level Logic Circuits -- A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk -- Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints -- Using MTBDDs for Composition and Model Checking of Real-Time Systems -- Formal Methods in CAD from an Industrial Perspective -- A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool -- Combined Formal Post- and Presynthesis Verification in High Level Synthesis -- Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem -- A Performance Study of BDD-Based Model Checking -- Symbolic Model Checking Visualization -- Input Elimination and Abstraction in Model Checking -- Symbolic Simulation of the JEM1 Microprocessor -- Symbolic Simulation: An ACL2 Approach -- Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study -- Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification -- Formally Verifying Data and Control with Weak Reachability Invariants -- Generalized Reversible Rules -- An Assume-Guarantee Rule for Checking Simulation -- Three Approaches to Hardware Verification: HOL, MDG, and VIS Compared -- An Instruction Set Process Calculus -- Techniques for Implicit State Enumeration of EFSMs -- Model Checking on Product Structures -- BDDNOW: A Parallel BDD Package -- Model Checking VHDL with CV -- Alexandria: A Tool for Hierarchical Verification -- PV: An Explicit Enumeration Model-Checker. |
| Record Nr. | UNINA-9910143467903321 |
| Berlin : , : Springer, , [1998] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Formal methods in computer-aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings / / Ganesh Gopalakrishnan, Phillip Windley (editors)
| Formal methods in computer-aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings / / Ganesh Gopalakrishnan, Phillip Windley (editors) |
| Edizione | [1st ed. 1998.] |
| Pubbl/distr/stampa | Berlin : , : Springer, , [1998] |
| Descrizione fisica | 1 online resource (X, 538 p.) |
| Disciplina | 621.392 |
| Collana | Lecture notes in computer science |
| Soggetto topico |
Digital integrated circuits - Computer-aided design
Computer engineering - Computer-aided design Integrated circuits - Verification Automatic theorem proving Formal methods (Computer science) |
| ISBN | 3-540-49519-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification -- Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution -- Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking -- Solving Bit-Vector Equations -- The Formal Design of 1M-Gate ASICs -- Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations -- A Tutorial on Stålmarck’s Proof Procedure for Propositional Logic -- Almana: A BDD Minimization Tool Integrating Heuristic and RewritingMethods -- Bisimulation Minimization in an Automata-Theoretic Verification Framework -- Automatic Verification of Mixed-Level Logic Circuits -- A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk -- Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints -- Using MTBDDs for Composition and Model Checking of Real-Time Systems -- Formal Methods in CAD from an Industrial Perspective -- A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool -- Combined Formal Post- and Presynthesis Verification in High Level Synthesis -- Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem -- A Performance Study of BDD-Based Model Checking -- Symbolic Model Checking Visualization -- Input Elimination and Abstraction in Model Checking -- Symbolic Simulation of the JEM1 Microprocessor -- Symbolic Simulation: An ACL2 Approach -- Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study -- Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification -- Formally Verifying Data and Control with Weak Reachability Invariants -- Generalized Reversible Rules -- An Assume-Guarantee Rule for Checking Simulation -- Three Approaches to Hardware Verification: HOL, MDG, and VIS Compared -- An Instruction Set Process Calculus -- Techniques for Implicit State Enumeration of EFSMs -- Model Checking on Product Structures -- BDDNOW: A Parallel BDD Package -- Model Checking VHDL with CV -- Alexandria: A Tool for Hierarchical Verification -- PV: An Explicit Enumeration Model-Checker. |
| Record Nr. | UNISA-996465910703316 |
| Berlin : , : Springer, , [1998] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Formal Methods in Computer-Aided Design
| Formal Methods in Computer-Aided Design |
| Pubbl/distr/stampa | Los Alamitos, California : , : IEEE Computer Society |
| Descrizione fisica | online resource |
| Disciplina | 621.3815 |
| Soggetto topico |
Digital integrated circuits - Computer-aided design
Digital integrated circuits - Design and construction - Data processing Computer-aided design Automatic theorem proving Integrated circuits - Verification |
| Soggetto genere / forma |
Periodicals.
Conference papers and proceedings. |
| ISSN | 2642-732X |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
Proceedings of
Proceedings of Formal Methods in Computer-Aided Design FMCAD .. |
| Record Nr. | UNINA-9910626187403321 |
| Los Alamitos, California : , : IEEE Computer Society | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Formal methods in computer-aided design : eight international conference, FMCAD 2008, Portland, Oregon, USA, November 17-20, 2008 : proceedings
| Formal methods in computer-aided design : eight international conference, FMCAD 2008, Portland, Oregon, USA, November 17-20, 2008 : proceedings |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 2008 |
| Disciplina | 621.39/2 |
| Soggetto topico |
Digital integrated circuits - Computer-aided design
Integrated circuits - Verification Formal methods (Computer science) - Mathematics - Design and construction Digital integrated circuits Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
1-5090-7875-4
1-4244-2736-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996204380203316 |
| [Place of publication not identified], : IEEE, 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
