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Analog and digital electronic circuits : fundamentals, analysis, and applications / / R. Prasad
| Analog and digital electronic circuits : fundamentals, analysis, and applications / / R. Prasad |
| Autore | Prasad R (Emeritus Professor of Physics) |
| Edizione | [1st ed. 2021.] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2021] |
| Descrizione fisica | 1 online resource (XVIII, 965 p. 838 illus., 276 illus. in color.) |
| Disciplina | 621.3815 |
| Collana | Undergraduate lecture notes in physics |
| Soggetto topico | Digital integrated circuits |
| ISBN | 3-030-65129-0 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Part- I: Circuit Analysis -- Chapter 1 - Electrical Network Thorems and Their Applications -- Chapter 2 - Circuit analyses using Laplace transform -- Chapter 3 - First and second order circuits, Phasor and Fourier analysis -- Part- II: Analog Electronics -- Chapter 4 - Electrical properties of materials -- Chapter 5 - p-n junction diode: a basic non-linear device- Chapter 6 - Bipolar Junction (BJT) and Field Effect (FET) Transistor -- Chapter 7 - Feedback in amplifiers -- Chapter 8 - Operational Amplifier -- Part - III: Digital Electronics -- Chapter 9 - Electronic Signals and Logic Gates -- Chapter 10 - Some Applications of Logic Gates -- Chapter 11 -Special Circuits and Devices. |
| Record Nr. | UNINA-9910484383003321 |
Prasad R (Emeritus Professor of Physics)
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| Cham, Switzerland : , : Springer, , [2021] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Analog and digital electronic circuits : fundamentals, analysis, and applications / / R. Prasad
| Analog and digital electronic circuits : fundamentals, analysis, and applications / / R. Prasad |
| Autore | Prasad R (Emeritus Professor of Physics) |
| Edizione | [1st ed. 2021.] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2021] |
| Descrizione fisica | 1 online resource (XVIII, 965 p. 838 illus., 276 illus. in color.) |
| Disciplina | 621.3815 |
| Collana | Undergraduate lecture notes in physics |
| Soggetto topico | Digital integrated circuits |
| ISBN | 3-030-65129-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Part- I: Circuit Analysis -- Chapter 1 - Electrical Network Thorems and Their Applications -- Chapter 2 - Circuit analyses using Laplace transform -- Chapter 3 - First and second order circuits, Phasor and Fourier analysis -- Part- II: Analog Electronics -- Chapter 4 - Electrical properties of materials -- Chapter 5 - p-n junction diode: a basic non-linear device- Chapter 6 - Bipolar Junction (BJT) and Field Effect (FET) Transistor -- Chapter 7 - Feedback in amplifiers -- Chapter 8 - Operational Amplifier -- Part - III: Digital Electronics -- Chapter 9 - Electronic Signals and Logic Gates -- Chapter 10 - Some Applications of Logic Gates -- Chapter 11 -Special Circuits and Devices. |
| Record Nr. | UNISA-996466731203316 |
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Prasad R (Emeritus Professor of Physics)
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| Cham, Switzerland : , : Springer, , [2021] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Continuous-time digital front-ends for multistandard wireless transmission / / Pieter A.J. Nuyts, Patrick Reynaert, Wim Dehaene
| Continuous-time digital front-ends for multistandard wireless transmission / / Pieter A.J. Nuyts, Patrick Reynaert, Wim Dehaene |
| Autore | Nuyts Pieter A. J |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , 2014 |
| Descrizione fisica | 1 online resource (xxv, 309 pages) : illustrations |
| Disciplina | 621.39732 |
| Collana | Analog Circuits and Signal Processing |
| Soggetto topico | Digital integrated circuits |
| ISBN | 3-319-03925-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Digital Transmitter Architectures: Overview -- High-Level Analysis of Fully Digital PWM Transmitters -- Continuous-time Digital Design Techniques -- A 65-nm CMOS Fully Digital Reconfigurable Transmitter Front-End for Class-E PA based on Baseband PWM -- A 40-nm CMOS Fully Digital Reconfigurable Transmitter with Class-D Pas using Baseband and RF PWM -- Conclusions and Future Work. |
| Record Nr. | UNINA-9910299481703321 |
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Nuyts Pieter A. J
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| Cham, Switzerland : , : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Digital design [[electronic resource]] : with a introduction to the verilog hdl / / M. Morris Mano, Michael D. Ciletti ; international edition contributions by B.R. Chandavarkar
| Digital design [[electronic resource]] : with a introduction to the verilog hdl / / M. Morris Mano, Michael D. Ciletti ; international edition contributions by B.R. Chandavarkar |
| Autore | Mano M. Morris <1927-> |
| Edizione | [Fifth edition, International edition.] |
| Pubbl/distr/stampa | Upper Saddle River, New Jersey : , : Pearson Prentice Hall, , [2013] |
| Descrizione fisica | 1 online resource (564 pages) |
| Disciplina | 621.395 |
| Soggetto topico |
Electronic digital computers - Circuits
Logic circuits Logic design Digital integrated circuits |
| ISBN | 0-273-77546-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover -- Contents -- Preface -- 1 Digital Systems and Binary Numbers -- 1.1 Digital Systems -- 1.2 Binary Numbers -- 1.3 Number-Base Conversions -- 1.4 Octal and Hexadecimal Numbers -- 1.5 Complements of Numbers -- 1.6 Signed Binary Numbers -- 1.7 Binary Codes -- 1.8 Binary Storage and Registers -- 1.9 Binary Logic -- 2 Boolean Algebra and Logic Gates -- 2.1 Introduction -- 2.2 Basic Definitions -- 2.3 Axiomatic Definition of Boolean Algebra -- 2.4 Basic Theorems and Properties of Boolean Algebra -- 2.5 Boolean Functions -- 2.6 Canonical and Standard Forms -- 2.7 Other Logic Operations -- 2.8 Digital Logic Gates -- 2.9 Integrated Circuits -- 3 Gate-Level Minimization -- 3.1 Introduction -- 3.2 The Map Method -- 3.3 Four-Variable K-Map -- 3.4 Product-of-Sums Simplification -- 3.5 Don't-Care Conditions -- 3.6 NAND and NOR Implementation -- 3.7 Other Two-Level Implementations -- 3.8 Exclusive-OR Function -- 3.9 Hardware Description Language -- 4 Combinational Logic -- 4.1 Introduction -- 4.2 Combinational Circuits -- 4.3 Analysis Procedure -- 4.4 Design Procedure -- 4.5 Binary Adder-Subtractor -- 4.6 Decimal Adder -- 4.7 Binary Multiplier -- 4.8 Magnitude Comparator -- 4.9 Decoders -- 4.10 Encoders -- 4.11 Multiplexers -- 4.12 HDL Models of Combinational Circuits -- 5 Synchronous Sequential Logic -- 5.1 Introduction -- 5.2 Sequential Circuits -- 5.3 Storage Elements: Latches -- 5.4 Storage Elements: Flip-Flops -- 5.5 Analysis of Clocked Sequential Circuits -- 5.6 Synthesizable HDL Models of Sequential Circuits -- 5.7 State Reduction and Assignment -- 5.8 Design Procedure -- 6 Registers and Counters -- 6.1 Registers -- 6.2 Shift Registers -- 6.3 Ripple Counters -- 6.4 Synchronous Counters -- 6.5 Other Counters -- 6.6 HDL for Registers and Counters -- 7 Memory and Programmable Logic -- 7.1 Introduction -- 7.2 Random-Access Memory.
7.3 Memory Decoding -- 7.4 Error Detection and Correction -- 7.5 Read-Only Memory -- 7.6 Programmable Logic Array -- 7.7 Programmable Array Logic -- 7.8 Sequential Programmable Devices -- 8 Design at the Register Transfer Level -- 8.1 Introduction -- 8.2 Register Transfer Level Notation -- 8.3 Register Transfer Level in HDL -- 8.4 Algorithmic State Machines (ASMs) -- 8.5 Design Example (ASMD Chart) -- 8.6 HDL Description of Design Example -- 8.7 Sequential Binary Multiplier -- 8.8 Control Logic -- 8.9 HDL Description of Binary Multiplier -- 8.10 Design with Multiplexers -- 8.11 Race-Free Design (Software Race Conditions) -- 8.12 Latch-Free Design (Why Waste Silicon?) -- 8.13 Other Language Features -- 9 Laboratory Experiments with Standard ICs and FPGAs -- 9.1 Introduction to Experiments -- 9.2 Experiment 1: Binary and Decimal Numbers -- 9.3 Experiment 2: Digital Logic Gates -- 9.4 Experiment 3: Simplification of Boolean Functions -- 9.5 Experiment 4: Combinational Circuits -- 9.6 Experiment 5: Code Converters -- 9.7 Experiment 6: Design with Multiplexers -- 9.8 Experiment 7: Adders and Subtractors -- 9.9 Experiment 8: Flip-Flops -- 9.10 Experiment 9: Sequential Circuits -- 9.11 Experiment 10: Counters -- 9.12 Experiment 11: Shift Registers -- 9.13 Experiment 12: Serial Addition -- 9.14 Experiment 13: Memory Unit -- 9.15 Experiment 14: Lamp Handball -- 9.16 Experiment 15: Clock-Pulse Generator -- 9.17 Experiment 16: Parallel Adder and Accumulator -- 9.18 Experiment 17: Binary Multiplier -- 9.19 Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAs -- 10 Standard Graphic Symbols -- 10.1 Rectangular-Shape Symbols -- 10.2 Qualifying Symbols -- 10.3 Dependency Notation -- 10.4 Symbols for Combinational Elements -- 10.5 Symbols for Flip-Flops -- 10.6 Symbols for Registers -- 10.7 Symbols for Counters -- 10.8 Symbol for RAM -- Appendix. Answers to Selected Problems -- Index. |
| Record Nr. | UNINA-9910150213903321 |
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Mano M. Morris <1927->
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| Upper Saddle River, New Jersey : , : Pearson Prentice Hall, , [2013] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Digital design from the VLSI perspective : concepts for VLSI beginners / / Vaibbhav Taraate
| Digital design from the VLSI perspective : concepts for VLSI beginners / / Vaibbhav Taraate |
| Autore | Taraate Vaibbhav |
| Pubbl/distr/stampa | Singapore : , : Springer, , [2023] |
| Descrizione fisica | 1 online resource (309 pages) |
| Disciplina | 621.3815 |
| Soggetto topico |
Digital integrated circuits - Design and construction
Integrated circuits - Very large scale integration Digital integrated circuits |
| ISBN |
9789811946523
9789811946516 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Acknowledgements -- Contents -- About the Author -- 1 Introduction -- 1.1 Number Representation -- 1.2 Digital Systems: System Perspective -- 1.3 Processors and Their Role -- 1.4 The Important Terminology: System Perspective -- 1.5 System Design Components -- 1.6 Few Important Considerations -- 1.7 Summary -- 2 Basics of Design Elements -- 2.1 Combinational Design Elements -- 2.1.1 Logic Gates and Their Use in the Design -- 2.2 De Morgen's Theorems -- 2.2.1 NAND is Equal to Bubbled OR -- 2.2.2 NOR is Equal to Bubbled and -- 2.3 Level Versus Edge Sensitive Elements -- 2.3.1 Latches and Their Use in the Design -- 2.3.2 Edge Sensitive Elements and Their Role -- 2.4 Summary -- 3 System and Architecture Design -- 3.1 Architecture of the Design -- 3.2 Micro-Architecture of the Design -- 3.3 System Design Architecture -- 3.4 Design for the Glue Logic -- 3.5 Application of 2-variable Karnaugh Maps -- 3.6 Let Us Design Two Variable Function -- 3.7 SOP Terms and Boolean Expression -- 3.8 POS Terms and Expression -- 3.9 Design of Glue or Combinational Using Minimum Logic Gates -- 3.10 Summary -- 4 Combinational Logic and Design Techniques -- 4.1 Let Us Design Few Boolean Functions -- 4.2 Arithmetic Resources -- 4.2.1 Half Adder -- 4.2.2 Half Subtractor -- 4.2.3 Full Adder -- 4.2.4 Full Adder Using Half Adders -- 4.3 Role of Data Control Elements -- 4.4 The Multi-Bit Adder and Subtractor -- 4.5 The Multi-Bit Adder with Area Optimization -- 4.6 3-Variable K-Map and Code Converters -- 4.6.1 3-bit Binary to Gray Code Converter -- 4.6.2 3-Bit Gray to Binary Code Converter -- 4.7 Summary -- 5 Data Control Elements and Applications -- 5.1 Data and Control Paths in Design -- 5.2 Multiplexers to Control the Data -- 5.3 Lowest Order Mux in the Design -- 5.4 The 2:1 MUX Using NAND -- 5.5 The 4:1 MUX -- 5.6 The Design of 4:1 Mux Using 2:1 Mux.
5.7 Design Using Multiplexers -- 5.7.1 NOT Using 2:1 Mux -- 5.7.2 NAND Using Mux -- 5.7.3 NOR Using 2:1 Mux -- 5.7.4 Design of XOR Gate to Get the SUM Output Using Mux -- 5.7.5 Design of XNOR Gate to Get the Even Parity -- 5.8 Boolean Functions and Implementation Using Mux -- 5.9 Mux as Universal Logic -- 5.10 Summary -- 6 Decoders and Encoders -- 6.1 Demultiplexers and Use in the Design -- 6.2 Decoder 2 to 4 Having Active High Output -- 6.3 Decoder 2 to 4 Having Active Low Output -- 6.4 Design for the Given Specifications -- 6.5 Design of 3:8 Encoder Using 2:4 Decoders -- 6.6 Encoders and Their Applications -- 6.7 Practical Encoder Design -- 6.8 Priority Encoders -- 6.9 Practical Design Scenario -- 6.10 Summary -- 7 Combinational Design Scenarios -- 7.1 Mux-Based Designs and Optimization -- 7.2 Right and Left Shift Using Multiplexers -- 7.3 Design of 8:1 Mux Using 4:1 Mux -- 7.4 Design of 8:1 Mux Using 2:1 Mux -- 7.5 Boolean Expression from the Logic -- 7.6 Boolean Expression for Mux-Based Design -- 7.7 Stuck at Faults -- 7.8 Design Using Decoders -- 7.9 Design Using Decoder and NAND Gates -- 7.10 Summary -- 8 Synchronous Sequential Design -- 8.1 Sequential Design Elements -- 8.2 Synchronous Design -- 8.3 Why to Use Synchronous Design? -- 8.4 Asynchronous Design -- 8.4.1 D Flip-Flop and Use in the Design -- 8.5 Design of the Synchronous Counters -- 8.6 Design of the Synchronous Down-Counters -- 8.7 Design of the Synchronous Gray Counter -- 8.8 Few Important Guidelines -- 8.9 Summary -- 9 Logic Design Scenarios and Objectives -- 9.1 What is Asynchronous Design? -- 9.2 Synchronous Versus Asynchronous Reset -- 9.2.1 D Flip-Flop Having Asynchronous Reset -- 9.2.2 Synchronous Reset D Flip_flop -- 9.3 Asynchronous MOD Counters -- 9.3.1 Frequency Divider Network -- 9.3.2 Ripple Counter Design -- 9.4 Design Scenario -- 9.5 PIPO Register. 9.6 Shift Register -- 9.6.1 Shift Operation and Clock Cycles -- 9.7 Bidirectional Shift Register -- 9.8 Important Design Guidelines -- 9.9 Summary -- 10 Sequential Design Scenarios -- 10.1 Design Scenario I -- 10.2 Four-Bit Latch -- 10.3 Positive Edge Sensitive Flip-Flop Using Multiplexers -- 10.4 Flip-Flop Negative Edge Sensitive -- 10.5 Timing Sequence of Design -- 10.6 Load and Shift Register -- 10.7 Design Scenario II -- 10.8 Design Scenario III -- 10.9 Design Scenario III -- 10.10 Design Scenario IV -- 10.11 Design of 4-bit Ring Counter -- 10.12 Design of 4-bit Johnson Counter -- 10.13 Duty Cycle Control -- 10.13.1 Counter Design with 50% Duty Cycle -- 10.14 Summary -- 11 Timing Parameters and Maximum Frequency Calculations -- 11.1 What is Delay in the System? -- 11.1.1 Cascade Logic Elements in Design -- 11.1.2 Parallel Logic Elements in Design -- 11.2 How Delays Affect the Performance of the Design? -- 11.3 Sequential Circuit and Timing Parameters -- 11.4 Timing Paths in Design -- 11.4.1 Input to Register Path -- 11.4.2 Register to Output Path -- 11.4.3 Register to Register Path -- 11.4.4 Input to Output Path -- 11.5 Maximum Frequency Calculations -- 11.5.1 Design 1: Toggle Flip-Flop -- 11.5.2 Design II: The 2-bit Synchronous Up-Counter -- 11.6 Maximum Operating Frequency -- 11.6.1 Maximum Operating Frequency for Synchronous Designs -- 11.7 Clock Skew -- 11.7.1 Positive Clock Skew and Maximum Operating Frequency -- 11.7.2 Negative Clock Skew and Maximum Operating Frequency for the Design -- 11.8 VLSI Specific Scenarios -- 11.8.1 VLSI Specific Design Scenario I -- 11.8.2 VLSI Specific Design Scenario II -- 11.9 Hold Slack -- 11.9.1 VLSI Specific Design Scenario III -- 11.10 Summary -- 12 FSM Designs -- 12.1 Introduction to FSM -- 12.1.1 Moore FSM -- 12.1.2 Mealy FSM -- 12.1.3 Moore Versus Mealy FSM -- 12.2 State Encoding Methods. 12.3 Moore FSM Design -- 12.4 Mealy FSM Design -- 12.5 Applications and Design Strategies -- 12.6 State Diagrams -- 12.6.1 Moore Machine State Diagram -- 12.6.2 Mealy Machine State Diagram -- 12.7 Summary -- 13 Design of Sequence Detectors -- 13.1 Moore Machine Non-overlapping 101 Sequence Detector -- 13.2 Mealy Machine Non-overlapping 101 Sequence Detector -- 13.3 One-Hot Encoding -- 13.4 FSM Area and Power Optimization -- 13.5 Moore Sequence Detector for 101 Overlapping Sequence -- 13.6 Mealy Sequence Detector for 101 Overlapping Sequence -- 13.7 Mealy Sequence Detector for 1010 Overlapping Sequence -- 13.8 Various Paths in the Design -- 13.9 Data and Control Path Design Techniques -- 13.10 Summary -- 14 Performance Improvement for the Design -- 14.1 What Is Design Performance? -- 14.2 How to Use the Minimum Arithmetic Resources -- 14.3 Multibit Adders and Subtractors -- 14.4 Four-Bit Full Adder -- 14.4.1 4-Bit Full Subtractor -- 14.4.2 4-Bit Adder and Subtractor -- 14.4.3 Area Optimization of 4-Bit Adder and Subtractor -- 14.4.4 Optimization of Design Using Only Adders -- 14.4.5 Optimization by Tweaking the Logic to Have Least Area and Least Power -- 14.5 Optimization of the Design for Least Area and Power -- 14.6 Comparators and Parity Detectors with Lesser Area -- 14.6.1 Binary Comparator Design with Least Area -- 14.6.2 Parity Detector Design with Least Area -- 14.7 Processor Designs and Speed Improvement Techniques (Source: www.onerupeest.com) -- 14.8 Avoid Asynchronous Designs to Improve the Speed -- 14.9 Power Improvement -- 14.9.1 Gated Clocks and Dynamic Power Reduction -- 14.10 Summary -- 15 Optimization Techniques -- 15.1 Let Us Understand About the Area Optimization -- 15.2 Arithmetic Resource Sharing -- 15.3 Resource Sharing for Sequential Circuits -- 15.4 Logic Duplications -- 15.5 Design Scenario: Performance Improvement. 15.6 Use of Pipelining in Design -- 15.6.1 Design Without Pipelining -- 15.6.2 Speed Improvement Using Register Balancing or Pipelining -- 15.7 Power Improvement of Design -- 15.8 Dynamic Power Reduction -- 15.9 Summary -- 16 Case Study: Speed Improvement for the Design -- 16.1 Case Study: Speed Improvement at Logic-Level Case Study -- 16.2 Speed Improvement at Architecture Level (Source: www.onerupeest.com) -- 16.2.1 Top-Level Pin Interface -- 16.2.2 Pin Description -- 16.2.3 Case Study: Micro-architecture Design -- 16.3 Summary -- 17 Case Study: Multiple Clock Domains and FIFO Architecture Design -- 17.1 Single Clock Domain Designs -- 17.2 Multiple Clock Domain Designs -- 17.3 Metastability -- 17.4 Control Path Synchronizer -- 17.5 Data Path Synchronizers -- 17.5.1 Why We Need FIFO? -- 17.5.2 FIFO Depth Calculation -- 17.5.3 Case Study: FIFO as a Data Path Synchronizer -- 17.5.4 Micro-architecture of FIFO -- 17.6 Design Guidelines -- 17.7 Summary -- 18 Hardware Description for Design -- 18.1 Verilog HDL -- 18.2 Use of Continuous Assignments -- 18.3 The always Procedural Block -- 18.4 The Procedural Block always@* -- 18.5 Use of the case Construct -- 18.6 Continuous Versus Procedural Assignments -- 18.7 Multiple Blocking Assignments Within the always Block -- 18.8 Design Scenario I: Blocking Assignments -- 18.9 Non-blocking Assignments -- 18.10 Design Scenario II: Example Using Non-blocking Assignments -- 18.11 The 4-bit Register -- 18.12 Asynchronous Reset -- 18.13 Synchronous Reset -- 18.14 Design Guidelines and Summary -- 19 FPGA Architecture and Design Flow -- 19.1 Basics of Programmable Logic -- 19.2 CPLD Versus FPGA -- 19.3 ASIC Versus FPGA -- 19.4 FPGA Architecture -- 19.5 FPGA Design Flow -- 19.5.1 Design Planning -- 19.5.2 RTL Design -- 19.5.3 Design Verification and Synthesis -- 19.5.4 Design Implementation. 19.5.5 Device Programming and Testing. |
| Record Nr. | UNINA-9910627238803321 |
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Taraate Vaibbhav
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| Singapore : , : Springer, , [2023] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Digital system design : use of microcontroller / / Dawoud Shenouda Dawoud, R. Peplow, University of Kwa-Zulu, Natal
| Digital system design : use of microcontroller / / Dawoud Shenouda Dawoud, R. Peplow, University of Kwa-Zulu, Natal |
| Autore | Dawoud Shenouda Dawoud |
| Pubbl/distr/stampa | Aalborg, Denmark : , : River Publishers, , [2010] |
| Descrizione fisica | 1 online resource (570 p.) |
| Altri autori (Persone) | PeplowR |
| Collana | River Publishers series in signal, image & speech processing |
| Soggetto topico |
Microcontrollers
Digital integrated circuits Microprocessors |
| Soggetto genere / forma | Electronic books. |
| ISBN | 87-93102-29-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
""Cover""; ""Contents""; ""List of Abbreviations""; ""1 Processor Design Metrics""; ""1.1 Introduction""; ""1.2 Common Design Metrics""; ""1.3 Performance Design Metrics""; ""1.3.1 Characteristics of a Good Performance Metric""; ""1.3.2 Some Popular Performance Metrics""; ""1.3.3 Analysing Algorithms""; ""1.4 Economic Design Metrics""; ""1.4.1 Time-to-Market""; ""1.4.2 Design Economics""; ""1.5 Power Design Metrics""; ""1.5.1 Reducing Power Consumption""; ""1.6 System Effectiveness Metrics""; ""1.6.1 Reliability, Maintainability and Availability Metrics""; ""1.7 Summary of the Chapter""
""1.8 Review Questions""""2 A System Approach to Digital System Design""; ""2.1 Introduction""; ""2.2 System Design Flow""; ""2.2.1 Requirement Analysis""; ""2.2.2 Specifications""; ""2.2.3 Functional Design: System Architecture""; ""2.2.4 Hardware Overview""; ""2.2.5 Software Overview""; ""2.2.6 Target System and Solution""; ""2.3 Technologies Involved in the Design Process""; ""2.4 Design Technology""; ""2.4.1 Design Partitioning""; ""2.4.2 Use of Multiple Views (Multiple Description Domains): The Y-Chart"" ""2.4.3 Use of Structured Design: Functional Block-Structured Top-Down Design (Structural Hierarchy)""""2.4.4 Design Procedure Based on Top-Down Approach""; ""2.4.5 Programmable Digital Systems Design Using Block Structured Design""; ""2.5 IC-Technology; Implementation Technology""; ""2.5.1 Programmable Logic Device (PLD)""; ""2.6 Processor Technology""; ""2.6.1 Use of General-Purpose Processor (GPP)""; ""2.6.2 Single-Purpose Processor""; ""2.6.3 Application Specific Processor (e.g. Use of Microcontroller and DSP)""; ""2.6.4 Summary of IC Technology and Processor Technology"" ""2.7 Summary of the Chapter""""2.8 Review Questions""; ""3 Introduction to Microprocessors and Microcontrollers""; ""3.1 Introduction""; ""3.1.1 Processor Architecture and Microarchitecture""; ""3.2 The Microprocessor""; ""3.2.1 General-Purpose Registers""; ""3.2.2 Arithmetic and Logic Unit (ALU)""; ""3.2.3 Control Unit""; ""3.2.4 I/O Control Section (Bus Interface Unit)""; ""3.2.5 Internal Buses""; ""3.2.6 System Clocks""; ""3.2.7 Basic Microprocessor Organization""; ""3.3 Microcontrollers""; ""3.3.1 Microcontroller Internal Structure"" ""3.4 Microprocessor-Based and Microcontroller-Based Systems""""3.4.1 Microprocessor-based and Microcontroller-based Digital Systems Design Using Top-Down Technique""; ""3.5 Practical Microcontrollers""; ""3.5.1 AVR ATmega8515 Microcontroller""; ""3.5.2 Intel 8051 Microcontroller""; ""3.6 Summary of the Chapter""; ""3.7 Review Questions""; ""4 Instructions And Instruction Set""; ""4.1 Introduction""; ""4.2 Instruction Format""; ""4.2.1 Expressing Numbers""; ""4.2.2 Basic Instruction Cycle; Execution Path of an Instruction""; ""4.2.3 Clock Cycle and Instruction Cycle""; ""4.2.4 Labels"" ""4.3 Describing the Instruction Cycle: Use of Register Transfer Language (RTL)"" |
| Record Nr. | UNINA-9910464195003321 |
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Dawoud Shenouda Dawoud
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| Aalborg, Denmark : , : River Publishers, , [2010] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Digital system design : use of microcontroller / / Dawoud Shenouda Dawoud, R. Peplow, University of Kwa-Zulu, Natal
| Digital system design : use of microcontroller / / Dawoud Shenouda Dawoud, R. Peplow, University of Kwa-Zulu, Natal |
| Autore | Dawoud Shenouda Dawoud |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Taylor & Francis, 2010 |
| Descrizione fisica | 1 online resource (570 p.) |
| Altri autori (Persone) | PeplowR |
| Collana | River Publishers series in signal, image & speech processing |
| Soggetto topico |
Microcontrollers
Digital integrated circuits Microprocessors |
| Soggetto non controllato |
Energy
Communications engineering / telecommunications |
| ISBN |
1-00-333794-5
1-003-33794-5 87-93102-29-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
""Cover""; ""Contents""; ""List of Abbreviations""; ""1 Processor Design Metrics""; ""1.1 Introduction""; ""1.2 Common Design Metrics""; ""1.3 Performance Design Metrics""; ""1.3.1 Characteristics of a Good Performance Metric""; ""1.3.2 Some Popular Performance Metrics""; ""1.3.3 Analysing Algorithms""; ""1.4 Economic Design Metrics""; ""1.4.1 Time-to-Market""; ""1.4.2 Design Economics""; ""1.5 Power Design Metrics""; ""1.5.1 Reducing Power Consumption""; ""1.6 System Effectiveness Metrics""; ""1.6.1 Reliability, Maintainability and Availability Metrics""; ""1.7 Summary of the Chapter""
""1.8 Review Questions""""2 A System Approach to Digital System Design""; ""2.1 Introduction""; ""2.2 System Design Flow""; ""2.2.1 Requirement Analysis""; ""2.2.2 Specifications""; ""2.2.3 Functional Design: System Architecture""; ""2.2.4 Hardware Overview""; ""2.2.5 Software Overview""; ""2.2.6 Target System and Solution""; ""2.3 Technologies Involved in the Design Process""; ""2.4 Design Technology""; ""2.4.1 Design Partitioning""; ""2.4.2 Use of Multiple Views (Multiple Description Domains): The Y-Chart"" ""2.4.3 Use of Structured Design: Functional Block-Structured Top-Down Design (Structural Hierarchy)""""2.4.4 Design Procedure Based on Top-Down Approach""; ""2.4.5 Programmable Digital Systems Design Using Block Structured Design""; ""2.5 IC-Technology; Implementation Technology""; ""2.5.1 Programmable Logic Device (PLD)""; ""2.6 Processor Technology""; ""2.6.1 Use of General-Purpose Processor (GPP)""; ""2.6.2 Single-Purpose Processor""; ""2.6.3 Application Specific Processor (e.g. Use of Microcontroller and DSP)""; ""2.6.4 Summary of IC Technology and Processor Technology"" ""2.7 Summary of the Chapter""""2.8 Review Questions""; ""3 Introduction to Microprocessors and Microcontrollers""; ""3.1 Introduction""; ""3.1.1 Processor Architecture and Microarchitecture""; ""3.2 The Microprocessor""; ""3.2.1 General-Purpose Registers""; ""3.2.2 Arithmetic and Logic Unit (ALU)""; ""3.2.3 Control Unit""; ""3.2.4 I/O Control Section (Bus Interface Unit)""; ""3.2.5 Internal Buses""; ""3.2.6 System Clocks""; ""3.2.7 Basic Microprocessor Organization""; ""3.3 Microcontrollers""; ""3.3.1 Microcontroller Internal Structure"" ""3.4 Microprocessor-Based and Microcontroller-Based Systems""""3.4.1 Microprocessor-based and Microcontroller-based Digital Systems Design Using Top-Down Technique""; ""3.5 Practical Microcontrollers""; ""3.5.1 AVR ATmega8515 Microcontroller""; ""3.5.2 Intel 8051 Microcontroller""; ""3.6 Summary of the Chapter""; ""3.7 Review Questions""; ""4 Instructions And Instruction Set""; ""4.1 Introduction""; ""4.2 Instruction Format""; ""4.2.1 Expressing Numbers""; ""4.2.2 Basic Instruction Cycle; Execution Path of an Instruction""; ""4.2.3 Clock Cycle and Instruction Cycle""; ""4.2.4 Labels"" ""4.3 Describing the Instruction Cycle: Use of Register Transfer Language (RTL)"" |
| Record Nr. | UNINA-9910535304403321 |
|
Dawoud Shenouda Dawoud
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| Taylor & Francis, 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Electromagnetics for high-speed analog and digital communication circuits / / Ali M. Niknejad [[electronic resource]]
| Electromagnetics for high-speed analog and digital communication circuits / / Ali M. Niknejad [[electronic resource]] |
| Autore | Niknejad Ali M. <1972-> |
| Pubbl/distr/stampa | Cambridge : , : Cambridge University Press, , 2007 |
| Descrizione fisica | 1 online resource (xi, 452 pages) : digital, PDF file(s) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Electromagnetic compatibility Digital integrated circuits Linear integrated circuits Electromagnetism |
| ISBN |
1-107-16562-8
1-280-75044-8 9786610750443 0-511-26953-6 0-511-27009-7 0-511-26861-0 0-511-32075-2 1-60119-741-1 0-511-80573-X 0-511-26928-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Cover; Half-title; Title; Copyright; Contents; Preface; Acknowledgments; 1 Introduction; 2 Capacitance; 3 Resistance; 4 Ampère, Faraday, and Maxwell; 5 Inductance; 6 Passive device design and layout; 7 Resonance and impedance matching; 8 Small-signal high-speed amplifiers; 9 Transmission lines; 10 Transformers; 11 Distributed circuits; 12 High-speed switching circuits; 13 Magnetic and electrical coupling and isolation; 14 Electromagnetic propagation and radiation; 15 Microwave circuits; References; Index |
| Altri titoli varianti | Electromagnetics for High-Speed Analog & Digital Communication Circuits |
| Record Nr. | UNINA-9910457758503321 |
|
Niknejad Ali M. <1972->
|
||
| Cambridge : , : Cambridge University Press, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electromagnetics for high-speed analog and digital communication circuits / / Ali M. Niknejad [[electronic resource]]
| Electromagnetics for high-speed analog and digital communication circuits / / Ali M. Niknejad [[electronic resource]] |
| Autore | Niknejad Ali M. <1972-> |
| Pubbl/distr/stampa | Cambridge : , : Cambridge University Press, , 2007 |
| Descrizione fisica | 1 online resource (xi, 452 pages) : digital, PDF file(s) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Electromagnetic compatibility Digital integrated circuits Linear integrated circuits Electromagnetism |
| ISBN |
1-107-16562-8
1-280-75044-8 9786610750443 0-511-26953-6 0-511-27009-7 0-511-26861-0 0-511-32075-2 1-60119-741-1 0-511-80573-X 0-511-26928-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Cover; Half-title; Title; Copyright; Contents; Preface; Acknowledgments; 1 Introduction; 2 Capacitance; 3 Resistance; 4 Ampère, Faraday, and Maxwell; 5 Inductance; 6 Passive device design and layout; 7 Resonance and impedance matching; 8 Small-signal high-speed amplifiers; 9 Transmission lines; 10 Transformers; 11 Distributed circuits; 12 High-speed switching circuits; 13 Magnetic and electrical coupling and isolation; 14 Electromagnetic propagation and radiation; 15 Microwave circuits; References; Index |
| Altri titoli varianti | Electromagnetics for High-Speed Analog & Digital Communication Circuits |
| Record Nr. | UNINA-9910784343703321 |
|
Niknejad Ali M. <1972->
|
||
| Cambridge : , : Cambridge University Press, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electromagnetics for high-speed analog and digital communication circuits / / Ali M. Niknejad [[electronic resource]]
| Electromagnetics for high-speed analog and digital communication circuits / / Ali M. Niknejad [[electronic resource]] |
| Autore | Niknejad Ali M. <1972-> |
| Pubbl/distr/stampa | Cambridge : , : Cambridge University Press, , 2007 |
| Descrizione fisica | 1 online resource (xi, 452 pages) : digital, PDF file(s) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Electromagnetic compatibility Digital integrated circuits Linear integrated circuits Electromagnetism |
| ISBN |
1-107-16562-8
1-280-75044-8 9786610750443 0-511-26953-6 0-511-27009-7 0-511-26861-0 0-511-32075-2 1-60119-741-1 0-511-80573-X 0-511-26928-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Cover; Half-title; Title; Copyright; Contents; Preface; Acknowledgments; 1 Introduction; 2 Capacitance; 3 Resistance; 4 Ampère, Faraday, and Maxwell; 5 Inductance; 6 Passive device design and layout; 7 Resonance and impedance matching; 8 Small-signal high-speed amplifiers; 9 Transmission lines; 10 Transformers; 11 Distributed circuits; 12 High-speed switching circuits; 13 Magnetic and electrical coupling and isolation; 14 Electromagnetic propagation and radiation; 15 Microwave circuits; References; Index |
| Altri titoli varianti | Electromagnetics for High-Speed Analog & Digital Communication Circuits |
| Record Nr. | UNINA-9910810212003321 |
|
Niknejad Ali M. <1972->
|
||
| Cambridge : , : Cambridge University Press, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
