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Design and test of digital circuits by quantum-dot cellular automata / / Fabrizio Lombardi, Jing Huang, editors
| Design and test of digital circuits by quantum-dot cellular automata / / Fabrizio Lombardi, Jing Huang, editors |
| Pubbl/distr/stampa | Boston ; , : Northeastern University, , ©2008 |
| Descrizione fisica | 1 online resource (380 p.) |
| Disciplina | 621.395 |
| Altri autori (Persone) |
LombardiFabrizio <1955->
HuangJing <1970-> |
| Soggetto topico |
Cellular automata
Digital electronics - Design and construction Digital electronics - Testing Nanoelectronics Quantum computers Quantum dots |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-5231-1706-0
1-59693-268-6 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Design and Test of Digital Circuits byQuantum-Dot Cellular Automata; Contents; Preface; Chapter 1 Introduction 1; Chapter 2 Nano Devices and Architectures Overview 11; Chapter 3 QCA 37; Chapter 4 QCA Combinational Logic Design 69; Chapter 5 Logic-Level Testing and Defect Characterization 91; Chapter 6 Two-Dimensional Schemes for Clocking/Timing of QCA Circuits 143; Chapter 7 Tile-Based QCA Design 171; Chapter 8 Sequential Circuit Design in QCA 213; Chapter 9 QCA Memory 247; Chapter 10 Implementing Universal Logic in QCA 287; Chapter 11 QCA Model for Computing and Energy Analysis 305
Chapter 12 Fault Tolerance of Reversible QCA Circuits 327Chapter 13 Conclusion and Future Work 349; Appendix A Preliminary for QCA Mechanical Model 353; Appendix B Validation of Mechanical Model 357; Appendix C Energy Dissipation Analysis of Circuit Units 363; About the Authors 367 |
| Record Nr. | UNINA-9910454116803321 |
| Boston ; , : Northeastern University, , ©2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Design and test of digital circuits by quantum-dot cellular automata / / Fabrizio Lombardi, Jing Huang, editors
| Design and test of digital circuits by quantum-dot cellular automata / / Fabrizio Lombardi, Jing Huang, editors |
| Pubbl/distr/stampa | Boston ; , : Northeastern University, , ©2008 |
| Descrizione fisica | 1 online resource (380 p.) |
| Disciplina | 621.395 |
| Altri autori (Persone) |
LombardiFabrizio <1955->
HuangJing <1970-> |
| Soggetto topico |
Cellular automata
Digital electronics - Design and construction Digital electronics - Testing Nanoelectronics Quantum computers Quantum dots |
| ISBN |
1-5231-1706-0
1-59693-268-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Design and Test of Digital Circuits byQuantum-Dot Cellular Automata; Contents; Preface; Chapter 1 Introduction 1; Chapter 2 Nano Devices and Architectures Overview 11; Chapter 3 QCA 37; Chapter 4 QCA Combinational Logic Design 69; Chapter 5 Logic-Level Testing and Defect Characterization 91; Chapter 6 Two-Dimensional Schemes for Clocking/Timing of QCA Circuits 143; Chapter 7 Tile-Based QCA Design 171; Chapter 8 Sequential Circuit Design in QCA 213; Chapter 9 QCA Memory 247; Chapter 10 Implementing Universal Logic in QCA 287; Chapter 11 QCA Model for Computing and Energy Analysis 305
Chapter 12 Fault Tolerance of Reversible QCA Circuits 327Chapter 13 Conclusion and Future Work 349; Appendix A Preliminary for QCA Mechanical Model 353; Appendix B Validation of Mechanical Model 357; Appendix C Energy Dissipation Analysis of Circuit Units 363; About the Authors 367 |
| Record Nr. | UNINA-9910782562303321 |
| Boston ; , : Northeastern University, , ©2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Design and test of digital circuits by quantum-dot cellular automata / / Fabrizio Lombardi, Jing Huang, editors
| Design and test of digital circuits by quantum-dot cellular automata / / Fabrizio Lombardi, Jing Huang, editors |
| Pubbl/distr/stampa | Boston ; , : Northeastern University, , ©2008 |
| Descrizione fisica | 1 online resource (380 p.) |
| Disciplina | 621.395 |
| Altri autori (Persone) |
LombardiFabrizio <1955->
HuangJing <1970-> |
| Soggetto topico |
Cellular automata
Digital electronics - Design and construction Digital electronics - Testing Nanoelectronics Quantum computers Quantum dots |
| ISBN |
1-5231-1706-0
1-59693-268-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Design and Test of Digital Circuits byQuantum-Dot Cellular Automata; Contents; Preface; Chapter 1 Introduction 1; Chapter 2 Nano Devices and Architectures Overview 11; Chapter 3 QCA 37; Chapter 4 QCA Combinational Logic Design 69; Chapter 5 Logic-Level Testing and Defect Characterization 91; Chapter 6 Two-Dimensional Schemes for Clocking/Timing of QCA Circuits 143; Chapter 7 Tile-Based QCA Design 171; Chapter 8 Sequential Circuit Design in QCA 213; Chapter 9 QCA Memory 247; Chapter 10 Implementing Universal Logic in QCA 287; Chapter 11 QCA Model for Computing and Energy Analysis 305
Chapter 12 Fault Tolerance of Reversible QCA Circuits 327Chapter 13 Conclusion and Future Work 349; Appendix A Preliminary for QCA Mechanical Model 353; Appendix B Validation of Mechanical Model 357; Appendix C Energy Dissipation Analysis of Circuit Units 363; About the Authors 367 |
| Record Nr. | UNINA-9910813998303321 |
| Boston ; , : Northeastern University, , ©2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital logic testing and simulation [[electronic resource] /] / Alexander Miczo
| Digital logic testing and simulation [[electronic resource] /] / Alexander Miczo |
| Autore | Miczo Alexander |
| Edizione | [2nd ed.] |
| Pubbl/distr/stampa | Hoboken, NJ, : Wiley-Interscience, c2003 |
| Descrizione fisica | 1 online resource (697 p.) |
| Disciplina |
621.3815/48
621.381548 |
| Soggetto topico | Digital electronics - Testing |
| ISBN |
1-280-36610-9
9786610366101 0-470-35712-6 0-471-45777-9 0-471-45778-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
DIGITAL LOGIC TESTING AND SIMULATION; CONTENTS; Preface; 1 Introduction; 1.1 Introduction; 1.2 Quality; 1.3 The Test; 1.4 The Design Process; 1.5 Design Automation; 1.6 Estimating Yield; 1.7 Measuring Test Effectiveness; 1.8 The Economics of Test; 1.9 Case Studies; 1.9.1 The Effectiveness of Fault Simulation; 1.9.2 Evaluating Test Decisions; 1.10 Summary; Problems; References; 2 Simulation; 2.1 Introduction; 2.2 Background; 2.3 The Simulation Hierarchy; 2.4 The Logic Symbols; 2.5 Sequential Circuit Behavior; 2.6 The Compiled Simulator; 2.6.1 Ternary Simulation
2.6.2 Sequential Circuit Simulation2.6.3 Timing Considerations; 2.6.4 Hazards; 2.6.5 Hazard Detection; 2.7 Event-Driven Simulation; 2.7.1 Zero-Delay Simulation; 2.7.2 Unit-Delay Simulation; 2.7.3 Nominal-Delay Simulation; 2.8 Multiple-Valued Simulation; 2.9 Implementing the Nominal-Delay Simulator; 2.9.1 The Scheduler; 2.9.2 The Descriptor Cell; 2.9.3 Evaluation Techniques; 2.9.4 Race Detection in Nominal-Delay Simulation; 2.9.5 Min-Max Timing; 2.10 Switch-Level Simulation; 2.11 Binary Decision Diagrams; 2.11.1 Introduction; 2.11.2 The Reduce Operation; 2.11.3 The Apply Operation 2.12 Cycle Simulation2.13 Timing Verification; 2.13.1 Path Enumeration; 2.13.2 Block-Oriented Analysis; 2.14 Summary; Problems; References; 3 Fault Simulation; 3.1 Introduction; 3.2 Approaches to Testing; 3.3 Analysis of a Faulted Circuit; 3.3.1 Analysis at the Component Level; 3.3.2 Gate-Level Symbols; 3.3.3 Analysis at the Gate Level; 3.4 The Stuck-At Fault Model; 3.4.1 The AND Gate Fault Model; 3.4.2 The OR Gate Fault Model; 3.4.3 The Inverter Fault Model; 3.4.4 The Tri-State Fault Model; 3.4.5 Fault Equivalence and Dominance; 3.5 The Fault Simulator: An Overview 3.6 Parallel Fault Processing3.6.1 Parallel Fault Simulation; 3.6.2 Performance Enhancements; 3.6.3 Parallel Pattern Single Fault Propagation; 3.7 Concurrent Fault Simulation; 3.7.1 An Example of Concurrent Simulation; 3.7.2 The Concurrent Fault Simulation Algorithm; 3.7.3 Concurrent Fault Simulation: Further Considerations; 3.8 Delay Fault Simulation; 3.9 Differential Fault Simulation; 3.10 Deductive Fault Simulation; 3.11 Statistical Fault Analysis; 3.12 Fault Simulation Performance; 3.13 Summary; Problems; References; 4 Automatic Test Pattern Generation; 4.1 Introduction 4.2 The Sensitized Path4.2.1 The Sensitized Path: An Example; 4.2.2 Analysis of the Sensitized Path Method; 4.3 The D-Algorithm; 4.3.1 The D-Algorithm: An Analysis; 4.3.2 The Primitive D-Cubes of Failure; 4.3.3 Propagation D-Cubes; 4.3.4 Justification and Implication; 4.3.5 The D-Intersection; 4.4 Testdetect; 4.5 The Subscripted D-Algorithm; 4.6 PODEM; 4.7 FAN; 4.8 Socrates; 4.9 The Critical Path; 4.10 Critical Path Tracing; 4.11 Boolean Differences; 4.12 Boolean Satisfiability; 4.13 Using BDDs for ATPG; 4.13.1 The BDD XOR Operation; 4.13.2 Faulting the BDD Graph; 4.14 Summary; Problems References |
| Record Nr. | UNINA-9910143518603321 |
Miczo Alexander
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| Hoboken, NJ, : Wiley-Interscience, c2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
