Autore	Kleitz William
Edizione	[First edition, Pearson new international edition.]
Pubbl/distr/stampa	Harlow, England : , : Pearson, , [2014]
Descrizione fisica	1 online resource (932 pages) : illustrations
Disciplina	621.381
Collana	Always learning
Soggetto topico	Digital electronics - Data processing
ISBN	1-292-05390-9
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Cover -- Table of Contents -- 1. Number Systems and Codes -- 2. Digital Electronic Signals and Switches -- 3. Basic Logic Gates -- 4. Programmable Logic Devices: CPLDs and FPGAs with VHDL Design -- 5. Boolean Algebra and Reduction Techniques -- 6. Exclusive-OR and Exclusive-NOR Gates -- 7. Arithmetic Operations and Circuits -- 8. Code Converters, Multiplexers, and Demultiplexers -- 9. Logic Families and Their Characteristics -- 10. Flip-Flops and Registers -- 11. Practical Considerations for Digital Design -- 12. Counter Circuits and VHDL State Machines -- 13. Shift Registers -- 14. Multivibrators and the 555 Timer -- 15. Interfacing to the Analog World -- 16. Semiconductor, Magnetic, and Optical Memory -- 17. Microprocessor Fundamentals -- Appendix: WWW Sites -- Appendix: Manufacturers' Data Sheets -- Appendix: Explanation of the IEEE/IEC Standard for Logic Symbols (Dependency Notation) -- Appendix: VHDL Language Reference -- Appendix: Review of Basic Electricity Principles -- Appendix: Schematic Diagrams for Chapter-End Problems -- Index.
Record Nr.	UNINA-9910153068703321

Autore	Zwoliński Mark
Edizione	[Second edition.]
Pubbl/distr/stampa	Harlow, England : , : Prentice Hall, , 2004
Descrizione fisica	1 online resource (385 pages) : illustrations
Disciplina	621.381
Soggetto topico	Digital electronics - Data processing
ISBN	1-4058-9097-5
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Cover -- Digital System Design with VHDL -- Contents -- Preface -- Introduction -- Modern digital design -- CMOS technology -- Programmable logic -- Electrical properties -- Summary -- Further reading -- Exercises -- Combinational logic design -- Boolean algebra -- Logic gates -- Combinational logic design -- Timing -- Number codes -- Summary -- Further reading -- Exercises -- Combinational logic using VHDL gate models -- Entities and architectures -- Identifiers, spaces and comments -- Netlists -- Signal assignments -- Generics -- Constant and open ports -- Testbenches -- Configurations -- Summary -- Further reading -- Exercises -- Combinational building blocks -- Three-state buffers -- Decoders -- Multiplexers -- Priority encoder -- Adders -- Parity checker -- Testbenches for combinational blocks -- Summary -- Further reading -- Exercises -- Synchronous sequential design -- Synchronous sequential systems -- Models of synchronous sequential systems -- Algorithmic state machines -- Synthesis from ASM charts -- State machines in VHDL -- VHDL testbenches for state machines -- Summary -- Further reading -- Exercises -- VHDL models of sequential logic blocks -- Latches -- Flip-flops -- JK and T flip-flops -- Registers and shift registers -- Counters -- Memory -- Sequential multiplier -- Testbenches for sequential building blocks -- Summary -- Further reading -- Exercises -- Complex sequential systems -- Linked state machines -- Datapath/controller partitioning -- Instructions -- A simple microprocessor -- VHDL model of a simple microprocessor -- Summary -- Further reading -- Exercises -- VHDL simulation -- Event-driven simulation -- Simulation of VHDL models -- Simulation modelling issues -- File operations -- Summary -- Further reading -- Exercises -- VHDL synthesis -- RTL synthesis -- Constraints -- Synthesis for FPGAs -- Behavioural synthesis. Verifying synthesis results -- Summary -- Further reading -- Exercises -- Testing digital systems -- The need for testing -- Fault models -- Fault-oriented test pattern generation -- Fault simulation -- Fault simulation in VHDL -- Summary -- Further reading -- Exercises -- Design for testability -- Ad hoc testability improvements -- Structured design for test -- Built-in self-test -- Boundary scan (IEEE 1149.1) -- Summary -- Further reading -- Exercises -- Asynchronous sequential design -- Asynchronous circuits -- Analysis of asynchronous circuits -- Design of asynchronous sequential circuits -- Asynchronous state machines -- Setup and hold times and metastability -- Summary -- Further reading -- Exercises -- Interfacing with the analogue world -- Digital to analogue converters -- Analogue to digital converters -- VHDL-AMS -- Phased-locked loops -- VHDL-AMS simulators -- Summary -- Further reading -- Exercises -- Appendix A VHDL standards -- Appendix B Verilog -- Appendix C Shared variable packages -- Bibliography -- Answers to selected exercises -- Index.
Record Nr.	UNINA-9910154652703321

Autore	Chu Pong P. <1959->
Pubbl/distr/stampa	Hoboken, New Jersey : , : Wiley-Interscience, , c2006
Descrizione fisica	1 online resource (695 p.)
Disciplina	621.39/2 621.392
Soggetto topico	Digital electronics - Data processing VHDL (Computer hardware description language)
ISBN	1-280-44810-5 9786610448104 0-470-32489-9 0-471-78641-1 0-471-78639-X
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Introduction to digital system design -- Overview of hardware description languages -- Basic language constructs of VHDL -- Concurrent signal assignment statements of VHDL -- Sequential statements of VHDL -- Synthesis of VHDL code -- Combinational circuit design : practice -- Sequential circuit design : principle -- Sequential circuit design : practice -- Finite state machine : principle and practice -- Register transfer methodology : principle -- Register transfer methodology : practice -- Hierarchical design in VHDL -- Parameterized design : principle -- Parameterized design : practice -- Clock and synchronization : principle and practice.
Record Nr.	UNINA-9910143580903321