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Formal methods in computer-aided design : third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings / / edited by Warren A. Hunt. Steven D. Johnson
| Formal methods in computer-aided design : third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings / / edited by Warren A. Hunt. Steven D. Johnson |
| Edizione | [1st ed. 2000.] |
| Pubbl/distr/stampa | Berlin, Germany ; ; New York, New York : , : Springer, , [2000] |
| Descrizione fisica | 1 online resource (XII, 552 p.) |
| Disciplina | 621.392 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computer engineering - Computer-aided design
Integrated circuits - Verification |
| ISBN | 3-540-40922-X |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Applications of Hierarchical Verification in Model Checking -- Applications of Hierarchical Verification in Model Checking -- Invited Talk -- Trends in Computing -- Invited Paper -- A Case Study in Formal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon TM Processor -- Contributed Papers -- An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps -- Automated Refinement Checking for Asynchronous Processes -- Border-Block Triangular Form and Conjunction Schedule in Image Computation -- B2M: A Semantic Based Tool for BLIF Hardware Descriptions -- Checking Safety Properties Using Induction and a SAT-Solver -- Combining Stream-Based and State-Based Verification Techniques -- A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles -- Correctness of Pipelined Machines -- Do You Trust Your Model Checker? -- Executable Protocol Specification in ESL -- Formal Verification of Floating Point Trigonometric Functions -- Hardware Modeling Using Function Encapsulation -- A Methodology for the Formal Analysis of Asynchronous Micropipelines -- A Methodology for Large-Scale Hardware Verification -- Model Checking Synchronous Timing Diagrams -- Model Reductions and a Case Study -- Modeling and Parameters Synthesis for an Air TrafficManagement System -- Monitor-Based Formal Specification of PCI -- SAT-Based Image Computation with Application in Reachability Analysis -- SAT-Based Verification without State Space Traversal -- Scalable Distributed On-the-Fly Symbolic Model Checking -- The Semantics of Verilog Using Transition System Combinators -- Sequential Equivalence Checking by Symbolic Simulation -- Speeding Up Image Computation by Using RTL Information -- Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs -- Symbolic Simulation with Approximate Values -- A Theory of Consistency for Modular Synchronous Systems -- Verifying Transaction Ordering Properties in Unbounded Bus Networks through Combined Deductive/Algorithmic Methods -- Visualizing System Factorizations with Behavior Tables. |
| Record Nr. | UNINA-9910143609903321 |
| Berlin, Germany ; ; New York, New York : , : Springer, , [2000] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Formal methods in computer-aided design : third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings / / edited by Warren A. Hunt. Steven D. Johnson
| Formal methods in computer-aided design : third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings / / edited by Warren A. Hunt. Steven D. Johnson |
| Edizione | [1st ed. 2000.] |
| Pubbl/distr/stampa | Berlin, Germany ; ; New York, New York : , : Springer, , [2000] |
| Descrizione fisica | 1 online resource (XII, 552 p.) |
| Disciplina | 621.392 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computer engineering - Computer-aided design
Integrated circuits - Verification |
| ISBN | 3-540-40922-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Applications of Hierarchical Verification in Model Checking -- Applications of Hierarchical Verification in Model Checking -- Invited Talk -- Trends in Computing -- Invited Paper -- A Case Study in Formal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon TM Processor -- Contributed Papers -- An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps -- Automated Refinement Checking for Asynchronous Processes -- Border-Block Triangular Form and Conjunction Schedule in Image Computation -- B2M: A Semantic Based Tool for BLIF Hardware Descriptions -- Checking Safety Properties Using Induction and a SAT-Solver -- Combining Stream-Based and State-Based Verification Techniques -- A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles -- Correctness of Pipelined Machines -- Do You Trust Your Model Checker? -- Executable Protocol Specification in ESL -- Formal Verification of Floating Point Trigonometric Functions -- Hardware Modeling Using Function Encapsulation -- A Methodology for the Formal Analysis of Asynchronous Micropipelines -- A Methodology for Large-Scale Hardware Verification -- Model Checking Synchronous Timing Diagrams -- Model Reductions and a Case Study -- Modeling and Parameters Synthesis for an Air TrafficManagement System -- Monitor-Based Formal Specification of PCI -- SAT-Based Image Computation with Application in Reachability Analysis -- SAT-Based Verification without State Space Traversal -- Scalable Distributed On-the-Fly Symbolic Model Checking -- The Semantics of Verilog Using Transition System Combinators -- Sequential Equivalence Checking by Symbolic Simulation -- Speeding Up Image Computation by Using RTL Information -- Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs -- Symbolic Simulation with Approximate Values -- A Theory of Consistency for Modular Synchronous Systems -- Verifying Transaction Ordering Properties in Unbounded Bus Networks through Combined Deductive/Algorithmic Methods -- Visualizing System Factorizations with Behavior Tables. |
| Record Nr. | UNISA-996466181903316 |
| Berlin, Germany ; ; New York, New York : , : Springer, , [2000] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Formal methods in computer-aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings / / Ganesh Gopalakrishnan, Phillip Windley (editors)
| Formal methods in computer-aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings / / Ganesh Gopalakrishnan, Phillip Windley (editors) |
| Edizione | [1st ed. 1998.] |
| Pubbl/distr/stampa | Berlin : , : Springer, , [1998] |
| Descrizione fisica | 1 online resource (X, 538 p.) |
| Disciplina | 621.392 |
| Collana | Lecture notes in computer science |
| Soggetto topico |
Digital integrated circuits - Computer-aided design
Computer engineering - Computer-aided design Integrated circuits - Verification Automatic theorem proving Formal methods (Computer science) |
| ISBN | 3-540-49519-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification -- Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution -- Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking -- Solving Bit-Vector Equations -- The Formal Design of 1M-Gate ASICs -- Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations -- A Tutorial on Stålmarck’s Proof Procedure for Propositional Logic -- Almana: A BDD Minimization Tool Integrating Heuristic and RewritingMethods -- Bisimulation Minimization in an Automata-Theoretic Verification Framework -- Automatic Verification of Mixed-Level Logic Circuits -- A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk -- Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints -- Using MTBDDs for Composition and Model Checking of Real-Time Systems -- Formal Methods in CAD from an Industrial Perspective -- A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool -- Combined Formal Post- and Presynthesis Verification in High Level Synthesis -- Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem -- A Performance Study of BDD-Based Model Checking -- Symbolic Model Checking Visualization -- Input Elimination and Abstraction in Model Checking -- Symbolic Simulation of the JEM1 Microprocessor -- Symbolic Simulation: An ACL2 Approach -- Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study -- Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification -- Formally Verifying Data and Control with Weak Reachability Invariants -- Generalized Reversible Rules -- An Assume-Guarantee Rule for Checking Simulation -- Three Approaches to Hardware Verification: HOL, MDG, and VIS Compared -- An Instruction Set Process Calculus -- Techniques for Implicit State Enumeration of EFSMs -- Model Checking on Product Structures -- BDDNOW: A Parallel BDD Package -- Model Checking VHDL with CV -- Alexandria: A Tool for Hierarchical Verification -- PV: An Explicit Enumeration Model-Checker. |
| Record Nr. | UNINA-9910143467903321 |
| Berlin : , : Springer, , [1998] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Formal methods in computer-aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings / / Ganesh Gopalakrishnan, Phillip Windley (editors)
| Formal methods in computer-aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings / / Ganesh Gopalakrishnan, Phillip Windley (editors) |
| Edizione | [1st ed. 1998.] |
| Pubbl/distr/stampa | Berlin : , : Springer, , [1998] |
| Descrizione fisica | 1 online resource (X, 538 p.) |
| Disciplina | 621.392 |
| Collana | Lecture notes in computer science |
| Soggetto topico |
Digital integrated circuits - Computer-aided design
Computer engineering - Computer-aided design Integrated circuits - Verification Automatic theorem proving Formal methods (Computer science) |
| ISBN | 3-540-49519-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification -- Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution -- Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking -- Solving Bit-Vector Equations -- The Formal Design of 1M-Gate ASICs -- Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations -- A Tutorial on Stålmarck’s Proof Procedure for Propositional Logic -- Almana: A BDD Minimization Tool Integrating Heuristic and RewritingMethods -- Bisimulation Minimization in an Automata-Theoretic Verification Framework -- Automatic Verification of Mixed-Level Logic Circuits -- A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk -- Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints -- Using MTBDDs for Composition and Model Checking of Real-Time Systems -- Formal Methods in CAD from an Industrial Perspective -- A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool -- Combined Formal Post- and Presynthesis Verification in High Level Synthesis -- Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem -- A Performance Study of BDD-Based Model Checking -- Symbolic Model Checking Visualization -- Input Elimination and Abstraction in Model Checking -- Symbolic Simulation of the JEM1 Microprocessor -- Symbolic Simulation: An ACL2 Approach -- Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study -- Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification -- Formally Verifying Data and Control with Weak Reachability Invariants -- Generalized Reversible Rules -- An Assume-Guarantee Rule for Checking Simulation -- Three Approaches to Hardware Verification: HOL, MDG, and VIS Compared -- An Instruction Set Process Calculus -- Techniques for Implicit State Enumeration of EFSMs -- Model Checking on Product Structures -- BDDNOW: A Parallel BDD Package -- Model Checking VHDL with CV -- Alexandria: A Tool for Hierarchical Verification -- PV: An Explicit Enumeration Model-Checker. |
| Record Nr. | UNISA-996465910703316 |
| Berlin : , : Springer, , [1998] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
