Edizione	[1st ed. 2007.]
Pubbl/distr/stampa	Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007
Descrizione fisica	1 online resource (XIII, 402 p.)
Disciplina	004
Collana	Theoretical Computer Science and General Issues
Soggetto topico	Computer systems Computer arithmetic and logic units Computer input-output equipment Logic design Computer networks Microprocessors Computer architecture Computer System Implementation Arithmetic and Logic Structures Input/Output and Data Communications Logic Design Computer Communication Networks Processor Architectures
ISBN	1-281-04270-6 9786611042707 3-540-74309-X
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	A Compiler Framework for Supporting Speculative Multicore Processors -- Power-Efficient Heterogeneous Multicore Technology for Digital Convergence -- StarDBT: An Efficient Multi-platform Dynamic Binary Translation System -- Unbiased Branches: An Open Problem -- An Online Profile Guided Optimization Approach for Speculative Parallel Threading -- Entropy-Based Profile Characterization and Classification for Automatic Profile Management -- Laplace Transformation on the FT64 Stream Processor -- Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation -- Evolution of NAND Flash Memory Interface -- FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs -- Exploiting Single-Usage for Effective Memory Management -- An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories -- An Effective Design of Master-Slave Operating System Architecture for Multiprocessor Embedded Systems -- Optimal Placement of Frequently Accessed IPs in Mesh NoCs -- An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips -- Performance of Keyword Connection Algorithm in Nested Mobility Networks -- Leakage Energy Reduction in Cache Memory by Software Self-invalidation -- Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters -- Runtime Performance Projection Model for Dynamic Power Management -- A Power-Aware Alternative for the Perceptron Branch Predictor -- Power Consumption and Performance Analysis of 3D NoCs -- A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels -- Bipartition Architecture for Low Power JPEG Huffman Decoder -- A SWP Specification for Sequential Image Processing Algorithms -- A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision -- FPGA-Accelerated Active Shape Model for Real-Time People Tracking -- Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures -- Synchronization Mechanisms on Modern Multi-core Architectures -- Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs -- Generalized Wormhole Switching: A New Fault-Tolerant Mathematical Model for Adaptively Wormhole-Routed Interconnect Networks -- Open Issues in MPI Implementation -- Implicit Transactional Memory in Kilo-Instruction Multiprocessors -- Design of a Low–Power Embedded Processor Architecture Using Asynchronous Function Units -- A Bypass Mechanism to Enhance Branch Predictor for SMT Processors -- Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor -- Architectural Solution to Object-Oriented Programming.
Record Nr.	UNISA-996465487703316

Edizione	[1st ed. 2006.]
Pubbl/distr/stampa	Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006
Descrizione fisica	1 online resource (XIV, 605 p.)
Disciplina	004.2/2
Collana	Theoretical Computer Science and General Issues
Soggetto topico	Computer systems Computer arithmetic and logic units Computer input-output equipment Logic design Computer networks Microprocessors Computer architecture Computer System Implementation Arithmetic and Logic Structures Input/Output and Data Communications Logic Design Computer Communication Networks Processor Architectures
ISBN	3-540-40058-3
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	The Era of Multi-core Chips -A Fresh Look on Software Challenges -- Streaming Networks for Coordinating Data-Parallel Programs (Position Statement) -- Implementations of Square-Root and Exponential Functions for Large FPGAs -- Using Branch Prediction Information for Near-Optimal I-Cache Leakage -- Scientific Computing Applications on the Imagine Stream Processor -- Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination -- A Study of the Performance Potential for Dynamic Instruction Hints Selection -- Reorganizing UNIX for Reliability -- Critical-Task Anticipation Scheduling Algorithm for Heterogeneous and Grid Computing -- Processor Directed Dynamic Page Policy -- Static WCET Analysis Based Compiler-Directed DVS Energy Optimization in Real-Time Applications -- A Study on Transformation of Self-similar Processes with Arbitrary Marginal Distributions -- ?TC – An Intermediate Language for Programming Chip Multiprocessors -- Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays -- Trace-Based Data Cache Leakage Reduction at Link Time -- Parallelizing User-Defined and Implicit Reductions Globally on Multiprocessors -- Overload Protection for Commodity Network Appliances -- An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit -- A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster -- Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor -- Combining Wireless Sensor Network with Grid for Intelligent City Traffic -- A Novel Processor Architecture for Real-Time Control -- A 0-1 Integer Linear Programming Based Approach for Global Locality Optimizations -- Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs -- Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection Networks -- Design of an Efficient Flexible Architecture for Color Image Enhancement -- Hypercube Communications on Optical Chordal Ring Networks with Chord Length of Three -- PMPS(3): A Performance Model of Parallel Systems -- Issues and Support for Dynamic Register Allocation -- A Heterogeneous Multi-core Processor Architecture for High Performance Computing -- Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation -- Fault-Free Pairwise Independent Hamiltonian Paths on Faulty Hypercubes -- Constructing Node-Disjoint Paths in Enhanced Pyramid Networks -- Striping Cache: A Global Cache for Striped Network File System -- DTuplesHPC: Distributed Tuple Space for Desktop High Performance Computing -- The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier -- Live Range Aware Cache Architecture -- The Challenges of Efficient Code-Generation for Massively Parallel Architectures -- Reliable Systolic Computing Through Redundancy -- A Diversity-Controllable Genetic Algorithm for Optimal Fused Traffic Planning on Sensor Networks -- A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling -- On the Reliability of Drowsy Instruction Caches -- Design of a Reconfigurable Cryptographic Engine -- Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors -- The New BCD Subtractor and Its Reversible Logic Implementation -- Power-Efficient Microkernel of Embedded Operating System on Chip -- Understanding Prediction Limits Through Unbiased Branches -- Bandwidth Optimization of the EMCI for a High Performance 32-bit DSP -- Research on Petersen Graphs and Hyper-cubes Connected Interconnection Networks -- Cycle Period Analysis and Optimization of Timed Circuits -- Acceleration Techniques for Chip-Multiprocessor Simulator Debug -- A DDL–Based Software Architecture Model -- Branch Behavior Characterization for Multimedia Applications -- Optimization and Evaluating of StreamYGX2 on MASA Stream Processor -- SecureTorrent: A Security Framework for File Swarming -- Register Allocation on Stream Processor with Local Register File -- A Self-reconfigurable System-on-Chip Architecture for Satellite On-Board Computer Maintenance -- Compile-Time Thread Distinguishment Algorithm on VIM-Based Architecture -- Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining -- Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications -- Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols -- An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors -- An Efficient Approach to Energy Saving in Microcontrollers.
Record Nr.	UNISA-996465886003316

Edizione	[1st ed. 2005.]
Pubbl/distr/stampa	Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005
Descrizione fisica	1 online resource (XVIII, 834 p.)
Disciplina	004.2/2
Collana	Theoretical Computer Science and General Issues
Soggetto topico	Computer systems Computer arithmetic and logic units Computer input-output equipment Logic design Computer networks Microprocessors Computer architecture Computer System Implementation Arithmetic and Logic Structures Input/Output and Data Communications Logic Design Computer Communication Networks Processor Architectures
ISBN	3-540-32108-X 3-540-29643-3
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Keynote Address I -- Processor Architecture for Trustworthy Computers -- Session 1A: Energy Efficient and Power Aware Techniques -- Efficient Voltage Scheduling and Energy-Aware Co-synthesis for Real-Time Embedded Systems -- Energy-Effective Instruction Fetch Unit for Wide Issue Processors -- Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty -- An Innovative Instruction Cache for Embedded Processors -- Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) Processor -- Session 1B: Methodologies and Architectures for Application-Specific Systems -- Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution -- A Pipelined Hardware Architecture for Motion Estimation of H.264/AVC -- Embedded Intelligent Imaging On-Board Small Satellites -- Architectural Enhancements for Color Image and Video Processing on Embedded Systems -- A Portable Doppler Device Based on a DSP with High- Performance Spectral Estimation and Output -- Session 2A: Processor Architectures and Microarchitectures -- A Power-Efficient Processor Core for Reactive Embedded Applications -- A Stream Architecture Supporting Multiple Stream Execution Models -- The Challenges of Massive On-Chip Concurrency -- FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit -- Session 2B: High-Reliability and Fault-Tolerant Architectures -- Modularized Redundant Parallel Virtual File System -- Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures -- A Fault-Tolerant Routing Strategy for Fibonacci-Class Cubes -- Embedding of Cycles in the Faulty Hypercube -- Session 3A: Compiler and OS for Emerging Architectures -- Improving the Performance of GCC by Exploiting IA-64 Architectural Features -- An Integrated Partitioning and Scheduling Based Branch Decoupling -- A Register Allocation Framework for Banked Register Files with Access Constraints -- Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems -- Irregular Redistribution Scheduling by Partitioning Messages -- Session 3B: Data Value Predictions -- Making Power-Efficient Data Value Predictions -- Speculative Issue Logic -- Using Decision Trees to Improve Program-Based and Profile-Based Static Branch Prediction -- Arithmetic Data Value Speculation -- Exploiting Thread-Level Speculative Parallelism with Software Value Prediction -- Keynote Address II -- Challenges and Opportunities on Multi-core Microprocessor -- Session 4A: Reconfigurable Computing Systems and Polymorphic Architectures -- Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures -- A Switch Wrapper Design for SNA On-Chip-Network -- A Configuration System Architecture Supporting Bit-Stream Compression for FPGAs -- Biological Sequence Analysis with Hidden Markov Models on an FPGA -- FPGAs for Improved Energy Efficiency in Processor Based Systems -- Morphable Structures for Reconfigurable Instruction Set Processors -- Session 4B: Interconnect Networks and Network Interfaces -- Implementation of a Hybrid TCP/IP Offload Engine Prototype -- Matrix-Star Graphs: A New Interconnection Network Based on Matrix Operations -- The Channel Assignment Algorithm on RP(k) Networks -- Extending Address Space of IP Networks with Hierarchical Addressing -- The Star-Pyramid Graph: An Attractive Alternative to the Pyramid -- Building a Terabit Router with XD Networks -- Session 5A: Parallel Architectures and Computation Models -- A Real Coded Genetic Algorithm for Data Partitioning and Scheduling in Networks with Arbitrary Processor Release Time -- D3DPR: A Direct3D-Based Large-Scale Display Parallel Rendering System Architecture for Clusters -- Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures -- A Technique to Reduce Preemption Overhead in Real-Time Multiprocessor Task Scheduling -- Session 5B: Hardware-Software Partitioning, Verification, and Testing of Complex Architectures -- Minimizing Power in Hardware/Software Partitioning -- Exploring Design Space Using Transaction Level Models -- Increasing Embedding Probabilities of RPRPs in RIN Based BIST -- A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture -- Session 6A: Architectures for Secured Computing -- DRIL– A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding Techniques -- Efficient Architectural Support for Secure Bus-Based Shared Memory Multiprocessor -- Covert Channel Analysis of the Password-Capability System -- Session 6B: Simulation and Performance Evaluation -- Comparing Low-Level Behavior of SPEC CPU and Java Workloads -- Application of Real-Time Object-Oriented Modeling Technique for Real-Time Computer Control -- VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers -- Session 7: Architectures for Emerging Technologies and Applications I -- Analysis of Real-Time Communication System with Queuing Priority -- FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks -- A Study on the Performance Evaluation of Forward Link in CDMA Mobile Communication Systems -- Session 8: Memory Systems Hierarchy and Management -- Cache Leakage Management for Multi-programming Workloads -- A Memory Bandwidth Effective Cache Store Miss Policy -- Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance -- Targeted Data Prefetching -- Session 9: Architectures for Emerging Technologies and Applications II -- Area-Time Efficient Systolic Architecture for the DCT -- Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform -- A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures -- Implementation and Analysis of TCP/IP Offload Engine and RDMA Transfer Mechanisms on an Embedded System.
Record Nr.	UNISA-996466223603316

Edizione	[1st ed. 2019.]
Pubbl/distr/stampa	Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019
Descrizione fisica	1 online resource (XIX, 462 p. 181 illus., 106 illus. in color.)
Disciplina	005.3
Collana	Theoretical Computer Science and General Issues
Soggetto topico	Algorithms Artificial intelligence Computer networks Computer arithmetic and logic units Application software Artificial Intelligence Computer Communication Networks Arithmetic and Logic Structures Computer and Information Systems Applications
ISBN	3-030-26369-X
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Novel Models and Algorithms for Optimization -- Generative Adversarial Optimization -- Digital Model of Swarm Unit System with Interruptions -- Algorithm Integration Behavior for Discovering Group Membership Rules -- Success History Based Position Adaptation in Co-Operation of Biology Related Algorithms -- An Inter-Peer Communication Mechanism Based Water Cycle Algorithm -- Cooperation-based Gene Regulatory Network for Target Entrapment -- Population-based Metaheuristics for Planning Interval Training Sessions in Mountain Biking -- Comparison of Infrastructure and Adhoc Modes in Survivable Networks Enabled by Evolutionary Swarms -- Particle Swarm Optimization -- An Analysis of Control Parameter Importance in the Particle Swarm Optimization Algorithm -- Parameters Optimization Of Relay Self-Oscillations Sampled Data Controller Based On Particle Swarm Optimization -- Niching Particle Swarm Optimizer with Entropy-based Exploration Strategy for Global Optimization -- A Study on Designing an Aperiodic Antenna Array using Boolean PSO -- Building Energy Performance Optimization: A New Multi-Objective Particle Swarm Method -- A Novel PSOEDE Algorithm for Vehicle Scheduling Problem in Public Transportation -- Hierarchical Competition Framework for Particle Swarm Optimization -- Study on Method of Cutting Trajectory Planning Based on Improved Particle Swarm Optimization for Roadheader -- Variants and Parameter Investigations of Particle Swarm Optimisation for Solving Course Timetabling Problems -- Ant Colony Optimization -- Multiple Start Modifications Of Ant Colony Algorithm For Multiversion Software Design -- Ant Colony Algorithm for Cell Tracking Based on Gaussian Cloud Model -- Physarum-based Ant Colony Optimization for Graph Coloring Problem -- Ant Colony Algorithm Based Scheduling with Lot-sizing for Printed Circuit Board Assembly Shop -- Variable Speed Robot Navigation by an ACO Approach -- Solving Scheduling Problem in PCB Assembly and Its Optimization Using ACO -- Fireworks Algorithms and Brain Storm Optimization -- Accelerating Fireworks Algorithm with Weight-based Guiding Sparks -- Last-position Elimination-based Fireworks Algorithm for Function Optimization -- Planar Thinned Antenna Array Synthesis Using Modified Brain Storm Optimization -- Refrigerated Showcase Fault Detection by a Correntropy Based Artificial Neural Network Using Fast Brain Storm Optimization -- Swarm Intelligence Algorithms and Improvements -- Automatic Diet Generation by Artificial Bee Colony Algorithm -- A Multi-strategy Artificial Bee Colony Algorithm with Neighborhood Search -- Cuckoo Search Algorithm for Border Reconstruction of Medical Images with Rational Curves -- Quantum Behaved Fruit Fly Optimization Algorithm for Continuous Function Optimization Problems -- Parameter Estimation of a Nonlinear Hydrologic Model for Channel Flood Routing with The Bat Algorithm -- Bacterial Foraging Optimization with Memory and Clone Schemes for Dynamic Environments -- Genetic Algorithm and Differential Evolution -- Evaluation of Genetic Algorithm and Hybrid Genetic Algorithm-Hill Climbing with Elitist for Lecturer University Timetabling Problem -- Federated Learning Assisted Interactive EDA with Dual Probabilistic Models for Personalized Search -- Second Order Differential Evolution for Constrained Optimization -- Computability and Stability for Hybrid Algorithms -- Swarm Robotics -- Stochastic Self-Organizing Control for Swarm Robot Systems -- Framework for Evaluation of Swarm-based Chemical Reaction Optimization Algorithm -- Mixed Game Pigeon-inspired Optimization for Unmanned Aircraft System Swarm Formation -- Research on UAV Task Assignment Method Based on Parental Genetic Algorithm -- A Comparison among the Denavit - Hartenberg, the Screw Theory, and the Iterative Methods to Solve Inverse Kinematics for Assistant Robot Arm.
Record Nr.	UNISA-996466213603316