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Dynamic Brain - from Neural Spikes to Behaviors [[electronic resource] ] : 12th International Summer School on Neural Networks, Erice, Italy, December 5-12, 2007, Revised Lectures / / edited by Maria Marinaro, Silvia Scarpetta, Yoko Yamaguchi
| Dynamic Brain - from Neural Spikes to Behaviors [[electronic resource] ] : 12th International Summer School on Neural Networks, Erice, Italy, December 5-12, 2007, Revised Lectures / / edited by Maria Marinaro, Silvia Scarpetta, Yoko Yamaguchi |
| Edizione | [1st ed. 2008.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 |
| Descrizione fisica | 1 online resource (VIII, 143 p.) |
| Disciplina | 512.0285 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Artificial intelligence
Computer science Computer storage devices Memory management (Computer science) Computer science—Mathematics Neurosciences Artificial Intelligence Theory of Computation Computer Memory Structure Symbolic and Algebraic Manipulation Neuroscience |
| ISBN | 3-540-88853-5 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Hippocampus and Neural Oscillations -- The Brain Computation Based on Synchronization of Nonlinear Oscillations: On Theta Rhythms in Rat Hippocampus and Human Scalp EEG -- Theta Phase Coding in Human Hippocampus: A Combined Approach of a Computational Model and Human Brain Activity Analyses -- Mechanisms for Memory-Guided Behavior Involving Persistent Firing and Theta Rhythm Oscillations in the Entorhinal Cortex -- Encoding and Replay of Dynamic Attractors with Multiple Frequencies: Analysis of a STDP Based Learning Rule -- A Biophysical Model of Cortical Up and Down States: Excitatory-Inhibitory Balance and H-Current -- Dynamics in Olfactory System and Behaviour -- Dynamical Architecture of the Mammalian Olfactory System -- From Behaviour to Brain Dynamics -- Correlation Structure of Spiking Trains -- Impact of Higher-Order Correlations on Coincidence Distributions of Massively Parallel Data -- Comparing Kurtosis Score to Traditional Statistical Metrics for Characterizing the Structure in Neural Ensemble Activity -- Neural Network Theories on Associative Memory -- Pioneeristic Works on Neuronal Nets: A Short History -- Place-Field and Memory Formation in the Hippocampus -- Improving Recall in an Associative Neural Network of Spiking Neurons. |
| Record Nr. | UNISA-996466097803316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Dynamic Brain - from Neural Spikes to Behaviors : 12th International Summer School on Neural Networks, Erice, Italy, December 5-12, 2007, Revised Lectures / / edited by Maria Marinaro, Silvia Scarpetta, Yoko Yamaguchi
| Dynamic Brain - from Neural Spikes to Behaviors : 12th International Summer School on Neural Networks, Erice, Italy, December 5-12, 2007, Revised Lectures / / edited by Maria Marinaro, Silvia Scarpetta, Yoko Yamaguchi |
| Edizione | [1st ed. 2008.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 |
| Descrizione fisica | 1 online resource (VIII, 143 p.) |
| Disciplina | 512.0285 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Artificial intelligence
Computer science Computer storage devices Memory management (Computer science) Computer science—Mathematics Neurosciences Artificial Intelligence Theory of Computation Computer Memory Structure Symbolic and Algebraic Manipulation Neuroscience |
| ISBN | 3-540-88853-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Hippocampus and Neural Oscillations -- The Brain Computation Based on Synchronization of Nonlinear Oscillations: On Theta Rhythms in Rat Hippocampus and Human Scalp EEG -- Theta Phase Coding in Human Hippocampus: A Combined Approach of a Computational Model and Human Brain Activity Analyses -- Mechanisms for Memory-Guided Behavior Involving Persistent Firing and Theta Rhythm Oscillations in the Entorhinal Cortex -- Encoding and Replay of Dynamic Attractors with Multiple Frequencies: Analysis of a STDP Based Learning Rule -- A Biophysical Model of Cortical Up and Down States: Excitatory-Inhibitory Balance and H-Current -- Dynamics in Olfactory System and Behaviour -- Dynamical Architecture of the Mammalian Olfactory System -- From Behaviour to Brain Dynamics -- Correlation Structure of Spiking Trains -- Impact of Higher-Order Correlations on Coincidence Distributions of Massively Parallel Data -- Comparing Kurtosis Score to Traditional Statistical Metrics for Characterizing the Structure in Neural Ensemble Activity -- Neural Network Theories on Associative Memory -- Pioneeristic Works on Neuronal Nets: A Short History -- Place-Field and Memory Formation in the Hippocampus -- Improving Recall in an Associative Neural Network of Spiking Neurons. |
| Record Nr. | UNINA-9910768181003321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Facing the Multicore-Challenge III [[electronic resource] ] : Aspects of New Paradigms and Technologies in Parallel Computing / / edited by Rainer Keller, David Kramer, Jan-Philipp Weiß
| Facing the Multicore-Challenge III [[electronic resource] ] : Aspects of New Paradigms and Technologies in Parallel Computing / / edited by Rainer Keller, David Kramer, Jan-Philipp Weiß |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 |
| Descrizione fisica | 1 online resource (X, 146 p. 61 illus.) |
| Disciplina | 004.1 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Microprocessors
Computer architecture Electronic digital computers—Evaluation Software engineering Computer graphics Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Processor Architectures System Performance and Evaluation Software Engineering Computer Graphics Arithmetic and Logic Structures Computer Memory Structure |
| ISBN | 3-642-35892-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996465996903316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro |
| Edizione | [1st ed. 2009.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 |
| Descrizione fisica | 1 online resource (XIII, 462 p.) |
| Disciplina | 620/.004202825536 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Logic design
Microprocessors Computer architecture Electronic digital computers—Evaluation Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Electronic circuits Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Computer Memory Structure Electronic Circuits and Systems |
| ISBN | 3-540-95948-3 |
| Classificazione |
DAT 190f
ELT 272f SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Session 1: Low-Leakage and Subthreshold Circuits -- Subthreshold FIR Filter Architecture for Ultra Low Power Applications -- Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs -- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits -- Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction -- Session 2: Low-Power Methods and Models -- Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating -- Intelligate: Scalable Dynamic Invariant Learning for Power Reduction -- Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption -- Power-Aware Design via Micro-architectural Link to Implementation -- Untraditional Approach to Computer Energy Reduction -- Session 3: Arithmetic and Memories -- Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication -- Power Optimization of Parallel Multipliers in Systems with Variable Word-Length -- A Design Space Comparison of 6T and 8T SRAM Core-Cells -- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization -- Session 4: Variability and Statistical Timing -- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic -- A Study on CMOS Time Uncertainty with Technology Scaling -- Static Timing Model Extraction for Combinational Circuits -- A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA -- Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power -- Session 5: Synchronization and Interconnect -- Logic Synthesis of Handshake Components Using Structural Clustering Techniques -- Fast Universal Synchronizers -- A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router -- PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels -- Session 6: Power Supplies and Switching Noise -- Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits -- A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint -- Generating Worst-Case Stimuli for Accurate Power Grid Analysis -- Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization -- Session 7: Low-Power Circuits; Reconfigurable Architectures -- Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements -- A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation -- Energy Efficient Elliptic Curve Processor -- Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing -- Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures -- Poster Session 1: Circuits and Methods -- Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers -- Ultra Low Voltage High Speed Differential CMOS Inverter -- Differential Capacitance Analysis -- Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey -- Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses -- Poster Session 2: Power and Delay Modeling -- Analytical High-Level Power Model for LUT-Based Components -- A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption -- Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates -- Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level -- Data Dependence of Delay Distribution for a Planar Bus -- Special Session: Power Optimizations Addressing Reconfigurable Architectures -- Towards Novel Approaches in Design Automation for FPGA Power Optimization -- Smart Enumeration: A Systematic Approach to Exhaustive Search -- An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs -- Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor -- Keynotes (Abstracts) -- Integration of Power Management Units onto the SoC -- Model to Hardware Matching for nm Scale Technologies -- Power and Profit: Engineering in the Envelope. |
| Record Nr. | UNISA-996465962903316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (XIV, 586 p.) |
| Disciplina | 621.395 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Logic design
Microprocessors Computer architecture Electronic digital computers—Evaluation Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Electronic circuits Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Computer Memory Structure Electronic Circuits and Systems |
| ISBN | 3-540-74442-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Session 1 - High-Level Design (1) -- System-Level Application-Specific NoC Design for Network and Multimedia Applications -- Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements -- A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms -- An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture -- Session 2 - Low Power Design Techniques -- Template Vertical Dictionary-Based Program Compression Scheme on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs -- Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports -- The Design and Implementation of a Power Efficient Embedded SRAM -- Session 3 - Low Power Analog Circuits -- Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN -- Settling Time Minimization of Operational Amplifiers -- Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs -- Session 4 - Statistical Static Timing Analysis -- Computation of Joint Timing Yield of Sequential Networks Considering Process Variations -- A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation -- A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits -- Session 5 - Power Modeling and Optimization -- A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect -- Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components -- Logic Style Comparison for Ultra Low Power Operation in 65nm Technology -- Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation -- Session 6 - Low Power Routing Optimization -- Clock Distribution Techniques for Low-EMI Design -- Crosstalk Waveform Modeling Using Wave Fitting -- Weakness Identification for Effective Repair of Power Distribution Network -- New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses -- On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects -- Session 7 - High Level Design (2) -- Soft Error-Aware Power Optimization Using Gate Sizing -- Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices -- RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating -- Functional Verification of Low Power Designs at RTL -- XEEMU: An Improved XScale Power Simulator -- Session 8 - Security and Asynchronous Design -- Low Power Elliptic Curve Cryptography -- Design and Test of Self-checking Asynchronous Control Circuit -- An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips -- Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA -- Session 9 - Low Power Applications -- Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform -- The Energy Scalability of Wavelet-Based, Scalable Video Decoding -- Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption -- Poster 1 - Modeling and Optimization -- Exploiting Input Variations for Energy Reduction -- A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates -- Static Power Consumption in CMOS Gates Using Independent Bodies -- Moderate Inversion: Highlights for Low Voltage Design -- On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems -- Semi Custom Design: A Case Study on SIMD Shufflers -- Poster 2 - High Level Design -- Optimization for Real-Time Systems with Non-convex Power Versus Speed Models -- Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS -- A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits -- Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates -- A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning -- Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems -- Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate -- Poster 3 - Low Power Techniques and Applications -- A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations -- Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data -- Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply -- Low-Power Digital Filtering Based on the Logarithmic Number System -- A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling -- Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers -- Keynotes -- Design and Industrialization Challenges of Memory Dominated SOCs -- Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies -- Analog Power Modelling -- Industrial Session - Design Challenges in Real-Life Projects -- Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms -- System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters. |
| Record Nr. | UNISA-996465995703316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
| Descrizione fisica | 1 online resource (XIV, 586 p.) |
| Disciplina | 621.395 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Logic design
Microprocessors Computer architecture Electronic digital computers—Evaluation Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Electronic circuits Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Computer Memory Structure Electronic Circuits and Systems |
| ISBN | 3-540-74442-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Session 1 - High-Level Design (1) -- System-Level Application-Specific NoC Design for Network and Multimedia Applications -- Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements -- A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms -- An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture -- Session 2 - Low Power Design Techniques -- Template Vertical Dictionary-Based Program Compression Scheme on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs -- Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports -- The Design and Implementation of a Power Efficient Embedded SRAM -- Session 3 - Low Power Analog Circuits -- Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN -- Settling Time Minimization of Operational Amplifiers -- Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs -- Session 4 - Statistical Static Timing Analysis -- Computation of Joint Timing Yield of Sequential Networks Considering Process Variations -- A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation -- A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits -- Session 5 - Power Modeling and Optimization -- A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect -- Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components -- Logic Style Comparison for Ultra Low Power Operation in 65nm Technology -- Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation -- Session 6 - Low Power Routing Optimization -- Clock Distribution Techniques for Low-EMI Design -- Crosstalk Waveform Modeling Using Wave Fitting -- Weakness Identification for Effective Repair of Power Distribution Network -- New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses -- On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects -- Session 7 - High Level Design (2) -- Soft Error-Aware Power Optimization Using Gate Sizing -- Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices -- RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating -- Functional Verification of Low Power Designs at RTL -- XEEMU: An Improved XScale Power Simulator -- Session 8 - Security and Asynchronous Design -- Low Power Elliptic Curve Cryptography -- Design and Test of Self-checking Asynchronous Control Circuit -- An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips -- Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA -- Session 9 - Low Power Applications -- Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform -- The Energy Scalability of Wavelet-Based, Scalable Video Decoding -- Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption -- Poster 1 - Modeling and Optimization -- Exploiting Input Variations for Energy Reduction -- A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates -- Static Power Consumption in CMOS Gates Using Independent Bodies -- Moderate Inversion: Highlights for Low Voltage Design -- On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems -- Semi Custom Design: A Case Study on SIMD Shufflers -- Poster 2 - High Level Design -- Optimization for Real-Time Systems with Non-convex Power Versus Speed Models -- Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS -- A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits -- Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates -- A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning -- Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems -- Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate -- Poster 3 - Low Power Techniques and Applications -- A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations -- Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data -- Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply -- Low-Power Digital Filtering Based on the Logarithmic Number System -- A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling -- Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers -- Keynotes -- Design and Industrialization Challenges of Memory Dominated SOCs -- Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies -- Analog Power Modelling -- Industrial Session - Design Challenges in Real-Life Projects -- Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms -- System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters. |
| Record Nr. | UNINA-9910484643403321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings / / edited by Johan Vounckx, Nadine Azemard, Philippe Maurine
| Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings / / edited by Johan Vounckx, Nadine Azemard, Philippe Maurine |
| Edizione | [1st ed. 2006.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 |
| Descrizione fisica | 1 online resource (XVI, 677 p.) |
| Disciplina | 621.395 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer science
Logic design Microprocessors Computer architecture Electronic digital computers—Evaluation Computer arithmetic and logic units Computer storage devices Memory management (Computer science) Theory of Computation Logic Design Processor Architectures System Performance and Evaluation Arithmetic and Logic Structures Computer Memory Structure |
| ISBN | 3-540-39097-9 |
| Classificazione | SS 4800 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Session 1 – High-Level Design -- Session 2 – Power Estimation / Modeling -- Session 3 – Memory and Register Files -- Session 4 – Low-Power Digital Circuits -- Session 5 – Busses and Interconnects -- Session 6 – Low Power Techniques -- Session 7 – Applications and SoC Design -- Session 8 – Modeling -- Session 9 – Digital Circuits -- Session 10 – Reconfigurable and Programmable Devices -- Poster 1 -- Poster 2 -- Poster 3 -- Keynotes -- Industrial Session. |
| Record Nr. | UNISA-996466116403316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Parallel Processing and Applied Mathematics [[electronic resource] ] : 7th International Conference, PPAM 2007, Gdansk, Poland, September 9-12, 2007, Revised Selected papers / / edited by Roman Wyrzykowski, Jack Dongarra, Konrad Karczewski, Jerzy Wasniewski
| Parallel Processing and Applied Mathematics [[electronic resource] ] : 7th International Conference, PPAM 2007, Gdansk, Poland, September 9-12, 2007, Revised Selected papers / / edited by Roman Wyrzykowski, Jack Dongarra, Konrad Karczewski, Jerzy Wasniewski |
| Edizione | [1st ed. 2008.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 |
| Descrizione fisica | 1 online resource (L, 1418 p.) |
| Disciplina | 004/.35 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Software engineering
Algorithms Computer science—Mathematics Computer storage devices Memory management (Computer science) Computer networks Mathematics—Data processing Software Engineering Mathematics of Computing Computer Memory Structure Computer Communication Networks Computational Mathematics and Numerical Analysis |
| ISBN | 3-540-68111-6 |
| Classificazione | 54.50 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Parallel/Distributed Architectures and Mobile Computing -- Numerical Algorithms and Parallel Numerics -- Parallel and Distributed Non-numerical Algorithms -- Environments and Tools for Parallel/Distributed/Grid Computing -- Applications of Parallel/Distributed/Grid Computing -- Evolutionary Computing, Meta-Heuristics and Neural Networks -- The Second Minisymposium on Novel Data Formats and Algorithms for Dense Linear Algebra Computations -- Combinatorial Tools for Parallel Sparse Matrix Computations Workshop -- The Third Grid Applications and Middleware Workshop (GAMW’07) -- The Third Workshop on Large Scale Computations on Grids (LaSCoG’07) -- Workshop on Models, Algorithms and Methodologies for Grid-Enabled Computing Environments -- Workshop on Scheduling for Parallel Computing (SPC’07) -- The Second Workshop on Language-Based Parallel Programming Models (WLPP’07) -- Workshop on Performance Evaluation of Parallel Applications on Large-Scale Systems -- Workshop on Parallel Computational Biology (PBC’2007) -- Workshop on High Performance Computing for Engineering Applications -- Minisymposium on Interval Analysis. |
| Record Nr. | UNISA-996465594403316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Parallel Processing and Applied Mathematics [[electronic resource] ] : 6th International Conference, PPAM 2005, Poznan, Poland, September 11-14, 2005, Revised Selected Papers / / edited by Roman Wyrzykowski, Jack Dongarra, Norbert Meyer, Jerzy Wasniewski
| Parallel Processing and Applied Mathematics [[electronic resource] ] : 6th International Conference, PPAM 2005, Poznan, Poland, September 11-14, 2005, Revised Selected Papers / / edited by Roman Wyrzykowski, Jack Dongarra, Norbert Meyer, Jerzy Wasniewski |
| Edizione | [1st ed. 2006.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 |
| Descrizione fisica | 1 online resource (XXIII, 1126 p.) |
| Disciplina | 003.3 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer systems
Software engineering Algorithms Computer science—Mathematics Computer storage devices Memory management (Computer science) Computer networks Computer System Implementation Software Engineering Mathematics of Computing Computer Memory Structure Computer Communication Networks |
| ISBN | 3-540-34142-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Parallel and Distributed Architectures -- Paralel and Distributed Non-numerical Algorithms -- Performance Analysis, Prediction and Optimization -- Grid Programming -- Tools and Environments for Clusters and Grids -- Applications of Parallel/Distributed/Grid Computing -- Evolutionary Computing with Applications -- Parallel Data Mining -- Parallel Numerics -- Computer Methods -- The Second Grid Application and Middleware Workshop (GAMW’2005) -- The Second Grid Resource Management Workshop (GRMW’2005) -- Workshop on Large Scale Computations on Grids -- Workshop on Scheduling for Parallel Computing -- Workshop on Language-Based Parallel Programming Models -- Workshop on Language-Based Parallel Programming Models -- Workshop on HPC Linear Algebra Libraries for Computers with Multilevel Memories -- Workshop on Parallel Bio-computing. |
| Record Nr. | UNISA-996465879303316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Pro .NET Memory Management : For Better Code, Performance, and Scalability / / by Konrad Kokosa, Christophe Nasarre, Kevin Gosse
| Pro .NET Memory Management : For Better Code, Performance, and Scalability / / by Konrad Kokosa, Christophe Nasarre, Kevin Gosse |
| Autore | Kokosa Konrad |
| Edizione | [2nd ed. 2024.] |
| Pubbl/distr/stampa | Berkeley, CA : , : Apress : , : Imprint : Apress, , 2024 |
| Descrizione fisica | 1 online resource (780 pages) |
| Disciplina | 005.268 |
| Altri autori (Persone) |
NasarreChristophe
GosseKevin |
| Soggetto topico |
Microsoft software
Microsoft .NET Framework Computer storage devices Memory management (Computer science) Compilers (Computer programs) Software engineering Microsoft Computer Memory Structure Compilers and Interpreters Software Engineering |
| ISBN | 979-88-6880-453-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | 1. Basic Concepts -- 2. Low-Level Memory Management -- 3. Memory Measurements -- 4. .NET Fundamentals -- 5. Memory Partitioning -- 6. Memory Allocation -- 7. Garbage Collection: Introduction -- 8. Garbage Collection: Mark Phase -- 9. Garbage Collection: Plan Phase -- 10. Garbage Collection: Sweep and Compact.-11. GC Flavors -- 12. Finalization -- 13. Miscellaneous Topics -- 14. Advanced Techniques -- 15. Programmatical APIs. |
| Record Nr. | UNINA-9910899897403321 |
Kokosa Konrad
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| Berkeley, CA : , : Apress : , : Imprint : Apress, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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