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MARC Lista (tabellare)
Big Memory Systems / / by Yu Hua
Big Memory Systems / / by Yu Hua
Autore Yu Hua
Edizione [1st ed. 2026.]
Pubbl/distr/stampa Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2026
Descrizione fisica 1 online resource (297 pages)
Disciplina 004.53
Collana Computer Science Series
Soggetto topico Computer storage devices
Memory management (Computer science)
Information storage and retrieval systems
Computer systems
Computer Memory Structure
Information Storage and Retrieval
Computer System Implementation
ISBN 981-9528-85-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto "1.Write Optimized and High Performance Persistence in Big Memory" -- "2.Lock free Concurrent Level Design for Persistent Memory" -- "3.GPU enabled Byte Granularity Persistence for Big Memory" -- "4.Scalable Learned Key Value Store for Disaggregated Memory" -- "5.Fast One sided RDMA based Transactions for Disaggregated Memory" -- "6.Multi Versioning Design for Distributed Transactions on Big Memory" -- "7.Fast and Cost Efficient Hashing Index Schemes for Cloud Systems" -- "8.Mitigating Asymmetric Read and Write Costs in Cuckoo based Designs".
Record Nr. UNINA-9911049220303321
Yu Hua  
Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2026
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Computer Engineering and Technology : 18th CCF Conference, NCCET 2014, Guiyang, China, July 29 -- August 1, 2014. Revised Selected Papers / / edited by Weixia Xu, Liquan Xiao, Jinwen Li, Chengyi Zhang, Zhenzhen Zhu
Computer Engineering and Technology : 18th CCF Conference, NCCET 2014, Guiyang, China, July 29 -- August 1, 2014. Revised Selected Papers / / edited by Weixia Xu, Liquan Xiao, Jinwen Li, Chengyi Zhang, Zhenzhen Zhu
Edizione [1st ed. 2015.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2015
Descrizione fisica 1 online resource (XII, 188 p. 110 illus.)
Disciplina 004.16
Collana Communications in Computer and Information Science
Soggetto topico Microprocessors
Computer architecture
Computer arithmetic and logic units
Computer storage devices
Memory management (Computer science)
Logic design
Computers
Processor Architectures
Arithmetic and Logic Structures
Computer Memory Structure
Logic Design
Hardware Performance and Reliability
ISBN 3-662-45815-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Processor architecture -- Computer application and software optimization -- Technology on the horizon.
Record Nr. UNINA-9910299252803321
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2015
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Computer Engineering and Technology : 17th National Conference, NCCET 2013, Xining, China, July 20-22, 2013. Revised Selected Papers / / edited by Weixia Xu, Liquan Xiao, Chengyi Zhang, Jinwen Li, Liyan Yu
Computer Engineering and Technology : 17th National Conference, NCCET 2013, Xining, China, July 20-22, 2013. Revised Selected Papers / / edited by Weixia Xu, Liquan Xiao, Chengyi Zhang, Jinwen Li, Liyan Yu
Edizione [1st ed. 2013.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013
Descrizione fisica 1 online resource (XIV, 252 p. 151 illus.)
Disciplina 004.1
Collana Communications in Computer and Information Science
Soggetto topico Microprocessors
Computer architecture
Computer arithmetic and logic units
Computer storage devices
Memory management (Computer science)
Logic design
Computers
Processor Architectures
Arithmetic and Logic Structures
Computer Memory Structure
Logic Design
Hardware Performance and Reliability
ISBN 3-642-41635-7
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Application Specific Processors -- Communication Architecture -- Computer Application and Software Optimization -- IC Design and Test -- Processor Architecture -- Technology on the Horizon.
Record Nr. UNINA-9910437578703321
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Computer Engineering and Technology : 16th National Conference, NCCET 2012, Shanghai, China, August 17-19, 2012, Revised Selected Papers / / edited by Weixia Xu, Liquan Xiao, Pingjing Lu, Jinwen Li, Chengyi Zhang
Computer Engineering and Technology : 16th National Conference, NCCET 2012, Shanghai, China, August 17-19, 2012, Revised Selected Papers / / edited by Weixia Xu, Liquan Xiao, Pingjing Lu, Jinwen Li, Chengyi Zhang
Edizione [1st ed. 2013.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013
Descrizione fisica 1 online resource (XIV, 263 p. 164 illus.)
Disciplina 004.1
Collana Communications in Computer and Information Science
Soggetto topico Microprocessors
Computer architecture
Computer arithmetic and logic units
Computer storage devices
Memory management (Computer science)
Logic design
Computers
Processor Architectures
Arithmetic and Logic Structures
Computer Memory Structure
Logic Design
Hardware Performance and Reliability
ISBN 3-642-35898-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Session 1: Microprocessor and Implementation -- A Method of Balancing the Global Multi-mode Clock Network in Ultra-large Scale CPU -- Hardware Architecture for the Parallel Generation of Long-Period Random Numbers Using MT Method -- MGTE: A Multi-level Hybrid Verification Platform for a 16-Core Processer -- An Efficient Parallel SURF Algorithm for Multi-core Processor -- A Study of Cache Design in Stream Processor -- Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Processor -- Dynamic and Online Task Scheduling Algorithm Based on Virtual Compute Group in Many-Core Architecture -- ADL and High Performance Processor Design -- Session 2: Design of Integration Circuit -- The Design of the ROHC Header Compression Accelerator -- A Hardware Implementation of Nussinov RNA Folding Algorithm -- A Configurable Architecture for 1-D Discrete Wavelet Transform -- A Comparison of Folded Architectures for the Discrete Wavelet Transform -- A High Performance DSP System with Fault Tolerant for Space Missions -- The Design and Realization of Campus Information Release Platform Based on Android Framework -- A Word-Length Optimized Hardware Gaussian Random Number Generator Based on the Box-Muller Method -- Session 3: I/O Interconnect -- DAMQ Sharing Scheme for Two Physical Channels in High Performance Router -- Design and Implementation of Dynamic Reliable Virtual Channel for Network-on-Chip -- HCCM: A Hierarchical Cross-Connected Mesh for Network on Chip -- Efficient Broadcast Scheme Based on Sub-network Partition for Many-Core CMPs on Gem5 Simulator -- A Quick Method for Mapping Cores Onto 2D-Mesh Based Networks on Chip -- Session 4: Measurement, Verification, and Others -- A Combined Hardware/Software Measurement for ARM Program Execution Time -- A Low-Complexity Parallel Two-Sided Jacobi Complex SVD Algorithm and Architecture for MIMO Beamforming Systems -- A Thermal-Aware Task Mapping Algorithm for Coarse Grain Reconfigurable Computing System -- DC Offset Mismatch Calibration for Time-Interleaved ADCs in High-Speed OFDM Receivers -- An Novel Graph Model for Loop Mapping on Coarse-Grained Reconfigurable Architectures -- Memristor Working Condition Analysis Based on SPICE Model -- On Stepsize of Fast Subspace Tracking Methods.
Record Nr. UNINA-9910437590403321
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Dynamic Brain - from Neural Spikes to Behaviors [[electronic resource] ] : 12th International Summer School on Neural Networks, Erice, Italy, December 5-12, 2007, Revised Lectures / / edited by Maria Marinaro, Silvia Scarpetta, Yoko Yamaguchi
Dynamic Brain - from Neural Spikes to Behaviors [[electronic resource] ] : 12th International Summer School on Neural Networks, Erice, Italy, December 5-12, 2007, Revised Lectures / / edited by Maria Marinaro, Silvia Scarpetta, Yoko Yamaguchi
Edizione [1st ed. 2008.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008
Descrizione fisica 1 online resource (VIII, 143 p.)
Disciplina 512.0285
Collana Theoretical Computer Science and General Issues
Soggetto topico Artificial intelligence
Computer science
Computer storage devices
Memory management (Computer science)
Computer science—Mathematics
Neurosciences
Artificial Intelligence
Theory of Computation
Computer Memory Structure
Symbolic and Algebraic Manipulation
Neuroscience
ISBN 3-540-88853-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Hippocampus and Neural Oscillations -- The Brain Computation Based on Synchronization of Nonlinear Oscillations: On Theta Rhythms in Rat Hippocampus and Human Scalp EEG -- Theta Phase Coding in Human Hippocampus: A Combined Approach of a Computational Model and Human Brain Activity Analyses -- Mechanisms for Memory-Guided Behavior Involving Persistent Firing and Theta Rhythm Oscillations in the Entorhinal Cortex -- Encoding and Replay of Dynamic Attractors with Multiple Frequencies: Analysis of a STDP Based Learning Rule -- A Biophysical Model of Cortical Up and Down States: Excitatory-Inhibitory Balance and H-Current -- Dynamics in Olfactory System and Behaviour -- Dynamical Architecture of the Mammalian Olfactory System -- From Behaviour to Brain Dynamics -- Correlation Structure of Spiking Trains -- Impact of Higher-Order Correlations on Coincidence Distributions of Massively Parallel Data -- Comparing Kurtosis Score to Traditional Statistical Metrics for Characterizing the Structure in Neural Ensemble Activity -- Neural Network Theories on Associative Memory -- Pioneeristic Works on Neuronal Nets: A Short History -- Place-Field and Memory Formation in the Hippocampus -- Improving Recall in an Associative Neural Network of Spiking Neurons.
Record Nr. UNISA-996466097803316
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Dynamic Brain - from Neural Spikes to Behaviors : 12th International Summer School on Neural Networks, Erice, Italy, December 5-12, 2007, Revised Lectures / / edited by Maria Marinaro, Silvia Scarpetta, Yoko Yamaguchi
Dynamic Brain - from Neural Spikes to Behaviors : 12th International Summer School on Neural Networks, Erice, Italy, December 5-12, 2007, Revised Lectures / / edited by Maria Marinaro, Silvia Scarpetta, Yoko Yamaguchi
Edizione [1st ed. 2008.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008
Descrizione fisica 1 online resource (VIII, 143 p.)
Disciplina 512.0285
Collana Theoretical Computer Science and General Issues
Soggetto topico Artificial intelligence
Computer science
Computer storage devices
Memory management (Computer science)
Computer science—Mathematics
Neurosciences
Artificial Intelligence
Theory of Computation
Computer Memory Structure
Symbolic and Algebraic Manipulation
Neuroscience
ISBN 3-540-88853-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Hippocampus and Neural Oscillations -- The Brain Computation Based on Synchronization of Nonlinear Oscillations: On Theta Rhythms in Rat Hippocampus and Human Scalp EEG -- Theta Phase Coding in Human Hippocampus: A Combined Approach of a Computational Model and Human Brain Activity Analyses -- Mechanisms for Memory-Guided Behavior Involving Persistent Firing and Theta Rhythm Oscillations in the Entorhinal Cortex -- Encoding and Replay of Dynamic Attractors with Multiple Frequencies: Analysis of a STDP Based Learning Rule -- A Biophysical Model of Cortical Up and Down States: Excitatory-Inhibitory Balance and H-Current -- Dynamics in Olfactory System and Behaviour -- Dynamical Architecture of the Mammalian Olfactory System -- From Behaviour to Brain Dynamics -- Correlation Structure of Spiking Trains -- Impact of Higher-Order Correlations on Coincidence Distributions of Massively Parallel Data -- Comparing Kurtosis Score to Traditional Statistical Metrics for Characterizing the Structure in Neural Ensemble Activity -- Neural Network Theories on Associative Memory -- Pioneeristic Works on Neuronal Nets: A Short History -- Place-Field and Memory Formation in the Hippocampus -- Improving Recall in an Associative Neural Network of Spiking Neurons.
Record Nr. UNINA-9910768181003321
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2008
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Facing the Multicore-Challenge III [[electronic resource] ] : Aspects of New Paradigms and Technologies in Parallel Computing / / edited by Rainer Keller, David Kramer, Jan-Philipp Weiß
Facing the Multicore-Challenge III [[electronic resource] ] : Aspects of New Paradigms and Technologies in Parallel Computing / / edited by Rainer Keller, David Kramer, Jan-Philipp Weiß
Edizione [1st ed. 2013.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013
Descrizione fisica 1 online resource (X, 146 p. 61 illus.)
Disciplina 004.1
Collana Theoretical Computer Science and General Issues
Soggetto topico Microprocessors
Computer architecture
Electronic digital computers—Evaluation
Software engineering
Computer graphics
Computer arithmetic and logic units
Computer storage devices
Memory management (Computer science)
Processor Architectures
System Performance and Evaluation
Software Engineering
Computer Graphics
Arithmetic and Logic Structures
Computer Memory Structure
ISBN 3-642-35892-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNISA-996465996903316
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Full-Field Structural Imaging Studies of Neuromorphic Devices and their Environments / / by Elliot Kisiel
Full-Field Structural Imaging Studies of Neuromorphic Devices and their Environments / / by Elliot Kisiel
Autore Kisiel Elliot
Edizione [1st ed. 2026.]
Pubbl/distr/stampa Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2026
Descrizione fisica 1 online resource (0 pages)
Disciplina 530.41
Collana Springer Theses, Recognizing Outstanding Ph.D. Research
Soggetto topico Solid state physics
Synchrotrons
Condensed matter
Materials - Microscopy
Computer storage devices
Memory management (Computer science)
Microtechnology
Microelectromechanical systems
Electronic Devices
Synchrotron Techniques
Phase Transition and Critical Phenomena
Microscopy
Computer Memory Structure
Microsystems and MEMS
ISBN 3-032-12107-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Neuromorphic Devices and Microscopy -- X-ray Techniques: Diffraction Contrast Imaging -- Experimental Development -- Filaments -- Barriers -- Substrates.
Record Nr. UNINA-9911066007903321
Kisiel Elliot  
Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2026
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro
Edizione [1st ed. 2009.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009
Descrizione fisica 1 online resource (XIII, 462 p.)
Disciplina 620/.004202825536
Collana Theoretical Computer Science and General Issues
Soggetto topico Logic design
Microprocessors
Computer architecture
Electronic digital computers—Evaluation
Computer arithmetic and logic units
Computer storage devices
Memory management (Computer science)
Electronic circuits
Logic Design
Processor Architectures
System Performance and Evaluation
Arithmetic and Logic Structures
Computer Memory Structure
Electronic Circuits and Systems
ISBN 3-540-95948-3
Classificazione DAT 190f
ELT 272f
SS 4800
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Session 1: Low-Leakage and Subthreshold Circuits -- Subthreshold FIR Filter Architecture for Ultra Low Power Applications -- Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs -- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits -- Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction -- Session 2: Low-Power Methods and Models -- Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating -- Intelligate: Scalable Dynamic Invariant Learning for Power Reduction -- Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption -- Power-Aware Design via Micro-architectural Link to Implementation -- Untraditional Approach to Computer Energy Reduction -- Session 3: Arithmetic and Memories -- Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication -- Power Optimization of Parallel Multipliers in Systems with Variable Word-Length -- A Design Space Comparison of 6T and 8T SRAM Core-Cells -- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization -- Session 4: Variability and Statistical Timing -- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic -- A Study on CMOS Time Uncertainty with Technology Scaling -- Static Timing Model Extraction for Combinational Circuits -- A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA -- Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power -- Session 5: Synchronization and Interconnect -- Logic Synthesis of Handshake Components Using Structural Clustering Techniques -- Fast Universal Synchronizers -- A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router -- PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels -- Session 6: Power Supplies and Switching Noise -- Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits -- A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint -- Generating Worst-Case Stimuli for Accurate Power Grid Analysis -- Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization -- Session 7: Low-Power Circuits; Reconfigurable Architectures -- Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements -- A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation -- Energy Efficient Elliptic Curve Processor -- Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing -- Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures -- Poster Session 1: Circuits and Methods -- Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers -- Ultra Low Voltage High Speed Differential CMOS Inverter -- Differential Capacitance Analysis -- Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey -- Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses -- Poster Session 2: Power and Delay Modeling -- Analytical High-Level Power Model for LUT-Based Components -- A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption -- Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates -- Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level -- Data Dependence of Delay Distribution for a Planar Bus -- Special Session: Power Optimizations Addressing Reconfigurable Architectures -- Towards Novel Approaches in Design Automation for FPGA Power Optimization -- Smart Enumeration: A Systematic Approach to Exhaustive Search -- An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs -- Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor -- Keynotes (Abstracts) -- Integration of Power Management Units onto the SoC -- Model to Hardware Matching for nm Scale Technologies -- Power and Profit: Engineering in the Envelope.
Record Nr. UNISA-996465962903316
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro
Edizione [1st ed. 2009.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009
Descrizione fisica 1 online resource (XIII, 462 p.)
Disciplina 620/.004202825536
Altri autori (Persone) SvenssonLars <1960->
MonteiroJosé <1966->
Collana Theoretical Computer Science and General Issues
Soggetto topico Logic design
Microprocessors
Computer architecture
Electronic digital computers - Evaluation
Computer arithmetic and logic units
Computer storage devices
Memory management (Computer science)
Electronic circuits
Logic Design
Processor Architectures
System Performance and Evaluation
Arithmetic and Logic Structures
Computer Memory Structure
Electronic Circuits and Systems
ISBN 3-540-95948-3
Classificazione DAT 190f
ELT 272f
SS 4800
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Session 1: Low-Leakage and Subthreshold Circuits -- Subthreshold FIR Filter Architecture for Ultra Low Power Applications -- Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs -- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits -- Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction -- Session 2: Low-Power Methods and Models -- Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating -- Intelligate: Scalable Dynamic Invariant Learning for Power Reduction -- Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption -- Power-Aware Design via Micro-architectural Link to Implementation -- Untraditional Approach to Computer Energy Reduction -- Session 3: Arithmetic and Memories -- Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication -- Power Optimization of Parallel Multipliers in Systems with Variable Word-Length -- A Design Space Comparison of 6T and 8T SRAM Core-Cells -- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization -- Session 4: Variability and Statistical Timing -- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic -- A Study on CMOS Time Uncertainty with Technology Scaling -- Static Timing Model Extraction for Combinational Circuits -- A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA -- Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power -- Session 5: Synchronization and Interconnect -- Logic Synthesis of Handshake Components Using Structural Clustering Techniques -- Fast Universal Synchronizers -- A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router -- PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels -- Session 6: Power Supplies and Switching Noise -- Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits -- A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint -- Generating Worst-Case Stimuli for Accurate Power Grid Analysis -- Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization -- Session 7: Low-Power Circuits; Reconfigurable Architectures -- Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements -- A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation -- Energy Efficient Elliptic Curve Processor -- Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing -- Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures -- Poster Session 1: Circuits and Methods -- Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers -- Ultra Low Voltage High Speed Differential CMOS Inverter -- Differential Capacitance Analysis -- Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey -- Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses -- Poster Session 2: Power and Delay Modeling -- Analytical High-Level Power Model for LUT-Based Components -- A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption -- Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates -- Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level -- Data Dependence of Delay Distribution for a Planar Bus -- Special Session: Power Optimizations Addressing Reconfigurable Architectures -- Towards Novel Approaches in Design Automation for FPGA Power Optimization -- Smart Enumeration: A Systematic Approach to Exhaustive Search -- An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs -- Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor -- Keynotes (Abstracts) -- Integration of Power Management Units onto the SoC -- Model to Hardware Matching for nm Scale Technologies -- Power and Profit: Engineering in the Envelope.
Record Nr. UNINA-9910485025903321
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui