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Asynchronous circuit design / / Chris J. Myers
| Asynchronous circuit design / / Chris J. Myers |
| Autore | Myers Chris J. <1969-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | New York, : J. Wiley & Sons, c2001 |
| Descrizione fisica | 1 online resource (425 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Asynchronous circuits - Design and construction
Electronic circuit design |
| ISBN |
1-280-26476-4
9786610264766 0-470-35666-9 0-471-46412-0 0-471-22414-6 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Contents; Preface; Acknowledgments; 1 Introduction; 1.1 Problem Specification; 1.2 Communication Channels; 1.3 Communication Protocols; 1.4 Graphical Representations; 1.5 Delay-Insensitive Circuits; 1.6 Huffman Circuits; 1.7 Muller Circuits; 1.8 Timed Circuits; 1.9 Verification; 1.10 Applications; 1.11 Let's Get Started; 1.12 Sources; Problems; 2 Communication Channels; 2.1 Basic Structure; 2.2 Structural Modeling in VHDL; 2.3 Control Structures; 2.3.1 Selection; 2.3.2 Repetition; 2.4 Deadlock; 2.5 Probe; 2.6 Parallel Communication; 2.7 Example: MiniMIPS; 2.7.1 VHDL Specification
2.7.2 Optimized MiniMIPS2.8 Sources; Problems; 3 Communication Protocols; 3.1 Basic Structure; 3.2 Active and Passive Ports; 3.3 Handshaking Expansion; 3.4 Reshuffling; 3.5 State Variable Insertion; 3.6 Data Encoding; 3.7 Example: Two Wine Shops; 3.8 Syntax-Directed Translation; 3.9 Sources; Problems; 4 Graphical Representations; 4.1 Graph Basics; 4.2 Asynchronous Finite State Machines; 4.2.1 Finite State Machines and Flow Tables; 4.2.2 Burst-Mode State Machines; 4.2.3 Extended Burst-Mode State Machines; 4.3 Petri Nets; 4.3.1 Ordinary Petri Nets; 4.3.2 Signal Transition Graphs 4.4 Timed Event/Level Structures4.5 Sources; Problems; 5 Huffman Circuits; 5.1 Solving Covering Problems; 5.1.1 Matrix Reduction Techniques; 5.1.2 Bounding; 5.1.3 Termination; 5.1.4 Branching; 5.2 State Minimization; 5.2.1 Finding the Compatible Pairs; 5.2.2 Finding the Maximal Compatibles; 5.2.3 Finding the Prime Compatibles; 5.2.4 Setting Up the Covering Problem; 5.2.5 Forming the Reduced Flow Table; 5.3 State Assignment; 5.3.1 Partition Theory and State Assignment; 5.3.2 Matrix Reduction Method; 5.3.3 Finding the Maximal Intersectibles; 5.3.4 Setting Up the Covering Problem 5.3.5 Fed-Back Outputs as State Variables5.4 Hazard-Free Two-Level Logic Synthesis; 5.4.1 Two-Level Logic Minimization; 5.4.2 Prime Implicant Generation; 5.4.3 Prime Implicant Selection; 5.4.4 Combinational Hazards; 5.5 Extensions for MIC Operation; 5.5.1 Transition Cubes; 5.5.2 Function Hazards; 5.5.3 Combinational Hazards; 5.5.4 Burst-Mode Transitions; 5.5.5 Extended Burst-Mode Transitions; 5.5.6 State Minimization; 5.5.7 State Assignment; 5.5.8 Hazard-Free Two-Level Logic Synthesis; 5.6 Multilevel Logic Synthesis; 5.7 Technology Mapping; 5.8 Generalized C-Element Implementation 5.9 Sequential Hazards5.10 Sources; Problems; 6 Muller Circuits; 6.1 Formal Definition of Speed Independence; 6.1.1 Subclasses of Speed-Independent Circuits; 6.1.2 Some Useful Definitions; 6.2 Complete State Coding; 6.2.1 Transition Points and Insertion Points; 6.2.2 State Graph Coloring; 6.2.3 Insertion Point Cost Function; 6.2.4 State Signal Insertion; 6.2.5 Algorithm for Solving CSC Violations; 6.3 Hazard-Free Logic Synthesis; 6.3.1 Atomic Gate Implementation; 6.3.2 Generalized C-Element Implementation; 6.3.3 Standard C-Implementation; 6.3.4 The Single-Cube Algorithm 6.4 Hazard-Free Decomposition |
| Record Nr. | UNINA-9910143175403321 |
Myers Chris J. <1969->
|
||
| New York, : J. Wiley & Sons, c2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Logically determined design [[electronic resource] ] : clockless system design with NULL convention logic / / Karl M. Fant
| Logically determined design [[electronic resource] ] : clockless system design with NULL convention logic / / Karl M. Fant |
| Autore | Fant Karl M |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley & Sons, 2005 |
| Descrizione fisica | 1 online resource (310 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Asynchronous circuits - Design and construction
Logic, Symbolic and mathematical Logic design Computer architecture |
| ISBN |
1-280-25243-X
9786610252435 0-470-32394-9 0-471-70287-0 0-471-70289-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
LOGICALLY DETERMINED DESIGN; CONTENTS; Preface; Acknowledgments; 1. Trusting Logic; 1.1 Mathematicianless Enlivenment of Logic Expression; 1.2 Emulating the Mathematician; 1.3 Supplementing the Expressivity of Boolean Logic; 1.3.1 The Expressional Insufficiency of Boolean Logic; 1.3.2 Supplementing the Logical Expression; 1.3.3 Coordinating Combinational Expressions; 1.3.4 The Complexity Burden of the Time Interval; 1.3.5 Forms of Supplementation Other Than the Time Interval; 1.3.6 The Complexity Burden of Asynchronous Design; 1.3.7 The Cost of Supplementation
1.4 Defining a Sufficiently Expressive Logic1.4.1 Logically Expressing Data Presentation Boundaries; 1.4.2 Logically Recognizing Data Presentation Boundaries; 1.4.3 Logically Coordinating the Flow of Data; 1.4.4 Mathematicianless Completeness of Expression; 1.5 The Logically Determined System; 1.6 Trusting the Logic: A Methodology of Logical Confidence; 1.7 Summary; 1.8 Exercises; 2. A Sufficiently Expressive Logic; 2.1 Searching for a New Logic; 2.1.1 Expressing Discrete Data Presentation Boundaries; 2.1.2 Logically Recognizing Discrete Data Presentation Boundaries 2.1.3 The Universality of the NULL Function2.1.4 Bounding the Behavior of a Combinational Expression; 2.1.5 Relationship of 4NCL to Boolean Logic; 2.2 Deriving a 3 Value Logic; 2.2.1 Expressing 3NCL State-holding Behavior; 2.2.2 3NCL Summary; 2.3 Deriving a 2 Value Logic; 2.3.1 The Data Differentiation Convention; 2.3.2 2NCL as a Threshold Logic; 2.3.3 2NCL in Relation to Boolean Logic; 2.3.4 Subvariable Expressivity; 2.3.5 Completeness at the Variable Level; 2.3.6 The 2NCL Orphan Path; 2.3.7 2NCL Summary; 2.4 Compromising Logical Completeness 2.4.1 Moving Logically Determined Completeness Boundaries Farther Apart2.4.2 No Logically Determined Boundaries in Data Path; 2.4.3 No Logically Determined Boundaries at All; 2.5 Summary; 3. The Structure of Logically Determined Systems; 3.1 The Cycle; 3.1.1 The Ring Oscillator; 3.1.2 Oscillator Composition with Shared Completeness Path; 3.1.3 Cycles and 2NCL Data Paths; 3.1.4 Data Path Abstraction; 3.1.5 Composition in Terms of Cycles; 3.1.6 Composition in Terms of Registration Stages; 3.2 Basic Pipeline Structures; 3.2.1 Pipeline Fan-out; 3.2.2 Pipeline Fan-in; 3.2.3 The Pipeline Ring 3.2.4 Cycle Structure Example3.3 Control Variables and Wavefront Steering; 3.3.1 Steering Control Variables; 3.3.2 Fan-out Wavefront Steering; 3.3.3 Fan-in Wavefront Steering; 3.3.4 Wavefront Steering Philosophy; 3.3.5 Concurrent Pipelined Function Paths; 3.4 The Logically Determined System; 3.4.1 Managing Wavefront Interaction; 3.4.2 A Simple Example System; 3.5 Initialization; 3.5.1 Initializing the System; 3.5.2 Initializing Data Wavefronts; 3.6 Testing; 3.7 Summary; 3.8 Exercises; 4. 2NCL Combinational Expression; 4.1 Function Classification; 4.1.1 Threshold Function Classification 4.1.2 Boolean Function Classification |
| Record Nr. | UNINA-9910146070003321 |
|
Fant Karl M
|
||
| Hoboken, NJ, : John Wiley & Sons, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Logically determined design : clockless system design with NULL convention logic / / Karl M. Fant
| Logically determined design : clockless system design with NULL convention logic / / Karl M. Fant |
| Autore | Fant Karl M |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley & Sons, 2005 |
| Descrizione fisica | 1 online resource (310 p.) |
| Disciplina | 621.381 |
| Soggetto topico |
Asynchronous circuits - Design and construction
Logic, Symbolic and mathematical Logic design Computer architecture |
| ISBN |
1-280-25243-X
9786610252435 0-470-32394-9 0-471-70287-0 0-471-70289-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
LOGICALLY DETERMINED DESIGN; CONTENTS; Preface; Acknowledgments; 1. Trusting Logic; 1.1 Mathematicianless Enlivenment of Logic Expression; 1.2 Emulating the Mathematician; 1.3 Supplementing the Expressivity of Boolean Logic; 1.3.1 The Expressional Insufficiency of Boolean Logic; 1.3.2 Supplementing the Logical Expression; 1.3.3 Coordinating Combinational Expressions; 1.3.4 The Complexity Burden of the Time Interval; 1.3.5 Forms of Supplementation Other Than the Time Interval; 1.3.6 The Complexity Burden of Asynchronous Design; 1.3.7 The Cost of Supplementation
1.4 Defining a Sufficiently Expressive Logic1.4.1 Logically Expressing Data Presentation Boundaries; 1.4.2 Logically Recognizing Data Presentation Boundaries; 1.4.3 Logically Coordinating the Flow of Data; 1.4.4 Mathematicianless Completeness of Expression; 1.5 The Logically Determined System; 1.6 Trusting the Logic: A Methodology of Logical Confidence; 1.7 Summary; 1.8 Exercises; 2. A Sufficiently Expressive Logic; 2.1 Searching for a New Logic; 2.1.1 Expressing Discrete Data Presentation Boundaries; 2.1.2 Logically Recognizing Discrete Data Presentation Boundaries 2.1.3 The Universality of the NULL Function2.1.4 Bounding the Behavior of a Combinational Expression; 2.1.5 Relationship of 4NCL to Boolean Logic; 2.2 Deriving a 3 Value Logic; 2.2.1 Expressing 3NCL State-holding Behavior; 2.2.2 3NCL Summary; 2.3 Deriving a 2 Value Logic; 2.3.1 The Data Differentiation Convention; 2.3.2 2NCL as a Threshold Logic; 2.3.3 2NCL in Relation to Boolean Logic; 2.3.4 Subvariable Expressivity; 2.3.5 Completeness at the Variable Level; 2.3.6 The 2NCL Orphan Path; 2.3.7 2NCL Summary; 2.4 Compromising Logical Completeness 2.4.1 Moving Logically Determined Completeness Boundaries Farther Apart2.4.2 No Logically Determined Boundaries in Data Path; 2.4.3 No Logically Determined Boundaries at All; 2.5 Summary; 3. The Structure of Logically Determined Systems; 3.1 The Cycle; 3.1.1 The Ring Oscillator; 3.1.2 Oscillator Composition with Shared Completeness Path; 3.1.3 Cycles and 2NCL Data Paths; 3.1.4 Data Path Abstraction; 3.1.5 Composition in Terms of Cycles; 3.1.6 Composition in Terms of Registration Stages; 3.2 Basic Pipeline Structures; 3.2.1 Pipeline Fan-out; 3.2.2 Pipeline Fan-in; 3.2.3 The Pipeline Ring 3.2.4 Cycle Structure Example3.3 Control Variables and Wavefront Steering; 3.3.1 Steering Control Variables; 3.3.2 Fan-out Wavefront Steering; 3.3.3 Fan-in Wavefront Steering; 3.3.4 Wavefront Steering Philosophy; 3.3.5 Concurrent Pipelined Function Paths; 3.4 The Logically Determined System; 3.4.1 Managing Wavefront Interaction; 3.4.2 A Simple Example System; 3.5 Initialization; 3.5.1 Initializing the System; 3.5.2 Initializing Data Wavefronts; 3.6 Testing; 3.7 Summary; 3.8 Exercises; 4. 2NCL Combinational Expression; 4.1 Function Classification; 4.1.1 Threshold Function Classification 4.1.2 Boolean Function Classification |
| Record Nr. | UNINA-9910813378203321 |
|
Fant Karl M
|
||
| Hoboken, NJ, : John Wiley & Sons, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
