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MARC Lista (tabellare)
ARM Assembly Language with Hardware Experiments / / by Ata Elahi, Trevor Arjeski
ARM Assembly Language with Hardware Experiments / / by Ata Elahi, Trevor Arjeski
Autore Elahi Ata
Pubbl/distr/stampa Cham : , : Springer, , [2015]
Descrizione fisica 1 online resource (144 pages) : illustrations
Disciplina 004.6
620
621.3815
621.382
Soggetto topico Assembly languages (Electronic computers)
Microprocessors - Programming
Electronic circuits
Computer communication systems
Electrical engineering
Circuits and Systems
Computer Communication Networks
Communications Engineering, Networks
ISBN 3-319-11704-1
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Number Systems and Data Communication -- Logic Gates and Introduction to Computer Architecture -- ARM Instructions Part I -- ARM Instructions Part II -- ARM Assembly Language Programming Using Keil Development Tools -- ARM Cortex-M3 Processor and MBED NXP LPC1768 -- Lab Experiments.    .
Record Nr. UNINA-9910299671003321
Elahi Ata  
Cham : , : Springer, , [2015]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
The art of Assembly language / / by Randall Hyde
The art of Assembly language / / by Randall Hyde
Autore Hyde Randall
Edizione [2nd ed.]
Pubbl/distr/stampa San Francisco, : No Starch Press, 2010
Descrizione fisica 1 online resource (764 p.)
Disciplina 005.13/6
Soggetto topico Assembly languages (Electronic computers)
Programming languages (Electronic computers)
ISBN 1-59327-301-0
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Contents in Detail; Acknowledgements; Chapter 1: Hello, World of Assembly Language; 1.1: The Anatomy of an HLA Program; 1.2: Running Your First HLA Program; 1.3: Some Basic HLA Data Declarations; 1.4: Boolean Values; 1.5: Character Values; 1.6: An Introduction to the Intel 80x86 CPU Family; 1.7: The Memory Subsystem; 1.8: Some Basic Machine Instructions; 1.9: Some Basic HLA Control Structures; 1.10: Introduction to the HLA Standard Library; 1.11: Additional Details About try..endtry; 1.12: High-Level Assembly Language vs. Low-Level Assembly Language; 1.13: For More Information
Chapter 2: Data Representation2.1: Numbering Systems; 2.2: The Hexadecimal Numbering System; 2.3: Data Organization; 2.4: Arithmetic Operations on Binary and Hexadecimal Numbers; 2.5: A Note About Numbers vs. Representation; 2.6: Logical Operations on Bits; 2.7: Logical Operations on Binary Numbers and Bit Strings; 2.8: Signed and Unsigned Numbers; 2.9: Sign Extension, Zero Extension, Contraction, and Saturation; 2.10: Shifts and Rotates; 2.11: Bit Fields and Packed Data; 2.12: An Introduction to Floating-Point Arithmetic; 2.13: Binary-Coded Decminal Representation; 2.14: Characters
2.15: The Unicode Character Set2.16: For More Information; Chapter 3: Memory Access and Organization; 3.1: The 80x86 Addressing Modes; 3.2: Runtime Memory Organization; 3.3: How HLA Allocates Memory for Variables; 3.4: HLA Support for Data Alignment; 3.5: Address Expressions; 3.6: Type Coercion; 3.7: Register Type Coercion; 3.8: The stack Segment and the push and pop Instructions; 3.9: The Stack Is a LIFO Data Structure; 3.10: Accessing Data You've Pushed onto the Stack Without Popping It; 3.11: Dynamic Memory Allocation and the Heap Segment; 3.12: The inc and dec Instructions
3.13: Obtaining the Address of a Memory Object3.14: For More Information; Chapter 4: Constants, Variables, and Data Types; 4.1: Some Additional Instructions: intmul, bound, into; 4.2: HLA Constant and Value Declarations; 4.3: The HLA Type Section; 4.4: enum and HLA Enumerated Data Types; 4.5: Pointer Data Types; 4.6: Composite Data Types; 4.7: Character Strings; 4.8: HLA Strings; 4.9: Accessing the Characters Within a String; 4.10: The HLA String Module and Other String-Related Routines; 4.11: In-Memory Conversions; 4.12: Character Sets; 4.13: Character Set Implementation in HLA
4.14: HLA Character Set Constants and Character Set Expressions4.15: Character Set Support in the HLA Standard Library; 4.16: Using Character Sets in Your HLA Programs; 4.17: Arrays; 4.18: Declaring Arrays in Your HLA Programs; 4.19: HLA Array Constants; 4.20: Accessing Elements of a Single-Dimensional Array; 4.21: Sorting an Array of Values; 4.22: Multidimensional Arrays; 4.23: Allocating Storage for Multidimensional Arrays; 4.24: Accessing Multidimensional Array Elements in Assembly Language; 4.25: Records; 4.26: Record Constants; 4.27: Arrays of Records
4.28: Arrays/Records as Record Fields
Record Nr. UNINA-9910813047203321
Hyde Randall  
San Francisco, : No Starch Press, 2010
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Assembly language programming : ARM Cortex-M3 / / Vincent Mahout
Assembly language programming : ARM Cortex-M3 / / Vincent Mahout
Autore Mahout Vincent
Edizione [1st ed.]
Pubbl/distr/stampa London, : ISTE Ltd.
Descrizione fisica 1 online resource (258 p.)
Disciplina 005.2
Collana ISTE
Soggetto topico Embedded computer systems
Microprocessors
Assembly languages (Electronic computers)
ISBN 1-118-56212-7
1-299-31584-4
1-118-56597-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Overview of Cortex-M3 architecture -- The core of Cortex-M3 -- The proper use of assembly directives -- Operands of instructions -- Instruction set -- Algorithmic and data structures -- Internal modularity -- managing exceptions -- From listing to executable : external modularity.
Record Nr. UNINA-9910819595603321
Mahout Vincent  
London, : ISTE Ltd.
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
The AVR microcontroller and embedded systems : using Assembly and C. / / Muhammad Ali Mazidi, Sarmad Naimi, Sepehr Naimi
The AVR microcontroller and embedded systems : using Assembly and C. / / Muhammad Ali Mazidi, Sarmad Naimi, Sepehr Naimi
Autore Mazidi Muhammad Ali
Edizione [Pearson new international edition.]
Pubbl/distr/stampa Harlow, England : , : Pearson Education, Limited, , [2014]
Descrizione fisica 1 online resource (744 pages) : illustrations, tables
Disciplina 004.16
Collana Always Learning
Soggetto topico Sistemes incrustats (Informàtica)
Atmel AVR (Microcontrolador)
Assembly languages (Electronic computers)
Embedded computer systems
Atmel AVR microcontroller
ISBN 1-322-83115-7
1-292-05433-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Cover -- Table of Contents -- 1. Introduction to Computing -- 2. The AVR Microcontroller: History and Features -- 3. AVR Architecture and Assembly Language Programming -- 4. Branch, Call, and Time Delay Loop -- 5. AVR I/O Port Programming -- 6. Arithmetic, Logic Instructions, and Programs -- 7. AVR Advanced Assembly Language Programming -- 8. AVR Programming in C -- 9. AVR Hardware Connection, Hex File, and Flash Loaders -- 10. AVR Timer Programming in Assembly and C -- 11. AVR Interrupt Programming in Assembly and C -- 12. AVR Serial Port Programming in Assembly and C -- 13. LCD and Keyboard Interfacing -- 14. ADC, DAC, and Sensor Interfacing -- 15. Relay, Optoisolator, and Stepper Motor Interfacing with AVR -- 16. Input Capture and Wave Generation in AVR -- 17. PWM Programming and DC Motor Control in AVR -- 18. SPI Protocol and MAX7221 Display Interfacing -- 19. I2C Protocol and DS1307 RTC Interfacing -- Appendix: AVR Instructions Explained -- Appendix: Data Sheets -- Index -- 2.
Record Nr. UNINA-9910153068903321
Mazidi Muhammad Ali  
Harlow, England : , : Pearson Education, Limited, , [2014]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Blue fox : arm assembly internals and binary analysis of mobile and IOT devices / / Maria Markstedter
Blue fox : arm assembly internals and binary analysis of mobile and IOT devices / / Maria Markstedter
Autore Markstedter Maria
Pubbl/distr/stampa Hoboken, New Jersey : , : John Wiley & Sons, Ltd, , 2023
Descrizione fisica 1 online resource (xi, 219 pages) : illustrations
Disciplina 005.265
Soggetto topico Assembly languages (Electronic computers)
Internet of Things
Embedded computer systems - Programming
ISBN 1-394-18920-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction -- Part I Arm Assembly Internals -- Chapter 1 Introduction to Reverse Engineering -- Introduction to Assembly -- Bits and Bytes -- Character Encoding -- Machine Code and Assembly -- Assembling -- Cross- Assemblers -- High- Level Languages -- Disassembling -- Decompilation -- Chapter 2 ELF File Format Internals -- Program Structure -- High- Level vs. Low- Level Languages -- The Compilation Process -- Cross- Compiling for Other Architectures -- Assembling and Linking -- The ELF File Overview -- The ELF File Header -- The ELF File Header Information Fields -- The Target Platform Fields -- The Entry Point Field -- The Table Location Fields -- ELF Program Headers -- The PHDR Program Header -- The INTERP Program Header -- The LOAD Program Headers -- The DYNAMIC Program Header -- The NOTE Program Header -- The TLS Program Header -- The GNU_EH_FRAME Program Header -- The GNU_STACK Program Header -- The GNU_RELRO Program Header -- ELF Section Headers -- The ELF Meta- Sections -- The String Table Section -- The Symbol Table Section -- The Main ELF Sections -- The .text Section -- The .data Section -- The .bss Section -- The .rodata Section -- The .tdata and .tbss Sections -- Symbols -- Global vs. Local Symbols -- Weak Symbols -- Symbol Versions -- Mapping Symbols -- The Dynamic Section and Dynamic Loading -- Dependency Loading (NEEDED) -- Program Relocations -- Static Relocations -- Dynamic Relocations -- The Global Offset Table (GOT) -- The Procedure Linkage Table (PLT) -- The ELF Program Initialization and Termination Sections -- Initialization and Termination Order -- Thread- Local Storage -- The Local- Exec TLS Access Model -- The Initial- Exec TLS Access Model -- The General- Dynamic TLS Access Model -- The Local- Dynamic TLS Access Model -- Chapter 3 OS Fundamentals -- OS Architecture Overview -- User Mode vs. Kernel Mode -- Processes -- System Calls -- Objects and Handles -- Threads -- Process Memory Management -- Memory Pages -- Memory Protections -- Anonymous and Memory- Mapped Memory -- Memory- Mapped Files and Modules -- Address Space Layout Randomization -- Stack Implementations -- Shared Memory -- Chapter 4 The Arm Architecture -- Architectures and Profiles -- The Armv8- A Architecture -- Exception Levels -- Armv8- A TrustZone Extension -- Exception Level Changes -- Armv8- A Execution States -- The AArch64 Execution State -- The A64 Instruction Set -- AArch64 Registers -- The Program Counter -- The Stack Pointer -- The Zero Register -- The Link Register -- The Frame Pointer -- The Platform Register (x18) -- The Intraprocedural Call Registers -- SIMD and Floating- Point Registers -- System Registers -- PSTATE -- The AArch32 Execution State -- A32 and T32 Instruction Sets -- The A32 Instruction Set -- The T32 Instruction Set -- Switching Between Instruction Sets -- AArch32 Registers -- The Program Counter -- The Stack Pointer -- The Frame Pointer -- The Link Register -- The Intraprocedural Call Register (IP, r12) -- The Current Program Status Register -- The Application Program Status Register -- The Execution State Registers -- The Instruction Set State Register -- The IT Block State Register (ITSTATE) -- Endianness state -- Mode and Exception Mask Bits -- Chapter 5 Data Processing Instructions -- Shift and Rotate Operations -- Logical Shift Left -- Logical Shift Right -- Arithmetic Shift Right -- Rotate Right -- Rotate Right with Extend -- Instruction Forms -- Shift by a Constant Immediate Form -- Shift by Register Form -- Bitfield Manipulation Operations -- Bitfield Move -- Sign- and Zero- Extend Operations -- Bitfield Extract and Insert -- Logical Operations -- Bitwise AND The TST Instruction -- Bitwise Bit Clear -- Bitwise OR Bitwise OR NOT Bitwise Exclusive OR The TEQ instruction Exclusive OR NOT Arithmetic Operations Addition and Subtraction -- Reverse Subtract -- Compare CMP Instruction Operation Behavior -- Multiplication Operations -- Multiplications on A64 -- Multiplications on A32/T32 -- Least Significant Word Multiplications -- Most Significant Word Multiplications -- Halfword Multiplications -- Vector (Dual) Multiplications -- Long (64- Bit) Multiplications -- Division Operations -- Move Operations -- Move Constant Immediate -- Move Immediate and MOVT on A32/T32 -- Move Immediate, MOVZ, and MOVK on A64 -- Move Register -- Move with NOT -- Chapter 6 Memory Access Instructions -- Instructions Overview -- Addressing Modes and Offset Forms -- Offset Addressing -- Constant Immediate Offset -- Register Offsets -- Pre- Indexed Mode -- Pre- Indexed Mode Example -- Post- Indexed Addressing -- Post- Indexed Addressing Example -- Literal (PC- Relative) Addressing -- Loading Constants -- Loading an Address into a Register -- Load and Store Instructions -- Load and Store Word or Doubleword -- Load and Store Halfword or Byte -- Example Using Load and Store -- Load and Store Multiple (A32) -- Example for STM and LDM -- A More Complicated Example Using STM and LDM -- Load and Store Pair (A64) -- Chapter 7 Conditional Execution -- Conditional Execution Overview -- Conditional Codes -- The NZCV Condition Flags -- Signed vs. Unsigned Integer Overflows -- Condition Codes -- Conditional Instructions -- The If- Then (IT) Instruction in Thumb -- Flag- Setting Instructions -- The Instruction "S" Suffix -- The S Suffix on Add and Subtract Instructions -- The S Suffix on Logical Shift Instructions -- The S Suffix on Multiply Instructions -- The S Suffix on Other Instructions -- Test and Comparison Instructions -- Compare (CMP) -- Compare Negative (CMN) -- Test Bits (TST) -- Test Equality (TEQ) -- Conditional Select Instructions -- Conditional Comparison Instructions -- Boolean AND Conditionals Using CCMP -- Boolean OR Conditionals Using CCMP -- Chapter 8 Control Flow -- Branch Instructions -- Conditional Branches and Loops -- Test and Compare Branches -- Table Branches (T32) -- Branch and Exchange -- Subroutine Branches -- Functions and Subroutines -- The Procedure Call Standard -- Volatile vs. Nonvolatile Registers -- Arguments and Return Values -- Passing Larger Values -- Leaf and Nonleaf Functions -- Leaf Functions -- Nonleaf Functions -- Prologue and Epilogue -- Part II Reverse Engineering -- Chapter 9 Arm Environments -- Arm Boards -- Emulation with QEMU -- QEMU User- Mode Emulation -- QEMU Full- System Emulation -- Firmware Emulation -- Chapter 10 Static Analysis -- Static Analysis Tools -- Command- Line Tools 322 Disassemblers and Decompilers -- Binary Ninja Cloud -- Call- By- Reference Example -- Control Flow Analysis -- Main Function -- Subroutine -- Converting to char if Statement -- Quotient Division for Loop -- Analyzing an Algorithm -- Chapter 11 Dynamic Analysis -- Command- Line Debugging -- GDB Commands -- GDB Multiuser -- GDB Extension: GEF -- Installation -- Interface -- Useful GEF Commands -- Examine Memory -- Watch Memory Regions -- Vulnerability Analyzers -- checksec -- Radare2 -- Debugging -- Remote Debugging -- Radare2 -- IDA Pro -- Debugging a Memory Corruption -- Debugging a Process with GDB -- Chapter 12 Reversing arm64 macOS Malware -- Background -- macOS arm64 Binaries macOS Hello World (arm64) -- Hunting for Malicious arm64 Binaries -- Analyzing arm64 Malware -- Anti- Analysis Techniques -- Anti- Debugging Logic (via ptrace) -- Anti- Debugging Logic (via sysctl) -- Anti- VM Logic (via SIP Status and the Detection of VM Artifacts) -- Conclusion -- Index.
Altri titoli varianti Blue Fox
Record Nr. UNINA-9910829852603321
Markstedter Maria  
Hoboken, New Jersey : , : John Wiley & Sons, Ltd, , 2023
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Computer systems : digital design, fundamentals of computer architecture and assembly language / / Ata Elahi
Computer systems : digital design, fundamentals of computer architecture and assembly language / / Ata Elahi
Autore Elahi Ata
Edizione [Second edition.]
Pubbl/distr/stampa Cham, Switzerland : , : Springer Nature Switzerland AG, , [2022]
Descrizione fisica 1 online resource (307 pages)
Disciplina 005.265
Soggetto topico Assembly languages (Electronic computers)
Computer engineering
Computer architecture
ISBN 9783030934491
9783030934484
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Intro -- Preface -- Intended Audience -- Organization -- Acknowledgments -- Contents -- Chapter 1: Signals and Number Systems -- 1.1 Introduction -- 1.1.1 CPU -- 1.1.1.1 CPU Execute Program -- Input Device -- Output Device -- Memory -- 1.2 Historical Development of the Computer -- 1.3 Hardware and Software Components of a Computer -- 1.4 Types of Computers -- 1.5 Analog Signals -- 1.5.1 Characteristics of an Analog Signal -- 1.6 Digital Signals -- 1.7 Number System -- 1.7.1 Converting from Binary to Decimal -- 1.7.2 Converting from Decimal Integer to Binary -- 1.7.3 Converting Decimal Fraction to Binary -- 1.7.4 Converting from Hex to Binary -- 1.7.5 Binary Addition -- 1.8 Complement and Two´s Complement -- 1.8.1 Subtraction of Unsigned Number Using Two´s Complement -- 1.9 Unsigned, Signed Magnitude, and Signed Two´s Complement Binary Number -- 1.9.1 Unsigned Number -- 1.9.2 Signed Magnitude Number -- 1.9.3 Signed Two´s Complement -- 1.10 Binary Addition Using Signed Two´s Complement -- 1.11 Floating Point Representation -- 1.11.1 Single and Double Precision Representations of Floating Point -- 1.11.1.1 Biased Exponent -- 1.11.1.2 Normalized Mantissa -- 1.11.1.3 Double Precision -- 1.12 Binary-Coded Decimal (BCD) -- 1.13 Coding Schemes -- 1.13.1 ASCII Code -- 1.13.2 Universal Code or Unicode -- 1.14 Parity Bit -- 1.14.1 Even Parity -- 1.14.2 Odd Parity -- 1.15 Clock -- 1.16 Transmission Modes -- 1.16.1 Asynchronous Transmission -- 1.16.2 Synchronous Transmission -- 1.17 Transmission Methods -- 1.17.1 Serial Transmission -- 1.17.2 Parallel Transmission -- 1.18 Summary -- Chapter 2: Boolean Logics and Logic Gates -- 2.1 Introduction -- 2.2 Boolean Logics and Logic Gates -- 2.2.1 AND Logic -- 2.2.2 OR Logic -- 2.2.3 NOT Logic -- 2.2.4 NAND Gate -- 2.2.5 NOR Gate -- 2.2.6 Exclusive OR Gate -- 2.2.7 Exclusive NOR Gate -- 2.2.8 Tri-State Device.
2.2.9 Multiple Inputs Logic Gates -- 2.3 Integrated Circuit (IC) Classifications -- 2.3.1 Small-Scale Integration (SSI) -- 2.3.2 Integrated Circuit Pins Numbering -- 2.3.3 Medium-Scale Integration (MSI) -- 2.3.4 Large-Scale Integration (LSI) -- 2.3.5 Very-Large-Scale Integration (VLSI) -- 2.4 Boolean Algebra Theorems -- 2.4.1 Distributive Theorem -- 2.4.2 De Morgan´s Theorem I -- 2.4.3 De Morgan´s Theorem II -- 2.4.4 Commutative Law -- 2.4.5 Associative Law -- 2.4.6 More Theorems -- 2.5 Boolean Function -- 2.5.1 Complement of a Function -- 2.6 Summary -- Problems -- Chapter 3: Minterms, Maxterms, Karnaugh Map (K-Map), and Universal Gates -- 3.1 Introduction -- 3.2 Minterms -- 3.2.1 Application of Minterms -- 3.2.2 Three-Variable Minterms -- 3.3 Maxterms -- 3.4 Karnaugh Map (K-Map) -- 3.4.1 Three-Variable Map -- 3.4.2 Four-Variable K-Map -- 3.5 Sum of Products (SOP) and Product of Sums (POS) -- 3.6 Don´t Care Conditions -- 3.7 Universal Gates -- 3.7.1 Using NAND Gates -- 3.7.2 Using NOR Gates -- 3.7.3 Implementation of Logic Functions Using NAND Gates or NOR Gates Only -- 3.7.4 Using NAND Gates -- 3.7.5 Using NOR Gates -- 3.8 Summary -- Problems -- Chapter 4: Combinational Logic -- 4.1 Introduction -- 4.2 Analysis of Combinational Logic -- 4.3 Design of Combinational Logic -- 4.3.1 Solution -- 4.4 Decoder -- 4.4.1 Implementing a Function Using a Decoder -- 4.5 Encoder -- 4.6 Multiplexer (MUX) -- 4.6.1 Designing Large Multiplexer Using Smaller Multiplexers -- 4.6.2 Implementing Functions Using Multiplexer -- 4.7 Half Adder, Full Adder, Binary Adder, and Subtractor -- 4.7.1 Full Adder (FA) -- 4.7.2 4-Bit Binary Adder -- 4.7.3 Subtractor -- 4.8 ALU (Arithmetic Logic Unit) -- 4.9 Seven-Segment Display -- 4.10 Summary -- Problems -- Chapter 5: Synchronous Sequential Logic -- 5.1 Introduction -- 5.2 S-R Latch -- 5.2.1 S-R Latch Operation -- 5.3 D Flip-Flop.
5.4 J-K Flip-Flop -- 5.5 T Flip-Flop -- 5.6 Register -- 5.6.1 Shift Register -- 5.6.2 Barrel Shifter -- 5.7 Frequency Divider Using J-K Flip-Flop -- 5.8 Analysis of Sequential Logic -- 5.9 State Diagram -- 5.9.1 D Flip-Flop State Diagram -- 5.10 Flip-Flop Excitation Table -- 5.10.1 D Flip-Flop Excitation Table -- 5.10.2 Excitation Table Operation -- 5.10.3 J-K Flip-Flop Excitation Table -- 5.10.4 T Flip-Flop Excitation Table -- 5.11 Counter -- 5.12 Summary -- Problems -- Chapter 6: Introduction to Computer Architecture -- 6.1 Introduction -- 6.1.1 Abstract Representation of Computer Architecture -- 6.2 Components of a Microcomputer -- 6.2.1 Central Processing Unit (CPU) -- 6.2.1.1 Register Bank -- 6.2.2 CPU Buses -- 6.2.2.1 Address Bus -- 6.2.2.2 Data Bus -- 6.2.2.3 Control Bus -- 6.2.3 Memory -- 6.2.4 Serial Input/Output -- 6.2.5 Direct Memory Access (DMA) -- 6.2.6 Programmable I/O Interrupt -- 6.2.7 32-Bit Versus 64-Bit CPU -- 6.3 CPU Technology -- 6.3.1 CISC (Complex Instruction Set Computer) -- 6.3.2 RISC -- 6.4 CPU Architecture -- 6.4.1 Von Neumann Architecture -- 6.4.2 Harvard Architecture -- 6.5 Intel Microprocessor Family -- 6.5.1 Upward Compatibility -- 6.6 Multicore Processors -- 6.7 CPU Instruction Execution Steps -- 6.7.1 Pipelining -- 6.8 Disk Controller -- 6.9 Microcomputer Bus -- 6.9.1 ISA Bus -- 6.9.2 Microchannel Architecture Bus -- 6.9.3 EISA Bus -- 6.9.4 VESA Bus -- 6.9.5 PCI Bus -- 6.9.6 Universal Serial BUS (USB) -- 6.9.7 USB Architecture -- 6.9.7.1 Host Controller -- 6.9.7.2 Root Hub -- 6.9.7.3 Hub -- 6.9.7.4 USB Cable -- 6.9.7.5 USB Device -- 6.9.8 PCI Express Bus -- 6.9.8.1 PCI Express Architecture -- 6.9.8.2 PCI Express Protocol Architecture -- 6.9.8.3 Software Layer -- 6.9.8.4 PCI Express Physical Layer -- 6.10 FireWire -- 6.10.1 HDMI (High-Definition Multimedia Interface) -- 6.10.1.1 Motherboard -- 6.11 Summary.
Review Questions -- Chapter 7: Memory -- 7.1 Introduction -- 7.2 Memory -- 7.2.1 RAM -- 7.2.2 DRAM Packaging -- 7.2.3 ROM (Read-Only Memory) -- 7.2.4 Memory Access Time -- 7.3 Hard Disk -- 7.3.1 Disk Characteristics -- 7.3.2 Cluster -- 7.3.3 Disk File System -- 7.4 Solid-State Drive (SSD) -- 7.5 Memory Hierarchy -- 7.5.1 Cache Memory -- 7.5.2 Cache Terminology -- 7.5.3 Cache Memory Mapping Methods -- 7.5.4 Direct Mapping -- 7.5.5 Set Associative Mapping -- 7.5.6 Replacement Method -- 7.5.7 Fully Associative Mapping -- 7.5.8 Cache Update Methods -- 7.5.9 Effective Access Time (EAT) of Memory -- 7.5.10 Virtual Memory -- 7.5.10.1 Page Table -- 7.5.11 Memory Organization of a Computer -- 7.5.11.1 Memory Operation -- Questions and Problems -- Problems -- Chapter 8: Assembly Language and ARM Instructions Part I -- 8.1 Introduction -- 8.2 Instruction Set Architecture (ISA) -- 8.2.1 Classification of Instruction Based on Number of Operands -- 8.2.1.1 No Operand Instructions -- 8.2.1.2 One-Operand Instructions -- 8.2.1.3 Two-Operand Instructions -- 8.2.1.4 Three-Operand Instructions -- 8.3 ARM Processor Architecture -- 8.3.1 Instruction Decoder and Logic Control -- 8.3.2 Address Register -- 8.3.3 Address Increment -- 8.3.4 Register Bank -- 8.3.5 Barrel Shifter -- 8.3.6 ALU -- 8.3.7 Write Data Register -- 8.3.8 Read Data Register -- 8.3.9 ARM Operation Mode -- 8.4 ARM Registers -- 8.4.1 Current Program Status Register (CPSR) -- 8.4.2 Flag Bits -- 8.4.3 Control Bits -- 8.5 ARM Instructions -- 8.5.1 Data Processing Instructions -- 8.5.1.1 Registers Operands -- 8.5.1.2 Immediate Operand -- 8.5.2 Compare and Test Instructions -- 8.5.2.1 CMP Instruction (Compare Instruction) -- 8.5.2.2 CMN Compare Negate -- 8.5.2.3 TST (Test Instruction) -- 8.5.3 Register Swap Instructions (MOV and MVN) -- 8.5.4 Shift and Rotate Instructions -- 8.5.4.1 Logical Shift Left (LSL).
8.5.4.2 Logical Shift Right (LSR) -- 8.5.4.3 Arithmetic Shift Right (ASR) -- 8.5.4.4 Rotate Right -- 8.5.5 ARM Unconditional Instructions and Conditional Instructions -- 8.6 Stack Operation and Instructions -- 8.7 Branch (B) and Branch with Link Instruction (BL) -- 8.8 Multiply (MUL) and Multiply-Accumulate (MLA) Instructions -- 8.9 Summary -- Problems and Questions -- Chapter 9: ARM Assembly Language Programming Using Keil Development Tools -- 9.1 Introduction -- 9.2 Keil Development Tools for ARM Assembly -- 9.2.1 Assembling a Program -- 9.2.2 Running the Debugger/Simulator -- 9.3 Program Template -- 9.4 Programming Rules -- 9.4.1 CASE Rules -- 9.4.2 Comments -- 9.5 Data Representation and Memory -- 9.6 Directives -- 9.6.1 Data Directive -- 9.6.1.1 DCB (Define Constant Byte) -- 9.6.1.2 DCW (Define Constant Half Word) -- 9.6.1.3 DCD (Define Constant Word) -- 9.6.1.4 Character Strings -- 9.6.1.5 Single Character -- 9.6.1.6 SPACE -- 9.7 Memory in μVision v5 -- 9.8 Summary -- Questions and Problems -- Chapter 10: ARM Instructions Part II and Instruction Formats -- 10.1 Introduction -- 10.2 ARM Data Transfer Instructions -- 10.2.1 ARM Pseudo Instructions -- 10.2.2 Store Instructions (STR) -- 10.3 ARM Addressing Mode -- 10.3.1 Immediate Addressing -- 10.3.2 Pre-indexed -- 10.3.3 Pre-indexed with Write Back -- 10.3.4 Post-index Addressing -- 10.4 Swap Memory and Register (SWAP) -- 10.5 Storing Data Using Keil μVision 5 -- 10.6 Bits Field Instructions -- 10.7 ARM Instruction Formats -- 10.7.1 ARM Data Processing Instruction Format -- 10.7.1.1 Condition Code -- 10.7.1.2 I bit -- 10.7.1.3 Op Code -- 10.7.2 B and BL Instruction Format -- 10.7.3 Multiply Instruction Format -- 10.7.4 Data Transfer Instructions (LDRB, LDR, STRB, and STR) -- 10.7.5 Data Transfer Half Word and Signed Number (LDRH, STRH, LDRSB, LDRSH) -- 10.7.6 Swap Memory and Register (SWAP).
10.8 Summary.
Record Nr. UNINA-9910553072903321
Elahi Ata  
Cham, Switzerland : , : Springer Nature Switzerland AG, , [2022]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Dragon Machine Language for the Absolute Beginner
Dragon Machine Language for the Absolute Beginner
Autore Reyden John
Pubbl/distr/stampa Luton, Bedfordshire : , : Andrews UK Ltd., , 2022
Descrizione fisica 1 online resource (262 pages)
Disciplina 001.64/24
Collana Retro Reproductions
Soggetto topico Assembly languages (Electronic computers)
Dragon 32 (Computer)
ISBN 1-78982-802-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Cover -- Contents -- Front Matter -- Title Page -- Title, Author, and Publisher -- Publisher Information -- Dragon Machine Language for the Absolute Beginner -- Chapter 1: The Beginning -- Chapter 2: What is a Micro-Computer? -- Chapter 3: Computers and Numbers -- Binary -- Negative Numbers -- Exponential Numbers -- Hexadecimal Numbers -- Binary Coded Decimal -- Decimal-Hexadecimal-Binary-Conversion Program -- Chapter 4: What is Machine Language? -- Chapter 5: What is Assembly Language? -- Chapter 6: The Dragon -- Chapter 7: The 6809 -- Registers -- Modes -- Chapter 8: Easy -- Chapter 9: Handy -- Chapter 10: Let's Get Logical -- Chapter 11: Condition Codes -- Decisions, Decisions -- Loops -- Chapter 12: Stacks and Subroutines -- Chapter 13: The 6809 Instruction Set -- Chapter 14: Demonstration Programs -- Introduction -- A) The No OPeration Instruction -- B) The Complete Byte and Register Handlers -- C) The Arithmetic Instructions -- D) The Logical Instructions -- E) Comparisons -- F) The Branch and Jump Instructions -- G) The Rotate Instructions -- H) The Stack Handling Instructions -- I) The Interrupt Instructions -- Chapter 15: Programming Your Dragon -- Planning Your Machine Language Programs -- Entering and Running Machine Language Programs -- Monitor Program -- Chapter 16: Sample Programs -- Introduction -- The PIA (Peripheral Interface Adaptor) -- Screen Memory -- The Hardware -- The Use of the Direct Page -- Program: PIA Keys -- Program: Score -- Program: Explode -- Program: Music -- Program: Demo -- Back Matter -- Appendices -- Appendix A: Colour Set Table -- Appendix B: Graphics Modes -- Appendix C: Handy Memory Locations in the Dragon -- Appendix D: Handy ROM Routines -- Appendix E: ASCII Codes for Keys -- Appendix F: Character Codes -- Appendix G: Base Conversions -- Appendix H: 6809 Instruction Set Summary -- Also Available.
Record Nr. UNINA-9910795654703321
Reyden John  
Luton, Bedfordshire : , : Andrews UK Ltd., , 2022
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Dragon Machine Language for the Absolute Beginner
Dragon Machine Language for the Absolute Beginner
Autore Reyden John
Pubbl/distr/stampa Luton, Bedfordshire : , : Andrews UK Ltd., , 2022
Descrizione fisica 1 online resource (262 pages)
Disciplina 001.64/24
Collana Retro Reproductions
Soggetto topico Assembly languages (Electronic computers)
Dragon 32 (Computer)
ISBN 1-78982-802-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Cover -- Contents -- Front Matter -- Title Page -- Title, Author, and Publisher -- Publisher Information -- Dragon Machine Language for the Absolute Beginner -- Chapter 1: The Beginning -- Chapter 2: What is a Micro-Computer? -- Chapter 3: Computers and Numbers -- Binary -- Negative Numbers -- Exponential Numbers -- Hexadecimal Numbers -- Binary Coded Decimal -- Decimal-Hexadecimal-Binary-Conversion Program -- Chapter 4: What is Machine Language? -- Chapter 5: What is Assembly Language? -- Chapter 6: The Dragon -- Chapter 7: The 6809 -- Registers -- Modes -- Chapter 8: Easy -- Chapter 9: Handy -- Chapter 10: Let's Get Logical -- Chapter 11: Condition Codes -- Decisions, Decisions -- Loops -- Chapter 12: Stacks and Subroutines -- Chapter 13: The 6809 Instruction Set -- Chapter 14: Demonstration Programs -- Introduction -- A) The No OPeration Instruction -- B) The Complete Byte and Register Handlers -- C) The Arithmetic Instructions -- D) The Logical Instructions -- E) Comparisons -- F) The Branch and Jump Instructions -- G) The Rotate Instructions -- H) The Stack Handling Instructions -- I) The Interrupt Instructions -- Chapter 15: Programming Your Dragon -- Planning Your Machine Language Programs -- Entering and Running Machine Language Programs -- Monitor Program -- Chapter 16: Sample Programs -- Introduction -- The PIA (Peripheral Interface Adaptor) -- Screen Memory -- The Hardware -- The Use of the Direct Page -- Program: PIA Keys -- Program: Score -- Program: Explode -- Program: Music -- Program: Demo -- Back Matter -- Appendices -- Appendix A: Colour Set Table -- Appendix B: Graphics Modes -- Appendix C: Handy Memory Locations in the Dragon -- Appendix D: Handy ROM Routines -- Appendix E: ASCII Codes for Keys -- Appendix F: Character Codes -- Appendix G: Base Conversions -- Appendix H: 6809 Instruction Set Summary -- Also Available.
Record Nr. UNINA-9910823907203321
Reyden John  
Luton, Bedfordshire : , : Andrews UK Ltd., , 2022
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Introduction to 80X86 assembly language and computer architecture / / Richard C. Detmer, Middle Tennessee State University
Introduction to 80X86 assembly language and computer architecture / / Richard C. Detmer, Middle Tennessee State University
Autore Detmer Richard C.
Edizione [Third edition.]
Pubbl/distr/stampa Burlington, Massachusetts : , : Jones & Bartlett Learning, , 2015
Descrizione fisica 1 online resource (406 pages) : illustrations, tables
Disciplina 004.2/2
Soggetto topico Computer architecture
Assembly languages (Electronic computers)
Intel 80x86 series microprocessors
ISBN 1-284-03613-8
1-284-03612-X
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Representing data in a computer -- Parts of a computer system -- Elements of assembly language -- Basic instructions -- Branching and looping -- Procedures -- Bit manipulation -- String operations -- Floating point operations.
Record Nr. UNINA-9910165026503321
Detmer Richard C.  
Burlington, Massachusetts : , : Jones & Bartlett Learning, , 2015
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Learn to program with Assembly : foundational learning for new programmers / / Jonathan Bartlett
Learn to program with Assembly : foundational learning for new programmers / / Jonathan Bartlett
Autore Bartlett Jonathan <1977->
Pubbl/distr/stampa [Place of publication not identified] : , : Apress, , [2021]
Descrizione fisica 1 online resource (324 pages)
Disciplina 005.265
Soggetto topico Assembly languages (Electronic computers)
Computer programming
ISBN 1-4842-7437-7
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Chapter 1: Introduction -- Chapter 2: The Truth About Computers -- Part I: Assembly Language Basics -- Chapter 3: Your First Program -- Chapter 4: Registers and Simple Arithmetic -- Chapter 5: Comparison, Branching and Looping -- Chapter 6: Working with Data in Memory -- Chapter 7: Data Records -- Chapter 8: Signed Numbers and Bitwise Operations -- Chapter 9: More Instructions You Should Know -- Part II: Operating System Basics -- Chapter 10: Making System Calls -- Chapter 11: The Stack and Function Calls -- Chapter 12: Calling Functions from Libraries -- Chapter 13: Common and Useful Assembler Directives -- Chapter 14: Dynamic Memory Allocation -- Chapter 15: Dynamic Linking -- Part III: Programming Language Topics -- Chapter 16: Basic Language Features Represented in Assembly Language -- Chapter 17: Tracking Memory Allocations -- Chapter 18: Object-Oriented Programming -- Chapter 19: Conclusion and Acknowledgments -- Part IV: Appendices -- Appendix A: Getting Set Up with Docker -- Appendix B: The Command Line -- Appendix C: Debugging with GDB -- Appendix D: Nasm (Intel) Assembly Language Syntax -- Appendix E: Common x86-64 Instructions -- Appendix F: Floating Point Numbers -- Appendix G: The Starting State of the Stack -- Appendix H: ASCII, Unicode, and UTF-8 -- Appendix I: Optimization -- Appendix J: A Simplified Garbage Collector -- Appendix K: Going to an Even Lower Level.
Record Nr. UNINA-9910508470203321
Bartlett Jonathan <1977->  
[Place of publication not identified] : , : Apress, , [2021]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui