Edizione	[1st ed. 2007.]
Pubbl/distr/stampa	Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007
Descrizione fisica	1 online resource (XIII, 402 p.)
Disciplina	004
Collana	Theoretical Computer Science and General Issues
Soggetto topico	Computer systems Computer arithmetic and logic units Computer input-output equipment Logic design Computer networks Microprocessors Computer architecture Computer System Implementation Arithmetic and Logic Structures Input/Output and Data Communications Logic Design Computer Communication Networks Processor Architectures
ISBN	1-281-04270-6 9786611042707 3-540-74309-X
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	A Compiler Framework for Supporting Speculative Multicore Processors -- Power-Efficient Heterogeneous Multicore Technology for Digital Convergence -- StarDBT: An Efficient Multi-platform Dynamic Binary Translation System -- Unbiased Branches: An Open Problem -- An Online Profile Guided Optimization Approach for Speculative Parallel Threading -- Entropy-Based Profile Characterization and Classification for Automatic Profile Management -- Laplace Transformation on the FT64 Stream Processor -- Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation -- Evolution of NAND Flash Memory Interface -- FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-core DSPs -- Exploiting Single-Usage for Effective Memory Management -- An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories -- An Effective Design of Master-Slave Operating System Architecture for Multiprocessor Embedded Systems -- Optimal Placement of Frequently Accessed IPs in Mesh NoCs -- An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips -- Performance of Keyword Connection Algorithm in Nested Mobility Networks -- Leakage Energy Reduction in Cache Memory by Software Self-invalidation -- Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters -- Runtime Performance Projection Model for Dynamic Power Management -- A Power-Aware Alternative for the Perceptron Branch Predictor -- Power Consumption and Performance Analysis of 3D NoCs -- A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels -- Bipartition Architecture for Low Power JPEG Huffman Decoder -- A SWP Specification for Sequential Image Processing Algorithms -- A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision -- FPGA-Accelerated Active Shape Model for Real-Time People Tracking -- Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures -- Synchronization Mechanisms on Modern Multi-core Architectures -- Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs -- Generalized Wormhole Switching: A New Fault-Tolerant Mathematical Model for Adaptively Wormhole-Routed Interconnect Networks -- Open Issues in MPI Implementation -- Implicit Transactional Memory in Kilo-Instruction Multiprocessors -- Design of a Low–Power Embedded Processor Architecture Using Asynchronous Function Units -- A Bypass Mechanism to Enhance Branch Predictor for SMT Processors -- Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor -- Architectural Solution to Object-Oriented Programming.
Record Nr.	UNISA-996465487703316

Edizione	[1st ed. 2006.]
Pubbl/distr/stampa	Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006
Descrizione fisica	1 online resource (XIV, 605 p.)
Disciplina	004.2/2
Collana	Theoretical Computer Science and General Issues
Soggetto topico	Computer systems Computer arithmetic and logic units Computer input-output equipment Logic design Computer networks Microprocessors Computer architecture Computer System Implementation Arithmetic and Logic Structures Input/Output and Data Communications Logic Design Computer Communication Networks Processor Architectures
ISBN	3-540-40058-3
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	The Era of Multi-core Chips -A Fresh Look on Software Challenges -- Streaming Networks for Coordinating Data-Parallel Programs (Position Statement) -- Implementations of Square-Root and Exponential Functions for Large FPGAs -- Using Branch Prediction Information for Near-Optimal I-Cache Leakage -- Scientific Computing Applications on the Imagine Stream Processor -- Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination -- A Study of the Performance Potential for Dynamic Instruction Hints Selection -- Reorganizing UNIX for Reliability -- Critical-Task Anticipation Scheduling Algorithm for Heterogeneous and Grid Computing -- Processor Directed Dynamic Page Policy -- Static WCET Analysis Based Compiler-Directed DVS Energy Optimization in Real-Time Applications -- A Study on Transformation of Self-similar Processes with Arbitrary Marginal Distributions -- ?TC – An Intermediate Language for Programming Chip Multiprocessors -- Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays -- Trace-Based Data Cache Leakage Reduction at Link Time -- Parallelizing User-Defined and Implicit Reductions Globally on Multiprocessors -- Overload Protection for Commodity Network Appliances -- An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit -- A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster -- Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor -- Combining Wireless Sensor Network with Grid for Intelligent City Traffic -- A Novel Processor Architecture for Real-Time Control -- A 0-1 Integer Linear Programming Based Approach for Global Locality Optimizations -- Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs -- Entropy Throttling: A Physical Approach for Maximizing Packet Mobility in Interconnection Networks -- Design of an Efficient Flexible Architecture for Color Image Enhancement -- Hypercube Communications on Optical Chordal Ring Networks with Chord Length of Three -- PMPS(3): A Performance Model of Parallel Systems -- Issues and Support for Dynamic Register Allocation -- A Heterogeneous Multi-core Processor Architecture for High Performance Computing -- Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation -- Fault-Free Pairwise Independent Hamiltonian Paths on Faulty Hypercubes -- Constructing Node-Disjoint Paths in Enhanced Pyramid Networks -- Striping Cache: A Global Cache for Striped Network File System -- DTuplesHPC: Distributed Tuple Space for Desktop High Performance Computing -- The Algorithm and Circuit Design of a 400MHz 16-Bit Hybrid Multiplier -- Live Range Aware Cache Architecture -- The Challenges of Efficient Code-Generation for Massively Parallel Architectures -- Reliable Systolic Computing Through Redundancy -- A Diversity-Controllable Genetic Algorithm for Optimal Fused Traffic Planning on Sensor Networks -- A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling -- On the Reliability of Drowsy Instruction Caches -- Design of a Reconfigurable Cryptographic Engine -- Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors -- The New BCD Subtractor and Its Reversible Logic Implementation -- Power-Efficient Microkernel of Embedded Operating System on Chip -- Understanding Prediction Limits Through Unbiased Branches -- Bandwidth Optimization of the EMCI for a High Performance 32-bit DSP -- Research on Petersen Graphs and Hyper-cubes Connected Interconnection Networks -- Cycle Period Analysis and Optimization of Timed Circuits -- Acceleration Techniques for Chip-Multiprocessor Simulator Debug -- A DDL–Based Software Architecture Model -- Branch Behavior Characterization for Multimedia Applications -- Optimization and Evaluating of StreamYGX2 on MASA Stream Processor -- SecureTorrent: A Security Framework for File Swarming -- Register Allocation on Stream Processor with Local Register File -- A Self-reconfigurable System-on-Chip Architecture for Satellite On-Board Computer Maintenance -- Compile-Time Thread Distinguishment Algorithm on VIM-Based Architecture -- Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining -- Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications -- Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols -- An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors -- An Efficient Approach to Energy Saving in Microcontrollers.
Record Nr.	UNISA-996465886003316

Edizione	[1st ed. 2005.]
Pubbl/distr/stampa	Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005
Descrizione fisica	1 online resource (XVIII, 834 p.)
Disciplina	004.2/2
Collana	Theoretical Computer Science and General Issues
Soggetto topico	Computer systems Computer arithmetic and logic units Computer input-output equipment Logic design Computer networks Microprocessors Computer architecture Computer System Implementation Arithmetic and Logic Structures Input/Output and Data Communications Logic Design Computer Communication Networks Processor Architectures
ISBN	3-540-32108-X 3-540-29643-3
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Keynote Address I -- Processor Architecture for Trustworthy Computers -- Session 1A: Energy Efficient and Power Aware Techniques -- Efficient Voltage Scheduling and Energy-Aware Co-synthesis for Real-Time Embedded Systems -- Energy-Effective Instruction Fetch Unit for Wide Issue Processors -- Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty -- An Innovative Instruction Cache for Embedded Processors -- Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) Processor -- Session 1B: Methodologies and Architectures for Application-Specific Systems -- Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution -- A Pipelined Hardware Architecture for Motion Estimation of H.264/AVC -- Embedded Intelligent Imaging On-Board Small Satellites -- Architectural Enhancements for Color Image and Video Processing on Embedded Systems -- A Portable Doppler Device Based on a DSP with High- Performance Spectral Estimation and Output -- Session 2A: Processor Architectures and Microarchitectures -- A Power-Efficient Processor Core for Reactive Embedded Applications -- A Stream Architecture Supporting Multiple Stream Execution Models -- The Challenges of Massive On-Chip Concurrency -- FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit -- Session 2B: High-Reliability and Fault-Tolerant Architectures -- Modularized Redundant Parallel Virtual File System -- Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures -- A Fault-Tolerant Routing Strategy for Fibonacci-Class Cubes -- Embedding of Cycles in the Faulty Hypercube -- Session 3A: Compiler and OS for Emerging Architectures -- Improving the Performance of GCC by Exploiting IA-64 Architectural Features -- An Integrated Partitioning and Scheduling Based Branch Decoupling -- A Register Allocation Framework for Banked Register Files with Access Constraints -- Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems -- Irregular Redistribution Scheduling by Partitioning Messages -- Session 3B: Data Value Predictions -- Making Power-Efficient Data Value Predictions -- Speculative Issue Logic -- Using Decision Trees to Improve Program-Based and Profile-Based Static Branch Prediction -- Arithmetic Data Value Speculation -- Exploiting Thread-Level Speculative Parallelism with Software Value Prediction -- Keynote Address II -- Challenges and Opportunities on Multi-core Microprocessor -- Session 4A: Reconfigurable Computing Systems and Polymorphic Architectures -- Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures -- A Switch Wrapper Design for SNA On-Chip-Network -- A Configuration System Architecture Supporting Bit-Stream Compression for FPGAs -- Biological Sequence Analysis with Hidden Markov Models on an FPGA -- FPGAs for Improved Energy Efficiency in Processor Based Systems -- Morphable Structures for Reconfigurable Instruction Set Processors -- Session 4B: Interconnect Networks and Network Interfaces -- Implementation of a Hybrid TCP/IP Offload Engine Prototype -- Matrix-Star Graphs: A New Interconnection Network Based on Matrix Operations -- The Channel Assignment Algorithm on RP(k) Networks -- Extending Address Space of IP Networks with Hierarchical Addressing -- The Star-Pyramid Graph: An Attractive Alternative to the Pyramid -- Building a Terabit Router with XD Networks -- Session 5A: Parallel Architectures and Computation Models -- A Real Coded Genetic Algorithm for Data Partitioning and Scheduling in Networks with Arbitrary Processor Release Time -- D3DPR: A Direct3D-Based Large-Scale Display Parallel Rendering System Architecture for Clusters -- Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures -- A Technique to Reduce Preemption Overhead in Real-Time Multiprocessor Task Scheduling -- Session 5B: Hardware-Software Partitioning, Verification, and Testing of Complex Architectures -- Minimizing Power in Hardware/Software Partitioning -- Exploring Design Space Using Transaction Level Models -- Increasing Embedding Probabilities of RPRPs in RIN Based BIST -- A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture -- Session 6A: Architectures for Secured Computing -- DRIL– A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding Techniques -- Efficient Architectural Support for Secure Bus-Based Shared Memory Multiprocessor -- Covert Channel Analysis of the Password-Capability System -- Session 6B: Simulation and Performance Evaluation -- Comparing Low-Level Behavior of SPEC CPU and Java Workloads -- Application of Real-Time Object-Oriented Modeling Technique for Real-Time Computer Control -- VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers -- Session 7: Architectures for Emerging Technologies and Applications I -- Analysis of Real-Time Communication System with Queuing Priority -- FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks -- A Study on the Performance Evaluation of Forward Link in CDMA Mobile Communication Systems -- Session 8: Memory Systems Hierarchy and Management -- Cache Leakage Management for Multi-programming Workloads -- A Memory Bandwidth Effective Cache Store Miss Policy -- Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance -- Targeted Data Prefetching -- Session 9: Architectures for Emerging Technologies and Applications II -- Area-Time Efficient Systolic Architecture for the DCT -- Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform -- A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures -- Implementation and Analysis of TCP/IP Offload Engine and RDMA Transfer Mechanisms on an Embedded System.
Record Nr.	UNISA-996466223603316

Edizione	[1st ed. 2004.]
Pubbl/distr/stampa	Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2004
Descrizione fisica	1 online resource (XVIII, 602 p.)
Disciplina	004.2/2
Collana	Lecture Notes in Computer Science
Soggetto topico	Architecture, Computer Arithmetic and logic units, Computer Input-output equipment (Computers) Microprocessors Computer communication systems Computer System Implementation Arithmetic and Logic Structures Input/Output and Data Communications Register-Transfer-Level Implementation Computer Communication Networks Processor Architectures
ISBN	3-540-30102-X
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Keynote Address I -- Some Real Observations on Virtual Machines -- Session 1A: Cache and Memory -- Replica Victim Caching to Improve Reliability of In-Cache Replication -- Efficient Victim Mechanism on Sector Cache Organization -- Cache Behavior Analysis of a Compiler-Assisted Cache Replacement Policy -- Modeling the Cache Behavior of Codes with Arbitrary Data-Dependent Conditional Structures -- Session 1B: Reconfigurable and Embedded Architectures -- A Configurable System-on-Chip Architecture for Embedded Devices -- An Auto-adaptative Reconfigurable Architecture for the Control -- Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory -- Heuristic Algorithm for Reducing Mapping Sets of Hardware-Software Partitioning in Reconfigurable System -- Session 2A: Processor Architecture and Design I -- Architecture Design of a High-Performance 32-Bit Fixed-Point DSP -- TengYue-1: A High Performance Embedded SoC -- A Fault-Tolerant Single-Chip Multiprocessor -- Session 2B: Power and Energy Management -- Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy -- dDVS: An Efficient Dynamic Voltage Scaling Algorithm Based on the Differential of CPU Utilization -- High Performance Microprocessor Design Methods Exploiting Information Locality and Data Redundancy for Lower Area Cost and Power Consumption -- Session 3A: Processor Architecture and Design II -- Dynamic Reallocation of Functional Units in Superscalar Processors -- Multiple-Dimension Scalable Adaptive Stream Architecture -- Impact of Register-Cache Bandwidth Variation on Processor Performance -- Session 3B: Compiler and Operating System Issues -- Exploiting Free Execution Slots on EPIC Processors for Efficient and Accurate Runtime Profiling -- Continuous Adaptive Object-Code Re-optimization Framework -- Initial Evaluation of a User-Level Device Driver Framework -- Keynote Address II -- A Generation Ahead of Microprocessor: Where Software Can Drive uArchitecture To? -- Session 4A: Application-Specific Systems -- A Cost-Effective Supersampling for Full Scene AntiAliasing -- A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2 m ) -- Scalable Design Framework for JPEG2000 System Architecture -- Real-Time Three Dimensional Vision -- Session 4B: Interconnection Networks -- A Router Architecture for QoS Capable Clusters -- Optimal Scheduling Algorithms in WDM Optical Interconnects with Limited Range Wavelength Conversion Capability -- Comparative Evaluation of Adaptive and Deterministic Routing in the OTIS-Hypercube -- A Two-Level On-Chip Bus System Based on Multiplexers -- Keynote Address III -- Make Computers Cheaper and Simpler -- Session 5A: Prediction Techniques -- A Low Power Branch Predictor to Selectively Access the BTB -- Static Techniques to Improve Power Efficiency of Branch Predictors -- Choice Predictor for Free -- Performance Impact of Different Data Value Predictors -- Session 5B: Parallel Architecture and Programming -- Heterogeneous Networks of Workstations -- Finding High Performance Solution in Reconfigurable Mesh-Connected VLSI Arrays -- Order Independent Transparency for Image Composition Parallel Rendering Machines -- An Authorization Architecture Oriented to Engineering and Scientific Computation in Grid Environments -- Session 6A: Microarchitecture Design and Evaluations -- Validating Word-Oriented Processors for Bit and Multi-word Operations -- Dynamic Fetch Engine for Simultaneous Multithreaded Processors -- A Novel Rename Register Architecture and Performance Analysis -- Session 6B: Memory and I/O Systems -- A New Hierarchy Cache Scheme Using RAM and Pagefile -- An Object-Oriented Data Storage System on Network-Attached Object Devices -- A Scalable and Adaptive Directory Scheme for Hardware Distributed Shared Memory -- Session 7A: Potpourri -- A Compiler-Assisted On-Chip Assigned-Signature Control Flow Checking -- A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in Parallel -- Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization.
Record Nr.	UNINA-9910144151503321

Edizione	[1st ed. 2003.]
Pubbl/distr/stampa	Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2003
Descrizione fisica	1 online resource (XIV, 410 p.)
Disciplina	004.2/2
Collana	Lecture Notes in Computer Science
Soggetto topico	Architecture, Computer Logic design Arithmetic and logic units, Computer Input-output equipment (Computers) Microprocessors Computer communication systems Computer System Implementation Logic Design Arithmetic and Logic Structures Input/Output and Data Communications Processor Architectures Computer Communication Networks
ISBN	3-540-39864-3
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	How Can the Earth Simulator Impact on Human Activities -- Toward Architecting and Designing Novel Computers -- Designing Ultra-large Instruction Issue Windows -- Multi-threaded Microprocessors – Evolution or Revolution -- The Development of System Software for Parallel Supercomputers -- Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA -- Reconfigurable Logic: A Saviour for Experimental Computer Architecture Research -- Design and Implementation of Java Processors -- MOOSS: CPU Architecture with Memory Protection and Support for OOP -- Reducing Access Count to Register-Files through Operand Reuse -- SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator -- Towards an Asynchronous MIPS Processor -- On Implementing High Level Concurrency in Java -- Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures -- A Novel Architecture for Genomic Sequence Searching and Alignment -- A Reconfigurable Multi-threaded Architecture Model -- Reconfigurable Instruction-Level Parallel Processor Architecture -- Mapping Applications to a Coarse Grain Reconfigurable System -- Packing with Boundary Constraints for a Reconfigurable Operating System -- Arithmetic Circuits Combining Residue and Signed-Digit Representations -- A New On-the-fly Summation Algorithm -- State Reordering for Low Power Combinational Logic -- User-Level Management of Kernel Memory -- Variable Radix Page Table: A Page Table for Modern Architectures -- L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy -- Legba: Fast Hardware Support for Fine-Grained Protection -- Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem -- Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor -- Performance of the Achilles Router -- Latency Improvement in Virtual Multicasting -- A Router Architecture to Achieve Link Rate Throughput in Suburban Ad-hoc Networks.
Record Nr.	UNINA-9910144047403321