top

  Info

  • Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.

  Info

  • Utilizzare questo link per rimuovere la selezione effettuata.

Biblioteca

MARC Lista (tabellare)
ESD : analog circuits and design / / Steven H Voldman
ESD : analog circuits and design / / Steven H Voldman
Autore Voldman Steven H.
Edizione [1st edition]
Pubbl/distr/stampa Chichester, England : , : Wiley, , 2015
Descrizione fisica 1 online resource (292 p.)
Disciplina 621.3815/3
Collana ESD Series
Soggetto topico Semiconductors - Protection
Analog integrated circuits - Protection
Analog integrated circuits - Design and construction
Electrostatics
Static eliminators
ISBN 1-118-70147-X
1-118-70140-2
1-118-70168-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto ESD: Analog Circuits and Design; Copyright; Contents; About the Author; Preface; Acknowledgments; Chapter 1 Analog, ESD, and EOS; 1.1 ESD in Analog Design; 1.2 Analog Design Discipline and ESD Circuit Techniques; 1.2.1 Analog Design: Local Matching; 1.2.2 Analog Design: Global Matching; 1.2.3 Symmetry; 1.2.3.1 Layout Symmetry; 1.2.3.2 Thermal Symmetry; 1.2.4 Analog Design: Across Chip Linewidth Variation; 1.3 Design Symmetry and ESD; 1.4 ESD Design Synthesis and Architecture Flow; 1.5 ESD Design and Noise; 1.6 ESD Design Concepts: Adjacency; 1.7 Electrical Overstress
1.7.1 Electrical Overcurrent 1.7.2 Electrical Overvoltage; 1.7.3 Electrical Overstress Events; 1.7.3.1 Characteristic Time Response; 1.7.4 Comparison of EOS versus ESD Waveforms; 1.8 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.8.1 The Shrinking Reliability Design Box; 1.8.2 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.9 Safe Operating Area; 1.9.1 Electrical Safe Operating Area; 1.9.2 Thermal Safe Operating Area (T-SOA); 1.9.3 Transient Safe Operating Area; 1.10 Closing Comments and Summary; References; Chapter 2 Analog Design Layout
2.1 Analog Design Layout Revisited 2.1.1 Analog Design: Local Matching; 2.1.2 Analog Design: Global Matching; 2.1.3 Symmetry; 2.1.4 Layout Design Symmetry; 2.1.5 Thermal Symmetry; 2.2 Common Centroid Design; 2.2.1 Common Centroid Arrays; 2.2.2 One-Axis Common Centroid Design; 2.2.3 Two-Axis Common Centroid Design; 2.3 Interdigitation Design; 2.4 Common Centroid and Interdigitation Design; 2.5 Passive Element Design; 2.6 Resistor Element Design; 2.6.1 Resistor Element Design: Dogbone Layout; 2.6.2 Resistor Design: Analog Interdigitated Layout; 2.6.3 Dummy Resistor Layout
2.6.4 Thermoelectric Cancellation Layout 2.6.5 Electrostatic Shield; 2.6.6 Interdigitated Resistors and ESD Parasitics; 2.7 Capacitor Element Design; 2.8 Inductor Element Design; 2.9 Diode Design; 2.10 MOSFET Design; 2.11 Bipolar Transistor Design; 2.12 Closing Comments and Summary; References; Chapter 3 3 Analog Design Circuits; 3.1 Analog Circuits; 3.2 Single-Ended Receivers; 3.2.1 Single-Ended Receivers; 3.2.2 Schmitt Trigger Receivers; 3.3 Differential Receivers; 3.4 Comparators; 3.5 Current Sources; 3.6 Current Mirrors; 3.6.1 Widlar Current Mirror; 3.6.2 Wilson Current Mirror
3.7 Voltage Regulators 3.7.1 Buck Converters; 3.7.2 Boost Converters; 3.7.3 Buck-Boost Converters; 3.7.4 Cuk Converters; 3.8 Voltage Reference Circuits; 3.8.1 Brokaw Bandgap Voltage Reference; 3.9 Converters; 3.9.1 Analog-to-Digital Converter; 3.9.2 Digital-to-Analog Converters; 3.10 Oscillators; 3.11 Phase Lock Loop; 3.12 Delay Locked Loop; 3.13 Closing Comments and Summary; References; Chapter 4 Analog ESD Circuits; 4.1 Analog ESD Devices and Circuits; 4.2 ESD Diodes; 4.2.1 Dual Diode and Series Diodes; 4.2.2 Dual Diode-Resistor; 4.2.3 Dual Diode-Resistor-Dual Diode
4.2.4 Dual Diode-Resistor-Grounded-Gate MOSFET
Record Nr. UNINA-9910132172303321
Voldman Steven H.  
Chichester, England : , : Wiley, , 2015
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
ESD : analog circuits and design / / Steven H Voldman
ESD : analog circuits and design / / Steven H Voldman
Autore Voldman Steven H.
Edizione [1st edition]
Pubbl/distr/stampa Chichester, England : , : Wiley, , 2015
Descrizione fisica 1 online resource (292 p.)
Disciplina 621.3815/3
Collana ESD Series
Soggetto topico Semiconductors - Protection
Analog integrated circuits - Protection
Analog integrated circuits - Design and construction
Electrostatics
Static eliminators
ISBN 1-118-70147-X
1-118-70140-2
1-118-70168-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto ESD: Analog Circuits and Design; Copyright; Contents; About the Author; Preface; Acknowledgments; Chapter 1 Analog, ESD, and EOS; 1.1 ESD in Analog Design; 1.2 Analog Design Discipline and ESD Circuit Techniques; 1.2.1 Analog Design: Local Matching; 1.2.2 Analog Design: Global Matching; 1.2.3 Symmetry; 1.2.3.1 Layout Symmetry; 1.2.3.2 Thermal Symmetry; 1.2.4 Analog Design: Across Chip Linewidth Variation; 1.3 Design Symmetry and ESD; 1.4 ESD Design Synthesis and Architecture Flow; 1.5 ESD Design and Noise; 1.6 ESD Design Concepts: Adjacency; 1.7 Electrical Overstress
1.7.1 Electrical Overcurrent 1.7.2 Electrical Overvoltage; 1.7.3 Electrical Overstress Events; 1.7.3.1 Characteristic Time Response; 1.7.4 Comparison of EOS versus ESD Waveforms; 1.8 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.8.1 The Shrinking Reliability Design Box; 1.8.2 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.9 Safe Operating Area; 1.9.1 Electrical Safe Operating Area; 1.9.2 Thermal Safe Operating Area (T-SOA); 1.9.3 Transient Safe Operating Area; 1.10 Closing Comments and Summary; References; Chapter 2 Analog Design Layout
2.1 Analog Design Layout Revisited 2.1.1 Analog Design: Local Matching; 2.1.2 Analog Design: Global Matching; 2.1.3 Symmetry; 2.1.4 Layout Design Symmetry; 2.1.5 Thermal Symmetry; 2.2 Common Centroid Design; 2.2.1 Common Centroid Arrays; 2.2.2 One-Axis Common Centroid Design; 2.2.3 Two-Axis Common Centroid Design; 2.3 Interdigitation Design; 2.4 Common Centroid and Interdigitation Design; 2.5 Passive Element Design; 2.6 Resistor Element Design; 2.6.1 Resistor Element Design: Dogbone Layout; 2.6.2 Resistor Design: Analog Interdigitated Layout; 2.6.3 Dummy Resistor Layout
2.6.4 Thermoelectric Cancellation Layout 2.6.5 Electrostatic Shield; 2.6.6 Interdigitated Resistors and ESD Parasitics; 2.7 Capacitor Element Design; 2.8 Inductor Element Design; 2.9 Diode Design; 2.10 MOSFET Design; 2.11 Bipolar Transistor Design; 2.12 Closing Comments and Summary; References; Chapter 3 3 Analog Design Circuits; 3.1 Analog Circuits; 3.2 Single-Ended Receivers; 3.2.1 Single-Ended Receivers; 3.2.2 Schmitt Trigger Receivers; 3.3 Differential Receivers; 3.4 Comparators; 3.5 Current Sources; 3.6 Current Mirrors; 3.6.1 Widlar Current Mirror; 3.6.2 Wilson Current Mirror
3.7 Voltage Regulators 3.7.1 Buck Converters; 3.7.2 Boost Converters; 3.7.3 Buck-Boost Converters; 3.7.4 Cuk Converters; 3.8 Voltage Reference Circuits; 3.8.1 Brokaw Bandgap Voltage Reference; 3.9 Converters; 3.9.1 Analog-to-Digital Converter; 3.9.2 Digital-to-Analog Converters; 3.10 Oscillators; 3.11 Phase Lock Loop; 3.12 Delay Locked Loop; 3.13 Closing Comments and Summary; References; Chapter 4 Analog ESD Circuits; 4.1 Analog ESD Devices and Circuits; 4.2 ESD Diodes; 4.2.1 Dual Diode and Series Diodes; 4.2.2 Dual Diode-Resistor; 4.2.3 Dual Diode-Resistor-Dual Diode
4.2.4 Dual Diode-Resistor-Grounded-Gate MOSFET
Record Nr. UNINA-9910807232603321
Voldman Steven H.  
Chichester, England : , : Wiley, , 2015
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui