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Analog circuit design . Volume 3 : the design note collection / / edited by Bob Dobkin and John Hamburger
| Analog circuit design . Volume 3 : the design note collection / / edited by Bob Dobkin and John Hamburger |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Waltham, Massachusetts ; ; Oxford, England : , : Newnes, , 2015 |
| Descrizione fisica | 1 online resource (1145 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Linear integrated circuits - Design and construction
Analog integrated circuits - Design and construction |
| ISBN | 0-12-800466-5 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Half Title; Analog Circuit Design Volume 2 ; Copyright; Dedication 1; Dedication 2; Contents; Publisher's Note; Trademarks; Acknowledgments; Introduction; Foreword; PART 1 : Power Management; Section 1 : Power Management Design ; 1 High performance single phase DC/DC controller with power system management; Introduction; 1.8V/30A single phase digital power supply with IIN sense; Input current sensing; Inductor DCR autocalibration; LTpowerPlay GUI; Conclusion; 2 One device replaces battery charger, pushbutton controller, LED driver and voltage regulator ICs in portable electronics
Introduction Pushbutton control; Battery, USB, wall and high voltage input sources; Battery charger; Three bucks, two LDOs and a boost/LED driver; Conclusion; 3 Simple circuit replaces and improves on power modules at less than half the price; Introduction; 100W isolated synchronous forward converter in an eighth brick footprint; This circuit is flexible; Conclusion; 4 Wide input range, high efficiency DDR termination power supply achieves fast transient response; Introduction; Overview of the LTC3717; Design example; Conclusion 5 Minimize input capacitors in multioutput, high current power suppliesIntroduction; Design details; Conclusion; 6 Dual phase high efficiency mobile CPU power supply minimizes size and thermal stress; Introduction; Design example; Conclusion; 7 SOT-23 SMBus fan speed controller extends battery life and reduces noise; Introduction; Boost-start timer, thermal shutdown and overcurrent clamp features; Conclusion; 8 Active voltage positioning reduces output capacitors; Introduction; Basic principle; Basic implementation; Current mode control example-LTC1736; 9 5V to 3.3V circuit collection High efficiency 3.3V regulator3.3V battery-powered supply with shutdown; 3.3V supply with shutdown; LT1585 linear regulator optimized for desktop Pentium processor applications; LTC1148 5V to 3.38V Pentium power solution 3.5A output current; LTC1266 switching regulator converts 5V to 3.38V at 7A for Pentium and other high speed μPs; 10 Hex level shift shrinks board space; Section 2 : Microprocessor Power Design; 11 Cost-effective, low profile, high efficiency 42A supply powers AMD Hammer processors; Introduction; Design example; Conclusion 12 Efficient, compact 2-phase power supply delivers 40A to Intel mobile CPUsIntroduction; Smaller inductors, simplified thermal management; 40A Intel IMVP-III voltage regulator; Conclusion; 13 Microprocessor core supply voltage set by I2C bus without VID lines; Introduction; How it works; Why use an SMBus?; Desktop/portable VID DC/DC converter; 14 High efficiency I/O power generation for mobile Pentium III microprocessors; 15 PolyPhase surface mount power supply meets AMD Athlon processor requirements with no heat sink; Introduction; PolyPhase architecture 16 2-step voltage regulation improves performance and decreases CPU temperature in portable computers |
| Record Nr. | UNINA-9910787117403321 |
| Waltham, Massachusetts ; ; Oxford, England : , : Newnes, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Analog circuit design . Volume 3 : the design note collection / / edited by Bob Dobkin and John Hamburger
| Analog circuit design . Volume 3 : the design note collection / / edited by Bob Dobkin and John Hamburger |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Waltham, Massachusetts ; ; Oxford, England : , : Newnes, , 2015 |
| Descrizione fisica | 1 online resource (1145 p.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Linear integrated circuits - Design and construction
Analog integrated circuits - Design and construction |
| ISBN | 0-12-800466-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Half Title; Analog Circuit Design Volume 2 ; Copyright; Dedication 1; Dedication 2; Contents; Publisher's Note; Trademarks; Acknowledgments; Introduction; Foreword; PART 1 : Power Management; Section 1 : Power Management Design ; 1 High performance single phase DC/DC controller with power system management; Introduction; 1.8V/30A single phase digital power supply with IIN sense; Input current sensing; Inductor DCR autocalibration; LTpowerPlay GUI; Conclusion; 2 One device replaces battery charger, pushbutton controller, LED driver and voltage regulator ICs in portable electronics
Introduction Pushbutton control; Battery, USB, wall and high voltage input sources; Battery charger; Three bucks, two LDOs and a boost/LED driver; Conclusion; 3 Simple circuit replaces and improves on power modules at less than half the price; Introduction; 100W isolated synchronous forward converter in an eighth brick footprint; This circuit is flexible; Conclusion; 4 Wide input range, high efficiency DDR termination power supply achieves fast transient response; Introduction; Overview of the LTC3717; Design example; Conclusion 5 Minimize input capacitors in multioutput, high current power suppliesIntroduction; Design details; Conclusion; 6 Dual phase high efficiency mobile CPU power supply minimizes size and thermal stress; Introduction; Design example; Conclusion; 7 SOT-23 SMBus fan speed controller extends battery life and reduces noise; Introduction; Boost-start timer, thermal shutdown and overcurrent clamp features; Conclusion; 8 Active voltage positioning reduces output capacitors; Introduction; Basic principle; Basic implementation; Current mode control example-LTC1736; 9 5V to 3.3V circuit collection High efficiency 3.3V regulator3.3V battery-powered supply with shutdown; 3.3V supply with shutdown; LT1585 linear regulator optimized for desktop Pentium processor applications; LTC1148 5V to 3.38V Pentium power solution 3.5A output current; LTC1266 switching regulator converts 5V to 3.38V at 7A for Pentium and other high speed μPs; 10 Hex level shift shrinks board space; Section 2 : Microprocessor Power Design; 11 Cost-effective, low profile, high efficiency 42A supply powers AMD Hammer processors; Introduction; Design example; Conclusion 12 Efficient, compact 2-phase power supply delivers 40A to Intel mobile CPUsIntroduction; Smaller inductors, simplified thermal management; 40A Intel IMVP-III voltage regulator; Conclusion; 13 Microprocessor core supply voltage set by I2C bus without VID lines; Introduction; How it works; Why use an SMBus?; Desktop/portable VID DC/DC converter; 14 High efficiency I/O power generation for mobile Pentium III microprocessors; 15 PolyPhase surface mount power supply meets AMD Athlon processor requirements with no heat sink; Introduction; PolyPhase architecture 16 2-step voltage regulation improves performance and decreases CPU temperature in portable computers |
| Record Nr. | UNINA-9910810318903321 |
| Waltham, Massachusetts ; ; Oxford, England : , : Newnes, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Analog circuits for machine learning, current/voltage/temperature sensors, and high-speed communication : advances in analog circuit design 2021 / / Pieter Harpe, Kofi A. A. Makinwa and Andrea Baschirotto, editors
| Analog circuits for machine learning, current/voltage/temperature sensors, and high-speed communication : advances in analog circuit design 2021 / / Pieter Harpe, Kofi A. A. Makinwa and Andrea Baschirotto, editors |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2022] |
| Descrizione fisica | 1 online resource (351 pages) |
| Disciplina | 006.31 |
| Soggetto topico |
Machine learning
Analog integrated circuits Analog integrated circuits - Design and construction |
| ISBN | 3-030-91741-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- The Topics Covered Before in this Series -- Contents -- Part I Analog Circuits for Machine Learning -- 1 Mixed-Signal Compute and Memory Fabrics for Deep Neural Networks -- 1 Introduction -- 2 Efficiency Limits of Digital DNN Accelerators -- 3 Analog and Mixed-Signal Computing -- 4 In-Memory Computing -- 5 Discussion and Conclusions -- References -- 2 Analog Computation with RRAM and Supporting Circuits -- 1 Introduction -- 2 Analog Crossbar Computation -- 3 Challenges of Crossbar Operation -- 3.1 Device Nonlinearity -- 3.2 Mixed-Signal Peripheral Circuitry -- 4 Non-volatile Crossbar Synapses -- 4.1 Flash -- 4.2 Filamentary Resistive-RAM -- 5 Digital RRAM Crossbar -- 5.1 Analog Operation with Digital RRAM Cells -- 6 Analog RRAM Crossbar -- 6.1 Analog Operation with Analog RRAM Cells -- 6.2 Fully Integrated CMOS-RRAM Analog Crossbar -- 6.2.1 RRAM Programming -- 6.2.2 RRAM Nonlinearity -- 6.2.3 CMOS Prototype -- 6.2.4 Measurement Setup -- 6.2.5 Single-Layer Perceptron Example -- 6.2.6 System Performance -- 7 Conclusions -- References -- 3 Analog In-Memory Computing with SOT-MRAM: Architecture and Circuit Challenges -- 1 Introduction -- 2 Resistive Element Array -- 3 SOT MRAM Memory Element -- 4 SOT MRAM-Based Cell for AiMC -- 5 MVM Result in SOT Array -- 6 Impact of LSB Size on ADC Design -- 6.1 LSB Shrinking on CS SAR DAC -- 6.2 LSB Shrinking on CS SAR Comparator -- 7 Conclusions -- References -- 4 Prospects for Analog Circuits in Deep Networks -- 1 Introduction -- 2 Review of Circuits for Analog Computing -- 3 Analog Circuits for Matrix-Vector Multiplication -- 4 Non-volatile Resistive Crossbars -- 5 Future of Analog Deep Neural Network Architectures -- 5.1 Trends in Machine Learning ASICs -- 6 Conclusion -- References -- 5 SPIRIT: A First Mixed-Signal SNN Using Co-integrated CMOS Neurons and Resistive Synapses.
1 Introduction -- 2 NVM Technology -- 3 Neural Network Architecture -- 3.1 Building a SNN -- 3.2 Learning Strategy -- 4 Circuit Architecture -- 4.1 Synapse Implementation -- 4.2 Neuron Design -- 4.3 Top Architecture -- 5 Measurement Results -- 5.1 Circuit Validation -- 5.2 Extra Measurements on OxRAMs -- 6 Discussion -- 7 Conclusion -- References -- 6 Accelerated Analog Neuromorphic Computing -- 1 Introduction -- 2 Overview of the bss Neuromorphic Architecture -- 3 The hicannx Chip -- 3.1 Event-Routing Within hicannx -- 3.2 Analog Inference: Rate-Based Extension of hicannx -- 4 Analog Verification of Complex Neuron Circuits -- 4.1 Interfacing Analog Simulations from Python -- 4.2 Monte Carlo Calibration of adex Neuron Circuits -- 5 Conclusion -- Author Contribution -- References -- Part II Current, Voltage, and Temperature Sensors -- 7 Advancements in Current Sensing for Future Automotive Applications -- 1 Introduction -- 2 Current Sensing -- 2.1 Classical Current Sensing -- 2.2 Improvement of Classical Current Sensing -- 2.3 From Linear to Switched Concepts -- 2.4 Current Sensing Goes Digital -- 2.5 Impact to Future Designs -- 3 Conclusions -- References -- 8 Next Generation Current Sense Interfaces for the IoT Era -- 1 Introduction -- 2 Sensing Interfaces for IoT -- 2.1 Current Sensing -- 2.2 Capacitive Sensing -- 2.3 Inductive Sensing -- 2.4 Resistive Sensing -- 3 Multi-sense Interfaces -- 4 Choosing a Current Sensing ADC -- 4.1 Two-Step ADCs -- 4.2 Current Mode Incremental ADC (CI-ADC) -- 5 Incremental Δ Design Considerations -- 5.1 Choosing Both Coarse and Fine ADC Order -- 5.2 Understanding Noise -- 5.3 Incremental Δ Linearity with Passive Integrators -- 5.4 Capacitor Sizing -- 5.5 Decimation Filter -- 6 Multi-Sense with a CI-ADC -- 6.1 Current Sensing with a CI-ADC -- 6.2 Capacitive Sensing with a CI-ADC -- 6.3 Inductive Sensing with a CI-ADC. 6.4 Resistive Sensing with a CI-ADC -- 7 Measurement Results -- 7.1 Optical Proximity Results -- 7.2 Capacitance Sensing Results -- 7.3 Inductive Sensing Results -- 7.4 Resistance Sensing -- 8 Conclusions -- References -- 9 Precision Voltage Sensing in Deep Sub-micron and Its Challenges -- 1 ADC Overview -- 1.1 Sampling -- 1.2 Quantisation -- 1.3 Other Noise Sources -- 1.3.1 Aperture Error -- 1.3.2 Thermal Noise -- 1.4 ADC Signal to Noise -- 1.5 Figure of Merits -- 1.5.1 Walden FoM -- 1.5.2 Schreier FoM -- 1.6 Architecture Comparison -- 1.7 Architecture Selection -- 2 SAR ADC Architecture -- 3 Noise-Shaped SAR ADC -- 4 Error Feedback Design Example -- 5 Dynamic Amplifier -- 6 Conclusion -- References -- 10 Breaking Unusual Barriers in Sensor Interfaces: From Minimum Energy to Ultimate Low Cost -- 1 Introduction -- 2 Ultra-Low Power All-Dynamic Multimodal Sensor Interface -- 2.1 Proposed All-Dynamic Versatile Sensing Platform -- 2.2 Low Power All-Dynamic Temperature Sensing -- 2.3 All-Dynamic Capacitance Sensor Interface -- 2.4 All-Dynamic 4-Terminal Resistance Sensor Interface -- 2.5 SAR ADC -- 2.6 Measurement Results -- 3 Ultimate Low-Cost Electronics -- 4 A Printed Smart Temperature Sensor for Cold Chain Monitoring Applications -- 4.1 System Architecture -- 4.2 Circuit Implementation -- 4.3 Measurement Results -- 5 Conclusions -- References -- 11 Thermal Sensor and Reference Circuits Based on a Time-Controlled Bias of pn-Junctions in FinFET Technology -- 1 Introduction -- 2 Basic Principles -- 2.1 Bulk Diode Properties -- 2.2 Capacitive Bias of PN-Junctions -- 2.3 Forward-Bias Through Negative Charge-Pump -- 3 Application to a Switch-Cap Reverse Bandgap Reference -- 4 An Untrimmed Thermal Sensor Using Bulk Diodes for Sensing -- 4.1 Pulse-Controlled Sensor Principle -- 4.2 Circuit Realization with C-DAC -- 4.3 Simulation and Measurement Results. 5 Conclusions -- References -- 12 Resistor-Based Temperature Sensors -- 1 Introduction -- 2 Theoretical Energy Efficiency of Different Sensors -- 2.1 Temperature Sensors and Resolution FoM -- 2.2 BJT Sensor and Theoretical FoM -- 2.3 Resistor Sensor and Theoretical FoM -- 2.4 Effect of Readout Circuits -- 3 Resistor Choice and Sensor Topologies -- 3.1 Sensing Resistor Choice -- 3.2 Reference Choice -- 3.3 Dual-R Sensor Examples -- 3.4 RC Sensor Examples -- 4 An Energy-Efficient WhB Sensor Design -- 4.1 Front-End Design -- 4.2 Readout Circuit Design -- 4.3 Measurement Results -- 5 Summary -- References -- Part III High-speed Communication -- 13 Recent Advances in Fractional-N Frequency Synthesis -- 1 Introduction -- 2 Noise and Fractional-N Spurs -- 3 Divider Controller Spurs -- 4 Loop Nonlinearities -- 4.1 Loop Filter and Controlled Oscillator -- 4.2 Frequency Divider -- 4.3 Time Difference Measurement -- 5 Interaction Between the Divider Controller and Loop Nonlinearities -- 6 Spur Mitigation Strategies -- 7 All-Digital Phase Locked Loops -- 8 Conclusion -- References -- 14 ADC/DSP-Based Receivers for High-Speed Serial Links -- 1 Introduction -- 2 ADC Resolution Requirements and Topologies -- 3 Digital Equalization -- 4 A 52 Gb/s ADC-Based PAM-4 Receiver with Comparator-Assisted 2 Bit/Stage SAR ADC and Partially Unrolled DFE -- 4.1 Receiver Architecture -- 4.2 ADC Design -- 4.3 DSP Design -- 4.4 Measurement Results -- 5 Conclusion -- References -- 15 ADC-Based SerDes Receiver for 112 Gb/s PAM4 Wireline Communication -- 1 Introduction -- 2 ADC-Based Receiver Architecture -- 2.1 Peak to Main Cursor Ratio (PMR) -- 2.2 Distributed Equalization -- 3 112 Gb/s 16 nm Silicon Implementation -- 3.1 Receiver -- 3.2 Clocking -- 3.3 Measurement Results -- 4 Conclusions -- References. 16 BiCMOS-Integrated Circuits for Millimeter-Wave Wireless Backhaul Transmitters -- 1 Introduction -- 2 Reconfigurable Multi-core Voltage Controlled Oscillator -- 2.1 Multi-Core VCO Overview -- 2.2 Effect of Components Mismatch -- 2.3 VCO Measurement Results -- 3 Frequency Tripler with High Harmonics Suppression -- 3.1 Tripler Operating Principle -- 3.2 Tripler Design and Measurements -- 4 Wideband I/Q LO Generation with Self-tuned Polyphase Filter -- 4.1 I/Q LO Generation Architecture and Circuits Design -- 4.2 I/Q LO Measurement Results -- 5 E-Band Common-Base PAs Leveraging Current-Clamping -- 5.1 Principle of Current-Clamping -- 5.2 PAs Design and Measurements -- 6 Conclusions -- References -- 17 Optical Communication in CMOS-Bringing New Opportunities to an Established Platform -- 1 Introduction -- 2 Schottky Photodiodes in Bulk CMOS -- 2.1 Electrical Characterization -- 2.2 Optical Characterization -- 3 Integrated Receivers Without Equalization -- 4 Integrated Receivers with Equalization -- 5 CMOS 1310/1550nm Receiver Chip Implementations -- 5.1 Receivers Without Equalization -- 5.2 Receiver with Embedded IIR DFE -- 6 Conclusions -- References -- 18 Coherent Silicon Photonic Links -- 1 Introduction -- 2 Coherent Transceiver Operation -- 2.1 Transmitter -- 2.2 Receiver -- 3 High-Swing Linear Driver -- 4 Measurement Results -- 5 Conclusions -- References -- Index. |
| Record Nr. | UNINA-9910556885403321 |
| Cham, Switzerland : , : Springer, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD : analog circuits and design / / Steven H Voldman
| ESD : analog circuits and design / / Steven H Voldman |
| Autore | Voldman Steven H. |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Chichester, England : , : Wiley, , 2015 |
| Descrizione fisica | 1 online resource (292 p.) |
| Disciplina | 621.3815/3 |
| Collana | ESD Series |
| Soggetto topico |
Semiconductors - Protection
Analog integrated circuits - Protection Analog integrated circuits - Design and construction Electrostatics Static eliminators |
| ISBN |
1-118-70147-X
1-118-70140-2 1-118-70168-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD: Analog Circuits and Design; Copyright; Contents; About the Author; Preface; Acknowledgments; Chapter 1 Analog, ESD, and EOS; 1.1 ESD in Analog Design; 1.2 Analog Design Discipline and ESD Circuit Techniques; 1.2.1 Analog Design: Local Matching; 1.2.2 Analog Design: Global Matching; 1.2.3 Symmetry; 1.2.3.1 Layout Symmetry; 1.2.3.2 Thermal Symmetry; 1.2.4 Analog Design: Across Chip Linewidth Variation; 1.3 Design Symmetry and ESD; 1.4 ESD Design Synthesis and Architecture Flow; 1.5 ESD Design and Noise; 1.6 ESD Design Concepts: Adjacency; 1.7 Electrical Overstress
1.7.1 Electrical Overcurrent 1.7.2 Electrical Overvoltage; 1.7.3 Electrical Overstress Events; 1.7.3.1 Characteristic Time Response; 1.7.4 Comparison of EOS versus ESD Waveforms; 1.8 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.8.1 The Shrinking Reliability Design Box; 1.8.2 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.9 Safe Operating Area; 1.9.1 Electrical Safe Operating Area; 1.9.2 Thermal Safe Operating Area (T-SOA); 1.9.3 Transient Safe Operating Area; 1.10 Closing Comments and Summary; References; Chapter 2 Analog Design Layout 2.1 Analog Design Layout Revisited 2.1.1 Analog Design: Local Matching; 2.1.2 Analog Design: Global Matching; 2.1.3 Symmetry; 2.1.4 Layout Design Symmetry; 2.1.5 Thermal Symmetry; 2.2 Common Centroid Design; 2.2.1 Common Centroid Arrays; 2.2.2 One-Axis Common Centroid Design; 2.2.3 Two-Axis Common Centroid Design; 2.3 Interdigitation Design; 2.4 Common Centroid and Interdigitation Design; 2.5 Passive Element Design; 2.6 Resistor Element Design; 2.6.1 Resistor Element Design: Dogbone Layout; 2.6.2 Resistor Design: Analog Interdigitated Layout; 2.6.3 Dummy Resistor Layout 2.6.4 Thermoelectric Cancellation Layout 2.6.5 Electrostatic Shield; 2.6.6 Interdigitated Resistors and ESD Parasitics; 2.7 Capacitor Element Design; 2.8 Inductor Element Design; 2.9 Diode Design; 2.10 MOSFET Design; 2.11 Bipolar Transistor Design; 2.12 Closing Comments and Summary; References; Chapter 3 3 Analog Design Circuits; 3.1 Analog Circuits; 3.2 Single-Ended Receivers; 3.2.1 Single-Ended Receivers; 3.2.2 Schmitt Trigger Receivers; 3.3 Differential Receivers; 3.4 Comparators; 3.5 Current Sources; 3.6 Current Mirrors; 3.6.1 Widlar Current Mirror; 3.6.2 Wilson Current Mirror 3.7 Voltage Regulators 3.7.1 Buck Converters; 3.7.2 Boost Converters; 3.7.3 Buck-Boost Converters; 3.7.4 Cuk Converters; 3.8 Voltage Reference Circuits; 3.8.1 Brokaw Bandgap Voltage Reference; 3.9 Converters; 3.9.1 Analog-to-Digital Converter; 3.9.2 Digital-to-Analog Converters; 3.10 Oscillators; 3.11 Phase Lock Loop; 3.12 Delay Locked Loop; 3.13 Closing Comments and Summary; References; Chapter 4 Analog ESD Circuits; 4.1 Analog ESD Devices and Circuits; 4.2 ESD Diodes; 4.2.1 Dual Diode and Series Diodes; 4.2.2 Dual Diode-Resistor; 4.2.3 Dual Diode-Resistor-Dual Diode 4.2.4 Dual Diode-Resistor-Grounded-Gate MOSFET |
| Record Nr. | UNINA-9910132172303321 |
Voldman Steven H.
|
||
| Chichester, England : , : Wiley, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
ESD : analog circuits and design / / Steven H Voldman
| ESD : analog circuits and design / / Steven H Voldman |
| Autore | Voldman Steven H. |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Chichester, England : , : Wiley, , 2015 |
| Descrizione fisica | 1 online resource (292 p.) |
| Disciplina | 621.3815/3 |
| Collana | ESD Series |
| Soggetto topico |
Semiconductors - Protection
Analog integrated circuits - Protection Analog integrated circuits - Design and construction Electrostatics Static eliminators |
| ISBN |
1-118-70147-X
1-118-70140-2 1-118-70168-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ESD: Analog Circuits and Design; Copyright; Contents; About the Author; Preface; Acknowledgments; Chapter 1 Analog, ESD, and EOS; 1.1 ESD in Analog Design; 1.2 Analog Design Discipline and ESD Circuit Techniques; 1.2.1 Analog Design: Local Matching; 1.2.2 Analog Design: Global Matching; 1.2.3 Symmetry; 1.2.3.1 Layout Symmetry; 1.2.3.2 Thermal Symmetry; 1.2.4 Analog Design: Across Chip Linewidth Variation; 1.3 Design Symmetry and ESD; 1.4 ESD Design Synthesis and Architecture Flow; 1.5 ESD Design and Noise; 1.6 ESD Design Concepts: Adjacency; 1.7 Electrical Overstress
1.7.1 Electrical Overcurrent 1.7.2 Electrical Overvoltage; 1.7.3 Electrical Overstress Events; 1.7.3.1 Characteristic Time Response; 1.7.4 Comparison of EOS versus ESD Waveforms; 1.8 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.8.1 The Shrinking Reliability Design Box; 1.8.2 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.9 Safe Operating Area; 1.9.1 Electrical Safe Operating Area; 1.9.2 Thermal Safe Operating Area (T-SOA); 1.9.3 Transient Safe Operating Area; 1.10 Closing Comments and Summary; References; Chapter 2 Analog Design Layout 2.1 Analog Design Layout Revisited 2.1.1 Analog Design: Local Matching; 2.1.2 Analog Design: Global Matching; 2.1.3 Symmetry; 2.1.4 Layout Design Symmetry; 2.1.5 Thermal Symmetry; 2.2 Common Centroid Design; 2.2.1 Common Centroid Arrays; 2.2.2 One-Axis Common Centroid Design; 2.2.3 Two-Axis Common Centroid Design; 2.3 Interdigitation Design; 2.4 Common Centroid and Interdigitation Design; 2.5 Passive Element Design; 2.6 Resistor Element Design; 2.6.1 Resistor Element Design: Dogbone Layout; 2.6.2 Resistor Design: Analog Interdigitated Layout; 2.6.3 Dummy Resistor Layout 2.6.4 Thermoelectric Cancellation Layout 2.6.5 Electrostatic Shield; 2.6.6 Interdigitated Resistors and ESD Parasitics; 2.7 Capacitor Element Design; 2.8 Inductor Element Design; 2.9 Diode Design; 2.10 MOSFET Design; 2.11 Bipolar Transistor Design; 2.12 Closing Comments and Summary; References; Chapter 3 3 Analog Design Circuits; 3.1 Analog Circuits; 3.2 Single-Ended Receivers; 3.2.1 Single-Ended Receivers; 3.2.2 Schmitt Trigger Receivers; 3.3 Differential Receivers; 3.4 Comparators; 3.5 Current Sources; 3.6 Current Mirrors; 3.6.1 Widlar Current Mirror; 3.6.2 Wilson Current Mirror 3.7 Voltage Regulators 3.7.1 Buck Converters; 3.7.2 Boost Converters; 3.7.3 Buck-Boost Converters; 3.7.4 Cuk Converters; 3.8 Voltage Reference Circuits; 3.8.1 Brokaw Bandgap Voltage Reference; 3.9 Converters; 3.9.1 Analog-to-Digital Converter; 3.9.2 Digital-to-Analog Converters; 3.10 Oscillators; 3.11 Phase Lock Loop; 3.12 Delay Locked Loop; 3.13 Closing Comments and Summary; References; Chapter 4 Analog ESD Circuits; 4.1 Analog ESD Devices and Circuits; 4.2 ESD Diodes; 4.2.1 Dual Diode and Series Diodes; 4.2.2 Dual Diode-Resistor; 4.2.3 Dual Diode-Resistor-Dual Diode 4.2.4 Dual Diode-Resistor-Grounded-Gate MOSFET |
| Record Nr. | UNINA-9910807232603321 |
|
Voldman Steven H.
|
||
| Chichester, England : , : Wiley, , 2015 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
