top

  Info

  • Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.

  Info

  • Utilizzare questo link per rimuovere la selezione effettuata.

Biblioteca

MARC Lista (tabellare)
Advanced graphics programming using openGL [[electronic resource] /] / Tom McReynolds, David Blythe
Advanced graphics programming using openGL [[electronic resource] /] / Tom McReynolds, David Blythe
Autore McReynolds Tom
Edizione [1st edition]
Pubbl/distr/stampa San Francisco, CA, : Elsevier Morgan Kaufmann Publishers, c2005
Descrizione fisica 1 online resource (673 p.)
Disciplina 006.6
006.693
Altri autori (Persone) BlytheDavid <1961->
Collana The Morgan Kaufmann series in computer graphics and geometric modeling
Soggetto topico Computer graphics
Soggetto genere / forma Electronic books.
ISBN 1-281-01007-3
9786611010072
0-08-047572-8
1-4237-0807-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; Advanced Graphics Programming Using OpenGL; Copyright Page; Contents; Preface; Acknowledgments; Biographies; Part I: Concepts; Chapter 1. Geometry Representation and Modeling; 1.1 Polygonal Representation; 1.2 Decomposition and Tessellation; 1.3 Shading Normals; 1.4 Triangle Stripping; 1.5 Vertices and Vertex Arrays; 1.6 Modeling vs. Rendering Revisited; Chapter 2. 3D Transformations; 2.1 Data Representation; 2.2 Overview of the Transformation Pipeline; 2.3 Normal Transformation; 2.4 Texture Coordinate Generation and Transformation; 2.5 Modeling Transforms
2.6 Visualizing Transform Sequences2.7 Projection Transform; 2.8 The Z Coordinate and Perspective Projection; 2.9 Vertex Programs; 2.10 Summary; Chapter 3. Color, Shading, and Lighting; 3.1 Representing Color; 3.2 Shading; 3.3 Lighting; 3.4 Fixed-Point and Floating-Point Arithmetic; 3.5 Summary; Chapter 4.Digital Images and Image Manipulation; 4.1 Image Representation; 4.2 Digital Filtering; 4.3 Convolution; 4.4 Images in OpenGL; 4.5 Positioning Images; 4.6 Pixel Store Operations; 4.7 Pixel Transfer Operations; 4.8 ARB Imaging Subset; 4.9 Off-Screen Processing; 4.10 Summary
Chapter 5. Texture Mapping5.1 Loading Texture Images; 5.2 Texture Coordinates; 5.3 Loading Texture Images from the Frame Buffer; 5.4 Environment Mapping; 5.5 3D Texture; 5.6 Filtering; 5.7 Additional Control of Texture Level of Detail; 5.8 Texture Objects; 5.9 Multitexture; 5.10 Texture Environment; 5.11 Summary; Chapter 6. Rasterization and Fragment Processing; 6.1 Rasterization; 6.2 Fragment Operations; 6.3 Framebuffer Operations; 6.4 Summary; Chapter 7. Window System and Platform Integration; 7.1 Renderer and Window State; 7.2 Address Space and Threads; 7.3 Anatomy of a Window
7.4 Off-Screen Rendering7.5 Rendering to Texture Maps; 7.6 Direct and Indirect Rendering; Chapter 8. OpenGL Implementations; 8.1 OpenGL Versions; 8.2 OpenGL Extensions; 8.3 OpenGL ES for Embedded Systems; 8.4 OpenGL Pipeline Evolution; 8.5 Hardware Implementations of the Pipeline; 8.6 The Future; Part II: Basic Techniques; Chapter 9. Multiple Rendering Passes; 9.1 Invariance; 9.2 Multipass Overview; 9.3 The Multipass Toolbox; 9.4 Multipass Limitations; 9.5 Multipass vs. Micropass; 9.6 Deferred Shading; 9.7 Summary; Chapter 10. Antialiasing; 10.1 Full-Scene Antialiasing; 10.2 Supersampling
10.3 Area Sampling10.4 Line and Point Antialiasing; 10.5 Antialiasing with Textures; 10.6 Polygon Antialiasing; 10.7 Temporal Antialiasing; 10.8 Summary; Chapter 11. Compositing, Blending, and Transparency; 11.1 Combining Two Images; 11.2 Other Compositing Operators; 11.3 Keying and Matting; 11.4 Blending Artifacts; 11.5 Compositing Images with Depth; 11.6 Other Blending Operations; 11.7 Dissolves; 11.8 Transparency; 11.9 Alpha-Blended Transparency; 11.10 Screen-Door Transparency; 11.11 Summary; Chapter 12. Image Processing Techniques; 12.1 OpenGL Imaging Support; 12.2 Image Storage
12.3 Point Operations
Record Nr. UNINA-9910449751503321
McReynolds Tom  
San Francisco, CA, : Elsevier Morgan Kaufmann Publishers, c2005
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Advanced graphics programming using openGL [[electronic resource] /] / Tom McReynolds, David Blythe
Advanced graphics programming using openGL [[electronic resource] /] / Tom McReynolds, David Blythe
Autore McReynolds Tom
Edizione [1st edition]
Pubbl/distr/stampa San Francisco, CA, : Elsevier Morgan Kaufmann Publishers, c2005
Descrizione fisica 1 online resource (673 p.)
Disciplina 006.6
006.693
Altri autori (Persone) BlytheDavid <1961->
Collana The Morgan Kaufmann series in computer graphics and geometric modeling
Soggetto topico Computer graphics
ISBN 1-281-01007-3
9786611010072
0-08-047572-8
1-4237-0807-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; Advanced Graphics Programming Using OpenGL; Copyright Page; Contents; Preface; Acknowledgments; Biographies; Part I: Concepts; Chapter 1. Geometry Representation and Modeling; 1.1 Polygonal Representation; 1.2 Decomposition and Tessellation; 1.3 Shading Normals; 1.4 Triangle Stripping; 1.5 Vertices and Vertex Arrays; 1.6 Modeling vs. Rendering Revisited; Chapter 2. 3D Transformations; 2.1 Data Representation; 2.2 Overview of the Transformation Pipeline; 2.3 Normal Transformation; 2.4 Texture Coordinate Generation and Transformation; 2.5 Modeling Transforms
2.6 Visualizing Transform Sequences2.7 Projection Transform; 2.8 The Z Coordinate and Perspective Projection; 2.9 Vertex Programs; 2.10 Summary; Chapter 3. Color, Shading, and Lighting; 3.1 Representing Color; 3.2 Shading; 3.3 Lighting; 3.4 Fixed-Point and Floating-Point Arithmetic; 3.5 Summary; Chapter 4.Digital Images and Image Manipulation; 4.1 Image Representation; 4.2 Digital Filtering; 4.3 Convolution; 4.4 Images in OpenGL; 4.5 Positioning Images; 4.6 Pixel Store Operations; 4.7 Pixel Transfer Operations; 4.8 ARB Imaging Subset; 4.9 Off-Screen Processing; 4.10 Summary
Chapter 5. Texture Mapping5.1 Loading Texture Images; 5.2 Texture Coordinates; 5.3 Loading Texture Images from the Frame Buffer; 5.4 Environment Mapping; 5.5 3D Texture; 5.6 Filtering; 5.7 Additional Control of Texture Level of Detail; 5.8 Texture Objects; 5.9 Multitexture; 5.10 Texture Environment; 5.11 Summary; Chapter 6. Rasterization and Fragment Processing; 6.1 Rasterization; 6.2 Fragment Operations; 6.3 Framebuffer Operations; 6.4 Summary; Chapter 7. Window System and Platform Integration; 7.1 Renderer and Window State; 7.2 Address Space and Threads; 7.3 Anatomy of a Window
7.4 Off-Screen Rendering7.5 Rendering to Texture Maps; 7.6 Direct and Indirect Rendering; Chapter 8. OpenGL Implementations; 8.1 OpenGL Versions; 8.2 OpenGL Extensions; 8.3 OpenGL ES for Embedded Systems; 8.4 OpenGL Pipeline Evolution; 8.5 Hardware Implementations of the Pipeline; 8.6 The Future; Part II: Basic Techniques; Chapter 9. Multiple Rendering Passes; 9.1 Invariance; 9.2 Multipass Overview; 9.3 The Multipass Toolbox; 9.4 Multipass Limitations; 9.5 Multipass vs. Micropass; 9.6 Deferred Shading; 9.7 Summary; Chapter 10. Antialiasing; 10.1 Full-Scene Antialiasing; 10.2 Supersampling
10.3 Area Sampling10.4 Line and Point Antialiasing; 10.5 Antialiasing with Textures; 10.6 Polygon Antialiasing; 10.7 Temporal Antialiasing; 10.8 Summary; Chapter 11. Compositing, Blending, and Transparency; 11.1 Combining Two Images; 11.2 Other Compositing Operators; 11.3 Keying and Matting; 11.4 Blending Artifacts; 11.5 Compositing Images with Depth; 11.6 Other Blending Operations; 11.7 Dissolves; 11.8 Transparency; 11.9 Alpha-Blended Transparency; 11.10 Screen-Door Transparency; 11.11 Summary; Chapter 12. Image Processing Techniques; 12.1 OpenGL Imaging Support; 12.2 Image Storage
12.3 Point Operations
Record Nr. UNINA-9910783457903321
McReynolds Tom  
San Francisco, CA, : Elsevier Morgan Kaufmann Publishers, c2005
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Advanced graphics programming using openGL [[electronic resource] /] / Tom McReynolds, David Blythe
Advanced graphics programming using openGL [[electronic resource] /] / Tom McReynolds, David Blythe
Autore McReynolds Tom
Edizione [1st edition]
Pubbl/distr/stampa San Francisco, CA, : Elsevier Morgan Kaufmann Publishers, c2005
Descrizione fisica 1 online resource (673 p.)
Disciplina 006.6
006.693
Altri autori (Persone) BlytheDavid <1961->
Collana The Morgan Kaufmann series in computer graphics and geometric modeling
Soggetto topico Computer graphics
ISBN 1-281-01007-3
9786611010072
0-08-047572-8
1-4237-0807-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; Advanced Graphics Programming Using OpenGL; Copyright Page; Contents; Preface; Acknowledgments; Biographies; Part I: Concepts; Chapter 1. Geometry Representation and Modeling; 1.1 Polygonal Representation; 1.2 Decomposition and Tessellation; 1.3 Shading Normals; 1.4 Triangle Stripping; 1.5 Vertices and Vertex Arrays; 1.6 Modeling vs. Rendering Revisited; Chapter 2. 3D Transformations; 2.1 Data Representation; 2.2 Overview of the Transformation Pipeline; 2.3 Normal Transformation; 2.4 Texture Coordinate Generation and Transformation; 2.5 Modeling Transforms
2.6 Visualizing Transform Sequences2.7 Projection Transform; 2.8 The Z Coordinate and Perspective Projection; 2.9 Vertex Programs; 2.10 Summary; Chapter 3. Color, Shading, and Lighting; 3.1 Representing Color; 3.2 Shading; 3.3 Lighting; 3.4 Fixed-Point and Floating-Point Arithmetic; 3.5 Summary; Chapter 4.Digital Images and Image Manipulation; 4.1 Image Representation; 4.2 Digital Filtering; 4.3 Convolution; 4.4 Images in OpenGL; 4.5 Positioning Images; 4.6 Pixel Store Operations; 4.7 Pixel Transfer Operations; 4.8 ARB Imaging Subset; 4.9 Off-Screen Processing; 4.10 Summary
Chapter 5. Texture Mapping5.1 Loading Texture Images; 5.2 Texture Coordinates; 5.3 Loading Texture Images from the Frame Buffer; 5.4 Environment Mapping; 5.5 3D Texture; 5.6 Filtering; 5.7 Additional Control of Texture Level of Detail; 5.8 Texture Objects; 5.9 Multitexture; 5.10 Texture Environment; 5.11 Summary; Chapter 6. Rasterization and Fragment Processing; 6.1 Rasterization; 6.2 Fragment Operations; 6.3 Framebuffer Operations; 6.4 Summary; Chapter 7. Window System and Platform Integration; 7.1 Renderer and Window State; 7.2 Address Space and Threads; 7.3 Anatomy of a Window
7.4 Off-Screen Rendering7.5 Rendering to Texture Maps; 7.6 Direct and Indirect Rendering; Chapter 8. OpenGL Implementations; 8.1 OpenGL Versions; 8.2 OpenGL Extensions; 8.3 OpenGL ES for Embedded Systems; 8.4 OpenGL Pipeline Evolution; 8.5 Hardware Implementations of the Pipeline; 8.6 The Future; Part II: Basic Techniques; Chapter 9. Multiple Rendering Passes; 9.1 Invariance; 9.2 Multipass Overview; 9.3 The Multipass Toolbox; 9.4 Multipass Limitations; 9.5 Multipass vs. Micropass; 9.6 Deferred Shading; 9.7 Summary; Chapter 10. Antialiasing; 10.1 Full-Scene Antialiasing; 10.2 Supersampling
10.3 Area Sampling10.4 Line and Point Antialiasing; 10.5 Antialiasing with Textures; 10.6 Polygon Antialiasing; 10.7 Temporal Antialiasing; 10.8 Summary; Chapter 11. Compositing, Blending, and Transparency; 11.1 Combining Two Images; 11.2 Other Compositing Operators; 11.3 Keying and Matting; 11.4 Blending Artifacts; 11.5 Compositing Images with Depth; 11.6 Other Blending Operations; 11.7 Dissolves; 11.8 Transparency; 11.9 Alpha-Blended Transparency; 11.10 Screen-Door Transparency; 11.11 Summary; Chapter 12. Image Processing Techniques; 12.1 OpenGL Imaging Support; 12.2 Image Storage
12.3 Point Operations
Record Nr. UNINA-9910817207803321
McReynolds Tom  
San Francisco, CA, : Elsevier Morgan Kaufmann Publishers, c2005
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Networks on chips [[electronic resource] ] : technology and tools / / Luca Benini and Giovanni De Micheli
Networks on chips [[electronic resource] ] : technology and tools / / Luca Benini and Giovanni De Micheli
Autore Benini Luca <1967->
Edizione [1st edition]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006
Descrizione fisica 1 online resource (408 p.)
Disciplina 621.3815
Altri autori (Persone) De MicheliGiovanni
Collana The Morgan Kaufmann series in systems on silicon
Soggetto topico Systems on a chip
Computer networks - Equipment and supplies
Soggetto genere / forma Electronic books.
ISBN 1-280-96683-1
9786610966837
0-08-047356-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; Title page; Copyright Page; Table of contents; About The Authors; List of Contributors; 1 Networks on Chip; 1.1 Why On-Chip Networking?; 1.2 Technology Trends; 1.3 SoC Objectives and NoC Needs; 1.4 Once Over Lightly; 1.5 Perspectives; 2 Network Architecture: Principles and Examples; 2.1 Network Architecture; 2.2 Network Architectures for On-Chip Realization; 2.3 Ad Hoc Network Architectures; 2.4 Component Design for NoCs; 2.5 Properties of Network Architectures; 2.6 Summary; 3 Physical Network Layer; 3.1 Interconnection in DSM SoC; 3.2 High-Performance Signaling
3.3 Building Blocks3.4 Summary; 4 The Data-Link Layer in NoC Design; 4.1 Tasks of the Data-Link Layer; 4.2 On-Chip Communication Reliability; 4.3 Fault Models for NoCs; 4.4 Principles of Coding Theory; 4.5 The Power-Reliability Trade-Off; 4.6 Unified Coding Framework; 4.7 Adaptive Error Protection; 4.8 Data-Link Layer Architecture: Case Studies; 4.9 On-Chip Stochastic Communication; 4.10 Link-Level versus End-to-End Error Protection; 4.11 Flow Control; 4.12 Performance Exploration; 4.13 Summary; 5 Network and Transport Layers in Network on Chip; 5.1 Network and Transport Layers in NoCs
5.2 NoC QoS5.3 NoC Topology; 5.4 Switching Techniques; 5.5 NoC Addressing and Routing; 5.6 NoC Addressing; 5.7 Congestion Control and Flow Control; 5.8 Summary; 6 Network Interface Architecture and Design Issues; 6.1 NI Services; 6.2 NI Structure; 6.3 Evolution of Communication Protocols; 6.4 Point-to-Point Communication Protocols; 6.5 Latest Advances in Processor Interfaces; 6.6 The Packetization Stage; 6.7 End-to-End Flow Control; 6.8 Packet and Circuit Switching; 6.9 NI Architecture: The Aethereal Case Study; 6.10 NI Architecture: The xpipes Case Study
6.11 NIs for Asynchronous NoCs: The Mango Case Study6.12 Summary; 7 NoC Programming; 7.1 Architectural Template; 7.2 Task-Level Parallel Programming; 7.3 Communication-Exposed Programming; 7.4 Computer-Aided Software Development Tools; 7.5 Summary; 8 Design Methodologies and CAD Tool Flows for NoCs; 8.1 Network Analysis and Simulation; 8.2 Network Synthesis and Optimization; 8.3 Design Flows for NoCs; 8.4 Tool Kits for Designing Bus-Based Interconnect; 8.5 Summary; 9 Designs and Implementations of NoC-Based SoCs; 9.1 KAIST BONE Series; 9.2 NoC-Based Experimental Systems; 9.3 Summary; Index
Record Nr. UNINA-9910458595103321
Benini Luca <1967->  
Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Networks on chips [[electronic resource] ] : technology and tools / / Luca Benini and Giovanni De Micheli
Networks on chips [[electronic resource] ] : technology and tools / / Luca Benini and Giovanni De Micheli
Autore Benini Luca <1967->
Edizione [1st edition]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006
Descrizione fisica 1 online resource (408 p.)
Disciplina 621.3815
Altri autori (Persone) De MicheliGiovanni
Collana The Morgan Kaufmann series in systems on silicon
Soggetto topico Systems on a chip
Computer networks - Equipment and supplies
ISBN 1-280-96683-1
9786610966837
0-08-047356-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; Title page; Copyright Page; Table of contents; About The Authors; List of Contributors; 1 Networks on Chip; 1.1 Why On-Chip Networking?; 1.2 Technology Trends; 1.3 SoC Objectives and NoC Needs; 1.4 Once Over Lightly; 1.5 Perspectives; 2 Network Architecture: Principles and Examples; 2.1 Network Architecture; 2.2 Network Architectures for On-Chip Realization; 2.3 Ad Hoc Network Architectures; 2.4 Component Design for NoCs; 2.5 Properties of Network Architectures; 2.6 Summary; 3 Physical Network Layer; 3.1 Interconnection in DSM SoC; 3.2 High-Performance Signaling
3.3 Building Blocks3.4 Summary; 4 The Data-Link Layer in NoC Design; 4.1 Tasks of the Data-Link Layer; 4.2 On-Chip Communication Reliability; 4.3 Fault Models for NoCs; 4.4 Principles of Coding Theory; 4.5 The Power-Reliability Trade-Off; 4.6 Unified Coding Framework; 4.7 Adaptive Error Protection; 4.8 Data-Link Layer Architecture: Case Studies; 4.9 On-Chip Stochastic Communication; 4.10 Link-Level versus End-to-End Error Protection; 4.11 Flow Control; 4.12 Performance Exploration; 4.13 Summary; 5 Network and Transport Layers in Network on Chip; 5.1 Network and Transport Layers in NoCs
5.2 NoC QoS5.3 NoC Topology; 5.4 Switching Techniques; 5.5 NoC Addressing and Routing; 5.6 NoC Addressing; 5.7 Congestion Control and Flow Control; 5.8 Summary; 6 Network Interface Architecture and Design Issues; 6.1 NI Services; 6.2 NI Structure; 6.3 Evolution of Communication Protocols; 6.4 Point-to-Point Communication Protocols; 6.5 Latest Advances in Processor Interfaces; 6.6 The Packetization Stage; 6.7 End-to-End Flow Control; 6.8 Packet and Circuit Switching; 6.9 NI Architecture: The Aethereal Case Study; 6.10 NI Architecture: The xpipes Case Study
6.11 NIs for Asynchronous NoCs: The Mango Case Study6.12 Summary; 7 NoC Programming; 7.1 Architectural Template; 7.2 Task-Level Parallel Programming; 7.3 Communication-Exposed Programming; 7.4 Computer-Aided Software Development Tools; 7.5 Summary; 8 Design Methodologies and CAD Tool Flows for NoCs; 8.1 Network Analysis and Simulation; 8.2 Network Synthesis and Optimization; 8.3 Design Flows for NoCs; 8.4 Tool Kits for Designing Bus-Based Interconnect; 8.5 Summary; 9 Designs and Implementations of NoC-Based SoCs; 9.1 KAIST BONE Series; 9.2 NoC-Based Experimental Systems; 9.3 Summary; Index
Record Nr. UNINA-9910784651503321
Benini Luca <1967->  
Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Networks on chips [[electronic resource] ] : technology and tools / / Luca Benini and Giovanni De Micheli
Networks on chips [[electronic resource] ] : technology and tools / / Luca Benini and Giovanni De Micheli
Autore Benini Luca <1967->
Edizione [1st edition]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006
Descrizione fisica 1 online resource (408 p.)
Disciplina 621.3815
Altri autori (Persone) De MicheliGiovanni
Collana The Morgan Kaufmann series in systems on silicon
Soggetto topico Systems on a chip
Computer networks - Equipment and supplies
ISBN 1-280-96683-1
9786610966837
0-08-047356-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; Title page; Copyright Page; Table of contents; About The Authors; List of Contributors; 1 Networks on Chip; 1.1 Why On-Chip Networking?; 1.2 Technology Trends; 1.3 SoC Objectives and NoC Needs; 1.4 Once Over Lightly; 1.5 Perspectives; 2 Network Architecture: Principles and Examples; 2.1 Network Architecture; 2.2 Network Architectures for On-Chip Realization; 2.3 Ad Hoc Network Architectures; 2.4 Component Design for NoCs; 2.5 Properties of Network Architectures; 2.6 Summary; 3 Physical Network Layer; 3.1 Interconnection in DSM SoC; 3.2 High-Performance Signaling
3.3 Building Blocks3.4 Summary; 4 The Data-Link Layer in NoC Design; 4.1 Tasks of the Data-Link Layer; 4.2 On-Chip Communication Reliability; 4.3 Fault Models for NoCs; 4.4 Principles of Coding Theory; 4.5 The Power-Reliability Trade-Off; 4.6 Unified Coding Framework; 4.7 Adaptive Error Protection; 4.8 Data-Link Layer Architecture: Case Studies; 4.9 On-Chip Stochastic Communication; 4.10 Link-Level versus End-to-End Error Protection; 4.11 Flow Control; 4.12 Performance Exploration; 4.13 Summary; 5 Network and Transport Layers in Network on Chip; 5.1 Network and Transport Layers in NoCs
5.2 NoC QoS5.3 NoC Topology; 5.4 Switching Techniques; 5.5 NoC Addressing and Routing; 5.6 NoC Addressing; 5.7 Congestion Control and Flow Control; 5.8 Summary; 6 Network Interface Architecture and Design Issues; 6.1 NI Services; 6.2 NI Structure; 6.3 Evolution of Communication Protocols; 6.4 Point-to-Point Communication Protocols; 6.5 Latest Advances in Processor Interfaces; 6.6 The Packetization Stage; 6.7 End-to-End Flow Control; 6.8 Packet and Circuit Switching; 6.9 NI Architecture: The Aethereal Case Study; 6.10 NI Architecture: The xpipes Case Study
6.11 NIs for Asynchronous NoCs: The Mango Case Study6.12 Summary; 7 NoC Programming; 7.1 Architectural Template; 7.2 Task-Level Parallel Programming; 7.3 Communication-Exposed Programming; 7.4 Computer-Aided Software Development Tools; 7.5 Summary; 8 Design Methodologies and CAD Tool Flows for NoCs; 8.1 Network Analysis and Simulation; 8.2 Network Synthesis and Optimization; 8.3 Design Flows for NoCs; 8.4 Tool Kits for Designing Bus-Based Interconnect; 8.5 Summary; 9 Designs and Implementations of NoC-Based SoCs; 9.1 KAIST BONE Series; 9.2 NoC-Based Experimental Systems; 9.3 Summary; Index
Record Nr. UNINA-9910809103403321
Benini Luca <1967->  
Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
VLSI test principles and architectures [[electronic resource] ] : design for testability / / edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen
VLSI test principles and architectures [[electronic resource] ] : design for testability / / edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen
Edizione [1st edition]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006
Descrizione fisica 1 online resource (809 p.)
Disciplina 621.39/5
Altri autori (Persone) WangLaung-Terng
WuCheng-Wen, EE Ph. D.
WenXiaoqing
Collana The Morgan Kaufmann series in systems on silicon
Soggetto topico Integrated circuits - Very large scale integration - Testing
Integrated circuits - Very large scale integration - Design
Soggetto genere / forma Electronic books.
ISBN 1-280-96684-X
9786610966844
0-08-047479-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front cover; Title page; Copyright page; Table of contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; 1 Introduction; Importance of Testing; Testing During the VLSI Lifecycle; VLSI Development Process; Design Verification; Yield and Reject Rate; Electronic System Manufacturing Process; System-Level Operation; Challenges in VLSI Testing; Test Generation; Fault Models; Stuck-At Faults; Transistor Faults; Open and Short Faults; Delay Faults and Crosstalk; Pattern Sensitivity and Coupling Faults; Analog Fault Models; Levels of Abstraction in VLSI Testing
Register-Transfer Level and Behavioral Level Gate Level; Switch Level; Physical Level; Historical Review of VLSI Test Technology; Automatic Test Equipment; Automatic Test Pattern Generation; Fault Simulation; Digital Circuit Testing; Analog and Mixed-Signal Circuit Testing; Design for Testability; Board Testing; Boundary Scan Testing; Concluding Remarks; Exercises; Acknowledgments; References; 2 Design for Testability; Introduction; Testability Analysis; SCOAP Testability Analysis; Combinational Controllability and Observability Calculation
Sequential Controllability and Observability Calculation Probability-Based Testability Analysis; Simulation-Based Testability Analysis; RTL Testability Analysis; Design for Testability Basics; Ad Hoc Approach; Test Point Insertion; Structured Approach; Scan Cell Designs; Muxed-D Scan Cell; Clocked-Scan Cell; LSSD Scan Cell; Scan Architectures; Full-Scan Design; Muxed-D Full-Scan Design; Clocked Full-Scan Design; LSSD Full-Scan Design; Partial-Scan Design; Random-Access Scan Design; Scan Design Rules; Tristate Buses; Bidirectional I/O Ports; Gated Clocks; Derived Clocks
Combinational Feedback Loops Asynchronous Set/Reset Signals; Scan Design Flow; Scan Design Rule Checking and Repair; Scan Synthesis; Scan Configuration; Scan Replacement; Scan Reordering; Scan Stitching; Scan Extraction; Scan Verification; Verifying the Scan Shift Operation; Verifying the Scan Capture Operation; Scan Design Costs; Special-Purpose Scan Designs; Enhanced Scan; Snapshot Scan; Error-Resilient Scan; RTL Design for Testability; RTL Scan Design Rule Checking and Repair; RTL Scan Synthesis; RTL Scan Extraction and Scan Verification; Concluding Remarks; Exercises; Acknowledgments
References 3 Logic and Fault Simulation; Introduction; Logic Simulation for Design Verification; Fault Simulation for Test and Diagnosis; Simulation Models; Gate-Level Network; Sequential Circuits; Logic Symbols; Unknown State u; High-Impedance State Z; Intermediate Logic States; Logic Element Evaluation; Truth Tables; Input Scanning; Input Counting; Parallel Gate Evaluation; Timing Models; Transport Delay; Inertial Delay; Wire Delay; Functional Element Delay Model; Logic Simulation; Compiled-Code Simulation; Logic Optimization; Logic Levelization; Code Generation; Event-Driven Simulation
Nominal-Delay Event-Driven Simulation
Record Nr. UNINA-9910458608703321
Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
VLSI test principles and architectures [[electronic resource] ] : design for testability / / edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen
VLSI test principles and architectures [[electronic resource] ] : design for testability / / edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen
Edizione [1st edition]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006
Descrizione fisica 1 online resource (809 p.)
Disciplina 621.39/5
Altri autori (Persone) WangLaung-Terng
WuCheng-Wen, EE Ph. D.
WenXiaoqing
Collana The Morgan Kaufmann series in systems on silicon
Soggetto topico Integrated circuits - Very large scale integration - Testing
Integrated circuits - Very large scale integration - Design
ISBN 1-280-96684-X
9786610966844
0-08-047479-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front cover; Title page; Copyright page; Table of contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; 1 Introduction; Importance of Testing; Testing During the VLSI Lifecycle; VLSI Development Process; Design Verification; Yield and Reject Rate; Electronic System Manufacturing Process; System-Level Operation; Challenges in VLSI Testing; Test Generation; Fault Models; Stuck-At Faults; Transistor Faults; Open and Short Faults; Delay Faults and Crosstalk; Pattern Sensitivity and Coupling Faults; Analog Fault Models; Levels of Abstraction in VLSI Testing
Register-Transfer Level and Behavioral Level Gate Level; Switch Level; Physical Level; Historical Review of VLSI Test Technology; Automatic Test Equipment; Automatic Test Pattern Generation; Fault Simulation; Digital Circuit Testing; Analog and Mixed-Signal Circuit Testing; Design for Testability; Board Testing; Boundary Scan Testing; Concluding Remarks; Exercises; Acknowledgments; References; 2 Design for Testability; Introduction; Testability Analysis; SCOAP Testability Analysis; Combinational Controllability and Observability Calculation
Sequential Controllability and Observability Calculation Probability-Based Testability Analysis; Simulation-Based Testability Analysis; RTL Testability Analysis; Design for Testability Basics; Ad Hoc Approach; Test Point Insertion; Structured Approach; Scan Cell Designs; Muxed-D Scan Cell; Clocked-Scan Cell; LSSD Scan Cell; Scan Architectures; Full-Scan Design; Muxed-D Full-Scan Design; Clocked Full-Scan Design; LSSD Full-Scan Design; Partial-Scan Design; Random-Access Scan Design; Scan Design Rules; Tristate Buses; Bidirectional I/O Ports; Gated Clocks; Derived Clocks
Combinational Feedback Loops Asynchronous Set/Reset Signals; Scan Design Flow; Scan Design Rule Checking and Repair; Scan Synthesis; Scan Configuration; Scan Replacement; Scan Reordering; Scan Stitching; Scan Extraction; Scan Verification; Verifying the Scan Shift Operation; Verifying the Scan Capture Operation; Scan Design Costs; Special-Purpose Scan Designs; Enhanced Scan; Snapshot Scan; Error-Resilient Scan; RTL Design for Testability; RTL Scan Design Rule Checking and Repair; RTL Scan Synthesis; RTL Scan Extraction and Scan Verification; Concluding Remarks; Exercises; Acknowledgments
References 3 Logic and Fault Simulation; Introduction; Logic Simulation for Design Verification; Fault Simulation for Test and Diagnosis; Simulation Models; Gate-Level Network; Sequential Circuits; Logic Symbols; Unknown State u; High-Impedance State Z; Intermediate Logic States; Logic Element Evaluation; Truth Tables; Input Scanning; Input Counting; Parallel Gate Evaluation; Timing Models; Transport Delay; Inertial Delay; Wire Delay; Functional Element Delay Model; Logic Simulation; Compiled-Code Simulation; Logic Optimization; Logic Levelization; Code Generation; Event-Driven Simulation
Nominal-Delay Event-Driven Simulation
Record Nr. UNINA-9910784654603321
Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
VLSI test principles and architectures [[electronic resource] ] : design for testability / / edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen
VLSI test principles and architectures [[electronic resource] ] : design for testability / / edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen
Edizione [1st edition]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006
Descrizione fisica 1 online resource (809 p.)
Disciplina 621.39/5
Altri autori (Persone) WangLaung-Terng
WuCheng-Wen, EE Ph. D.
WenXiaoqing
Collana The Morgan Kaufmann series in systems on silicon
Soggetto topico Integrated circuits - Very large scale integration - Testing
Integrated circuits - Very large scale integration - Design
ISBN 1-280-96684-X
9786610966844
0-08-047479-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front cover; Title page; Copyright page; Table of contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; 1 Introduction; Importance of Testing; Testing During the VLSI Lifecycle; VLSI Development Process; Design Verification; Yield and Reject Rate; Electronic System Manufacturing Process; System-Level Operation; Challenges in VLSI Testing; Test Generation; Fault Models; Stuck-At Faults; Transistor Faults; Open and Short Faults; Delay Faults and Crosstalk; Pattern Sensitivity and Coupling Faults; Analog Fault Models; Levels of Abstraction in VLSI Testing
Register-Transfer Level and Behavioral Level Gate Level; Switch Level; Physical Level; Historical Review of VLSI Test Technology; Automatic Test Equipment; Automatic Test Pattern Generation; Fault Simulation; Digital Circuit Testing; Analog and Mixed-Signal Circuit Testing; Design for Testability; Board Testing; Boundary Scan Testing; Concluding Remarks; Exercises; Acknowledgments; References; 2 Design for Testability; Introduction; Testability Analysis; SCOAP Testability Analysis; Combinational Controllability and Observability Calculation
Sequential Controllability and Observability Calculation Probability-Based Testability Analysis; Simulation-Based Testability Analysis; RTL Testability Analysis; Design for Testability Basics; Ad Hoc Approach; Test Point Insertion; Structured Approach; Scan Cell Designs; Muxed-D Scan Cell; Clocked-Scan Cell; LSSD Scan Cell; Scan Architectures; Full-Scan Design; Muxed-D Full-Scan Design; Clocked Full-Scan Design; LSSD Full-Scan Design; Partial-Scan Design; Random-Access Scan Design; Scan Design Rules; Tristate Buses; Bidirectional I/O Ports; Gated Clocks; Derived Clocks
Combinational Feedback Loops Asynchronous Set/Reset Signals; Scan Design Flow; Scan Design Rule Checking and Repair; Scan Synthesis; Scan Configuration; Scan Replacement; Scan Reordering; Scan Stitching; Scan Extraction; Scan Verification; Verifying the Scan Shift Operation; Verifying the Scan Capture Operation; Scan Design Costs; Special-Purpose Scan Designs; Enhanced Scan; Snapshot Scan; Error-Resilient Scan; RTL Design for Testability; RTL Scan Design Rule Checking and Repair; RTL Scan Synthesis; RTL Scan Extraction and Scan Verification; Concluding Remarks; Exercises; Acknowledgments
References 3 Logic and Fault Simulation; Introduction; Logic Simulation for Design Verification; Fault Simulation for Test and Diagnosis; Simulation Models; Gate-Level Network; Sequential Circuits; Logic Symbols; Unknown State u; High-Impedance State Z; Intermediate Logic States; Logic Element Evaluation; Truth Tables; Input Scanning; Input Counting; Parallel Gate Evaluation; Timing Models; Transport Delay; Inertial Delay; Wire Delay; Functional Element Delay Model; Logic Simulation; Compiled-Code Simulation; Logic Optimization; Logic Levelization; Code Generation; Event-Driven Simulation
Nominal-Delay Event-Driven Simulation
Record Nr. UNINA-9910822798703321
Amsterdam ; ; Boston, : Elsevier Morgan Kaufmann Publishers, c2006
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui