Edizione	[2nd ed.]
Pubbl/distr/stampa	Chichester, West Susex, : Wiley, 2012
Descrizione fisica	1 online resource (615 p.)
Disciplina	621.39/5
Altri autori (Persone)	BaklanovMikhail HoP. S ZschechEhrenfried
Soggetto topico	Integrated circuits - Ultra large scale integration Interconnects (Integrated circuit technology)
ISBN	1-119-96686-8 1-119-96367-2 1-280-59080-7 9786613620637 1-119-96324-9
Classificazione	TEC008050
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Advanced Interconnects for ULSI Technology; Contents; About the Editors; List of Contributors; Preface; Abbreviations; Section I Low-k Materials; 1 Low-k Materials: Recent Advances; 1.1 Introduction; 1.2 Integration Challenges; 1.2.1 Process-Induced Damage; 1.2.2 Mechanical Properties; 1.3 Processing Approaches to Existing Integration Issues; 1.3.1 Post-deposition Treatments; 1.3.2 Prevention or Repair of Plasma-Induced Processing Damage; 1.3.3 Multilayer Structures; 1.4 Material Advances to Overcome Current Limitations; 1.4.1 Silica Zeolites; 1.4.2 Hybrid Organic-Inorganic: Oxycarbosilanes 1.5 ConclusionReferences; 2 Ultra-Low-k by CVD: Deposition and Curing; 2.1 Introduction; 2.2 Porogen Approach by PECVD; 2.2.1 Precursors and Deposition Conditions; 2.2.2 Mystery Still Unsolved: From Porogens to Pores; 2.3 UV Curing; 2.3.1 General Overview of Curing; 2.3.2 UV Curing Mechanisms; 2.4 Impact of Curing on Structure and Physical Properties: Benefits of UV Curing; 2.4.1 Porosity; 2.4.2 Chemical Structure and Mechanical Properties; 2.4.3 Electrical Properties; 2.5 Limit/Issues with the Porogen Approach; 2.5.1 Porosity Creation Limit; 2.5.2 Porogen Residues; 2.6 Future of CVD Low-k 2.6.1 New Matrix Precursor2.6.2 Other Deposition Strategies; 2.6.3 New Deposition Techniques; 2.7 Material Engineering: Adaptation to Integration Schemes; 2.8 Conclusion; References; 3 Plasma Processing of Low-k Dielectrics; 3.1 Introduction; 3.2 Materials and Equipment; 3.3 Process Results Characterization; 3.4 Interaction of Low-k Dielectrics with Plasma; 3.4.1 Low-k Etch Chemistries; 3.4.2 Patterning Strategies and Masking Materials; 3.4.3 Etch Mechanisms; 3.5 Mechanisms of Plasma Damage; 3.5.1 Gap Structure Studies; 3.5.2 Effect of Radical Density; 3.5.3 Effect of Ion Energy 3.5.4 Effect of Photon Energy and Intensity3.5.5 Plasma Damage by Oxidative Radicals; 3.5.6 Hydrogen-Based Plasma; 3.5.7 Minimization of Plasma Damage; 3.6 Dielectric Recovery; 3.6.1 CH4 Beam Treatment; 3.6.2 Dielectric Recovery by Silylation; 3.6.3 UV Radiation; 3.7 Conclusions; References; 4 Wet Clean Applications in Porous Low-k Patterning Processes; 4.1 Introduction; 4.2 Silica and Porous Hybrid Dielectric Materials; 4.3 Impact of Plasma and Subsequent Wet Clean Processes on the Stability of Porous Low-k Dielectrics; 4.3.1 Stability in Pure Chemical Solutions 4.3.2 Stability in Commercial Chemistries4.3.3 Hydrophobicity of Hybrid Low-k Materials; 4.4 Removal of Post-Etch Residues and Copper Surface Cleaning; 4.5 Plasma Modification and Removal of Post-Etch 193 nm Photoresist; 4.5.1 Modification of 193 nm Photoresist by Plasma Etch; 4.5.2 Wet Removal of 193 nm Photoresist; Acknowledgments; References; Section II Conductive Layers and Barriers; 5 Copper Electroplating for On-Chip Metallization; 5.1 Introduction; 5.2 Copper Electroplating Techniques; 5.3 Copper Electroplating Superfill; 5.3.1 The Role of Accelerator; 5.3.2 The Role of Suppressor 5.3.3 The Role of Leveler
Record Nr.	UNINA-9910141346803321

Autore	Li Er-Ping
Pubbl/distr/stampa	Hoboken, N.J., : Wiley, c2012
Descrizione fisica	1 online resource (390 p.)
Disciplina	621.3815
Soggetto topico	Three-dimensional integrated circuits Integrated circuits
ISBN	9786613650047 9781280673115 1280673117 9781118166741 1118166744 9781118166727 1118166728 9781118166758 1118166752
Classificazione	TEC008050
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Macromodeling of Complex Interconnects in 3D Integration -- 2.5D Simulation Method for 3D Integrated Systems -- Hybrid Integral Equation Modeling Methods for 3D Integration -- Systematic Microwave Network Analysis for 3D Integrated Systems -- Modeling of Through-Silicon Vias (TSV) in 3D Integration.
Record Nr.	UNINA-9911020335303321

Autore	Doman David
Edizione	[1st edition]
Pubbl/distr/stampa	Hoboken, N.J., : John Wiley & Sons, c2012
Descrizione fisica	1 online resource (343 p.)
Disciplina	621.3815
Soggetto topico	Digital integrated circuits - Design and construction Metal oxide semiconductors, Complementary Industrial efficiency
ISBN	1-280-59206-0 9786613621894 1-118-27313-3 1-118-27314-1 1-118-27311-7
Classificazione	TEC008050
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon; Contents; Preface; Acknowledgments; 1: Introduction; 1.1: Adding Project-Specific Functions, Drive Strengths, Views, and Corners; 1.2: What Is a DDK?; 2: Stdcell Libraries; 2.1: Lesson from the Real World: Manager's Perspective and Engineer's Perspective; 2.2: What Is a Stdcell?; 2.2.1: Combinational Functions; 2.2.2: Sequential Functions; 2.2.3: Clock Functions; 2.3: Extended Library Offerings; 2.3.1: Low-Power Support; 2.4: Boutique Library Offerings; 2.5: Concepts for Further Study; 3: IO Libraries 3.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 3.2: Extension Capable Architectures versus Function Complete Architectures; 3.3: Electrostatic Discharge Considerations; 3.3.1: Footprints; 3.3.2: Custom Design Versus Standard IO Design Comparison; 3.3.3: The Need for Maintaining Multiple IO Footprint Regions on an IC; 3.3.4: Circuit Under Pad; 3.4: Concepts for Further Study; 4: Memory Compilers; 4.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 4.2: Single Ports, Dual Ports, and ROM: The Compiler 4.3: Nonvolatile Memories: The Block 4.4: Special-Purpose Memories: The Custom; 4.5: Concepts for Further Study; 5: Other Functions; 5.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 5.2: Phase-Locked Loops, Power-On Resets, and Other Small-Scale Integration Analogs; 5.3: Low-Power Support Structures; 5.4: Stitching Structures; 5.4.1: Core-Fill Cells; 5.4.2: IO-Fill Cells; 5.4.3: DECAP Cells; 5.4.4: CMP-Fill Cells; 5.4.5: Spare Logic Cells; 5.4.6: Probe-Point Cells; 5.4.7: Antenna Diodes; 5.4.8: Test-Debug Diodes; 5.4.9: Others 5.5: Hard, Firm, and Soft Boxes 5.6: Concepts for Further Study; 6: Physical Views; 6.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 6.2: Picking an Architecture; 6.3: Measuring Density; 6.4: The Need and the Way to Work with Fabrication Houses; 6.5: Concepts for Further Study; 7: SPICE; 7.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 7.2: Why a Tool More Than 40 Years Old Is Still Useful; 7.3: Accuracy, Reality, and Why SPICE Results Must be Viewed with a Wary Eye; 7.4: Sufficient Parasitics 7.5: Concepts for Further Study 8: Timing Views; 8.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 8.2: Performance Limits and Measurement; 8.3: Default Versus Conditional Arcs; 8.4: Break-Point Optimization; 8.5: A Word on Setup and Hold; 8.6: Failure Mechanisms and Roll-Off; 8.7: Supporting Efficient Synthesis; 8.7.1: SPICE, Monotonic Arrays, and Favorite Stdcells; 8.7.2: SPICE, Positive Arrays, and Useful Skew; 8.8: Supporting Efficient Timing Closure; 8.9: Design Corner Specific Timing Views; 8.10: Nonlinear Timing Views are so ""Old Hat"" . . . 8.11: Concepts for Further Study
Record Nr.	UNINA-9910141337703321

Autore	Grivet-Talocia Stefano <1970->
Pubbl/distr/stampa	Hoboken, New Jersey : , : Wiley, , 2016
Descrizione fisica	1 online resource (903 p.)
Disciplina	621.301/1
Collana	Wiley Series in Microwave and Optical Engineering
Soggetto topico	Electromagnetic interference - Computer simulation Analog electronic systems - Computer simulation Electric power systems - Computer simulation Passive components - Computer simulation
ISBN	1-119-14095-1 1-119-14097-8
Classificazione	TEC008050
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Record Nr.	UNINA-9910131383103321