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Advanced Frequency Synthesis by Phase Lock / / William F. Egan
| Advanced Frequency Synthesis by Phase Lock / / William F. Egan |
| Autore | Egan William F. <1936-> |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : Wiley, , c2011 |
| Descrizione fisica | 1 online resource (314 p.) |
| Disciplina | 621.3815486 |
| Soggetto topico |
Frequency synthesizers
Phase-locked loops |
| ISBN |
1-283-33753-3
9786613337535 1-118-17115-2 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Frontmatter -- Introduction -- Fractional-N and Basic S? Synthesizers -- Other Spurious Reduction Techniques -- Defects in S? Synthesizers -- Other S? Architectures -- Simulation -- Diophantine Synthesizer -- Operation at Extreme Bandwidths -- All-Digital Frequency Synthesizers -- Appendix A: All Digital -- Appendix C: Fractional Cancellation -- Appendix E: Excess PPSD -- Appendix F: References to -- Appendix G: Using Gsmpl -- Appendix H: Sample-and-Hold Circuit -- Appendix L: Loop Response -- Appendix M: Mash PPSD -- Appendix N: Sampled Noise -- Appendix O: Oscillator Spectrums -- Appendix P: Phase Detectors -- Appendix Q: Quantization PPSD -- Appendix R: Reference Frequency Spurs -- Appendix S: Spectrum Analysis -- Appendix T: Toolboxes -- Appendix U: Noise Produced by Charge Pump Current Unbalance (Mismatch) -- Appendix W: Getting Files from the Wiley Internet Site -- Appendix X: Some Tables -- End Notes -- References -- Index. |
| Record Nr. | UNINA-9910139746003321 |
Egan William F. <1936->
|
||
| Hoboken, New Jersey : , : Wiley, , c2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Advanced Frequency Synthesis by Phase Lock / / William F. Egan
| Advanced Frequency Synthesis by Phase Lock / / William F. Egan |
| Autore | Egan William F. <1936-> |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : Wiley, , c2011 |
| Descrizione fisica | 1 online resource (314 p.) |
| Disciplina | 621.3815486 |
| Soggetto topico |
Frequency synthesizers
Phase-locked loops |
| ISBN |
1-283-33753-3
9786613337535 1-118-17115-2 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Frontmatter -- Introduction -- Fractional-N and Basic S? Synthesizers -- Other Spurious Reduction Techniques -- Defects in S? Synthesizers -- Other S? Architectures -- Simulation -- Diophantine Synthesizer -- Operation at Extreme Bandwidths -- All-Digital Frequency Synthesizers -- Appendix A: All Digital -- Appendix C: Fractional Cancellation -- Appendix E: Excess PPSD -- Appendix F: References to -- Appendix G: Using Gsmpl -- Appendix H: Sample-and-Hold Circuit -- Appendix L: Loop Response -- Appendix M: Mash PPSD -- Appendix N: Sampled Noise -- Appendix O: Oscillator Spectrums -- Appendix P: Phase Detectors -- Appendix Q: Quantization PPSD -- Appendix R: Reference Frequency Spurs -- Appendix S: Spectrum Analysis -- Appendix T: Toolboxes -- Appendix U: Noise Produced by Charge Pump Current Unbalance (Mismatch) -- Appendix W: Getting Files from the Wiley Internet Site -- Appendix X: Some Tables -- End Notes -- References -- Index. |
| Record Nr. | UNINA-9910830729803321 |
|
Egan William F. <1936->
|
||
| Hoboken, New Jersey : , : Wiley, , c2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Advanced frequency synthesis by phase lock / / William F. Egan
| Advanced frequency synthesis by phase lock / / William F. Egan |
| Autore | Egan William F |
| Pubbl/distr/stampa | Hoboken, New Jersey, : Wiley, 2011 |
| Descrizione fisica | 1 online resource (314 p.) |
| Disciplina | 621.3815/486 |
| Soggetto topico |
Frequency synthesizers
Phase-locked loops |
| ISBN |
1-283-33753-3
9786613337535 1-118-17115-2 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Frontmatter -- Introduction -- Fractional-N and Basic S? Synthesizers -- Other Spurious Reduction Techniques -- Defects in S? Synthesizers -- Other S? Architectures -- Simulation -- Diophantine Synthesizer -- Operation at Extreme Bandwidths -- All-Digital Frequency Synthesizers -- Appendix A: All Digital -- Appendix C: Fractional Cancellation -- Appendix E: Excess PPSD -- Appendix F: References to -- Appendix G: Using Gsmpl -- Appendix H: Sample-and-Hold Circuit -- Appendix L: Loop Response -- Appendix M: Mash PPSD -- Appendix N: Sampled Noise -- Appendix O: Oscillator Spectrums -- Appendix P: Phase Detectors -- Appendix Q: Quantization PPSD -- Appendix R: Reference Frequency Spurs -- Appendix S: Spectrum Analysis -- Appendix T: Toolboxes -- Appendix U: Noise Produced by Charge Pump Current Unbalance (Mismatch) -- Appendix W: Getting Files from the Wiley Internet Site -- Appendix X: Some Tables -- End Notes -- References -- Index. |
| Record Nr. | UNINA-9910877676603321 |
|
Egan William F
|
||
| Hoboken, New Jersey, : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
CMOS voltage references : an analytical and practical perspective / / Chi-Wah Kok and Wing-Shan Tam
| CMOS voltage references : an analytical and practical perspective / / Chi-Wah Kok and Wing-Shan Tam |
| Autore | Kok Chi-Wah |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Singapore, : IEEE, 2013 |
| Descrizione fisica | 1 online resource (312 p.) |
| Disciplina |
621.381528
621.39732 |
| Altri autori (Persone) | TamWing-Shan |
| Soggetto topico |
Voltage references
Electric circuit analysis Electric circuits - Design and construction |
| ISBN |
1-118-27569-1
1-283-86962-4 1-118-27570-5 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Front Matter -- Warm Up -- Voltage Reference -- Bandgap Voltage Reference -- Error Sources in Bandgap Voltage Reference Circuit -- Advanced Voltage Reference Circuits. Temperature Compensation Techniques -- Sub-1V Voltage Reference Circuit -- High Order Curvature Correction -- CMOS Voltage Reference without Resistors -- SPICE Model File -- SPICE Netlist of Voltage Reference Circuit -- Index |
| Record Nr. | UNINA-9910877211303321 |
|
Kok Chi-Wah
|
||
| Singapore, : IEEE, 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
CMOS voltage references : an analytical and practical perspective / / Chi-Wah Kok and Wing-Shan Tam
| CMOS voltage references : an analytical and practical perspective / / Chi-Wah Kok and Wing-Shan Tam |
| Autore | Kok Chi-Wah |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | [Hoboken, New Jersey] : , : Wiley, , 2012 |
| Descrizione fisica | 1 online resource (312 p.) |
| Disciplina |
621.381528
621.39732 |
| Altri autori (Persone) | TamWing-Shan |
| Soggetto topico |
Voltage references
Electric circuit analysis Electric circuits - Design and construction |
| ISBN |
1-118-27569-1
1-283-86962-4 1-118-27570-5 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Front Matter -- Warm Up -- Voltage Reference -- Bandgap Voltage Reference -- Error Sources in Bandgap Voltage Reference Circuit -- Advanced Voltage Reference Circuits. Temperature Compensation Techniques -- Sub-1V Voltage Reference Circuit -- High Order Curvature Correction -- CMOS Voltage Reference without Resistors -- SPICE Model File -- SPICE Netlist of Voltage Reference Circuit -- Index |
| Record Nr. | UNINA-9910138865403321 |
|
Kok Chi-Wah
|
||
| [Hoboken, New Jersey] : , : Wiley, , 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
CMOS voltage references : an analytical and practical perspective / / Chi-Wah Kok and Wing-Shan Tam
| CMOS voltage references : an analytical and practical perspective / / Chi-Wah Kok and Wing-Shan Tam |
| Autore | Kok Chi-Wah |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | [Hoboken, New Jersey] : , : Wiley, , 2012 |
| Descrizione fisica | 1 online resource (312 p.) |
| Disciplina |
621.381528
621.39732 |
| Altri autori (Persone) | TamWing-Shan |
| Soggetto topico |
Voltage references
Electric circuit analysis Electric circuits - Design and construction |
| ISBN |
1-118-27569-1
1-283-86962-4 1-118-27570-5 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Front Matter -- Warm Up -- Voltage Reference -- Bandgap Voltage Reference -- Error Sources in Bandgap Voltage Reference Circuit -- Advanced Voltage Reference Circuits. Temperature Compensation Techniques -- Sub-1V Voltage Reference Circuit -- High Order Curvature Correction -- CMOS Voltage Reference without Resistors -- SPICE Model File -- SPICE Netlist of Voltage Reference Circuit -- Index |
| Record Nr. | UNINA-9910830590803321 |
|
Kok Chi-Wah
|
||
| [Hoboken, New Jersey] : , : Wiley, , 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electrical overstress (EOS) [[electronic resource] ] : devices, circuits and systems / / Steven H. Voldman
| Electrical overstress (EOS) [[electronic resource] ] : devices, circuits and systems / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K., : John Wiley & Sons Inc., 2014 |
| Descrizione fisica | 1 online resource (370 p.) |
| Disciplina | 621.3815 |
| Collana | ESD series |
| Soggetto topico |
Semiconductors - Failures
Semiconductors - Protection Transients (Electricity) Overvoltage |
| ISBN |
1-118-70333-2
1-118-70332-4 1-118-70334-0 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Electrical Overstress (EOS): Devices, Circuits and Systems; Contents; About the Author; Preface; Acknowledgements; 1 Fundamentals of Electrical Overstress; 1.1 Electrical Overstress; 1.1.1 The Cost of Electrical Overstress; 1.1.2 Product Field Returns - The Percentage that is Electrical Overstress; 1.1.3 Product Field Returns - No Defect Found versus Electrical Overstress; 1.1.4 Product Failures - Failures in Integrated Circuits; 1.1.5 Classification of Electrical Overstress Events; 1.1.6 Electrical Over-Current; 1.1.7 Electrical Over-Voltage; 1.1.8 Electrical Over-Power
1.2 De-Mystifying Electrical Overstress1.2.1 Electrical Overstress Events; 1.3 Sources of Electrical Overstress; 1.3.1 Sources of Electrical Overstress in Manufacturing Environment; 1.3.2 Sources of Electrical Overstress in Production Environments; 1.4 Misconceptions of Electrical Overstress; 1.5 Minimization of Electrical Overstress Sources; 1.6 Mitigation of Electrical Overstress; 1.7 Signs of Electrical Overstress Damage; 1.7.1 Signs of Electrical Overstress Damage - The Electrical Signature; 1.7.2 Signs of Electrical Overstress Damage - The Visual Signature 1.8 Electrical Overstress and Electrostatic Discharge1.8.1 Comparison of High and Low Current EOS versus ESD Events; 1.8.2 Electrical Overstress and Electrostatic Discharge Differences; 1.8.3 Electrical Overstress and Electrostatic Discharge Similarities; 1.8.4 Comparison of EOS versus ESDWaveforms; 1.8.5 Comparison of EOS versus ESD Event Failure Damage; 1.9 Electromagnetic Interference; 1.9.1 Electrical Overstress Induced Electromagnetic Interference; 1.10 Electromagnetic Compatibility; 1.11 Thermal Over-Stress; 1.11.1 Electrical Overstress and Thermal Overstress 1.11.2 Temperature Dependent Electrical Overstress1.11.3 Electrical Overstress and Melting Temperature; 1.12 Reliability Technology Scaling; 1.12.1 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.12.2 The Shrinking Reliability Design Box; 1.12.3 The Shrinking Electrostatic Discharge Design Box; 1.12.4 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.13 Safe Operating Area; 1.13.1 Electrical Safe Operating Area; 1.13.2 Thermal Safe Operating Area; 1.13.3 Transient Safe Operating Area; 1.14 Summary and Closing Comments; References 2 Fundamentals of EOS Models2.1 Thermal Time Constants; 2.1.1 The Thermal Diffusion Time; 2.1.2 The Adiabatic Regime Time Constant; 2.1.3 The Thermal Diffusion Regime Time Constant; 2.1.4 The Steady State Regime Time Constant; 2.2 Pulse Event Time Constants; 2.2.1 The ESD HBM Pulse Time Constant; 2.2.2 The ESD MM Pulse Time Constant; 2.2.3 The ESD Charged Device Model Pulse Time Constant; 2.2.4 The ESD Pulse Time Constant - Transmission Line Pulse; 2.2.5 The ESD Pulse Time Constant - Very Fast Transmission Line Pulse; 2.2.6 The IEC 61000-4-2 Pulse Time Constant 2.2.7 The Cable Discharge Event Pulse Time Constant |
| Record Nr. | UNINA-9910139024303321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, U.K., : John Wiley & Sons Inc., 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electrical overstress (EOS) : devices, circuits and systems / / Steven H. Voldman
| Electrical overstress (EOS) : devices, circuits and systems / / Steven H. Voldman |
| Autore | Voldman Steven H |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Chichester, West Sussex, U.K., : John Wiley & Sons Inc., 2014 |
| Descrizione fisica | 1 online resource (370 p.) |
| Disciplina | 621.3815 |
| Collana | ESD series |
| Soggetto topico |
Semiconductors - Failures
Semiconductors - Protection Transients (Electricity) Overvoltage |
| ISBN |
1-118-70333-2
1-118-70332-4 1-118-70334-0 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Electrical Overstress (EOS): Devices, Circuits and Systems; Contents; About the Author; Preface; Acknowledgements; 1 Fundamentals of Electrical Overstress; 1.1 Electrical Overstress; 1.1.1 The Cost of Electrical Overstress; 1.1.2 Product Field Returns - The Percentage that is Electrical Overstress; 1.1.3 Product Field Returns - No Defect Found versus Electrical Overstress; 1.1.4 Product Failures - Failures in Integrated Circuits; 1.1.5 Classification of Electrical Overstress Events; 1.1.6 Electrical Over-Current; 1.1.7 Electrical Over-Voltage; 1.1.8 Electrical Over-Power
1.2 De-Mystifying Electrical Overstress1.2.1 Electrical Overstress Events; 1.3 Sources of Electrical Overstress; 1.3.1 Sources of Electrical Overstress in Manufacturing Environment; 1.3.2 Sources of Electrical Overstress in Production Environments; 1.4 Misconceptions of Electrical Overstress; 1.5 Minimization of Electrical Overstress Sources; 1.6 Mitigation of Electrical Overstress; 1.7 Signs of Electrical Overstress Damage; 1.7.1 Signs of Electrical Overstress Damage - The Electrical Signature; 1.7.2 Signs of Electrical Overstress Damage - The Visual Signature 1.8 Electrical Overstress and Electrostatic Discharge1.8.1 Comparison of High and Low Current EOS versus ESD Events; 1.8.2 Electrical Overstress and Electrostatic Discharge Differences; 1.8.3 Electrical Overstress and Electrostatic Discharge Similarities; 1.8.4 Comparison of EOS versus ESDWaveforms; 1.8.5 Comparison of EOS versus ESD Event Failure Damage; 1.9 Electromagnetic Interference; 1.9.1 Electrical Overstress Induced Electromagnetic Interference; 1.10 Electromagnetic Compatibility; 1.11 Thermal Over-Stress; 1.11.1 Electrical Overstress and Thermal Overstress 1.11.2 Temperature Dependent Electrical Overstress1.11.3 Electrical Overstress and Melting Temperature; 1.12 Reliability Technology Scaling; 1.12.1 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.12.2 The Shrinking Reliability Design Box; 1.12.3 The Shrinking Electrostatic Discharge Design Box; 1.12.4 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.13 Safe Operating Area; 1.13.1 Electrical Safe Operating Area; 1.13.2 Thermal Safe Operating Area; 1.13.3 Transient Safe Operating Area; 1.14 Summary and Closing Comments; References 2 Fundamentals of EOS Models2.1 Thermal Time Constants; 2.1.1 The Thermal Diffusion Time; 2.1.2 The Adiabatic Regime Time Constant; 2.1.3 The Thermal Diffusion Regime Time Constant; 2.1.4 The Steady State Regime Time Constant; 2.2 Pulse Event Time Constants; 2.2.1 The ESD HBM Pulse Time Constant; 2.2.2 The ESD MM Pulse Time Constant; 2.2.3 The ESD Charged Device Model Pulse Time Constant; 2.2.4 The ESD Pulse Time Constant - Transmission Line Pulse; 2.2.5 The ESD Pulse Time Constant - Very Fast Transmission Line Pulse; 2.2.6 The IEC 61000-4-2 Pulse Time Constant 2.2.7 The Cable Discharge Event Pulse Time Constant |
| Record Nr. | UNINA-9910810547003321 |
|
Voldman Steven H
|
||
| Chichester, West Sussex, U.K., : John Wiley & Sons Inc., 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electrical, electronics, and digital hardware essentials for scientists and engineers / / Ed Lipiansky
| Electrical, electronics, and digital hardware essentials for scientists and engineers / / Ed Lipiansky |
| Autore | Lipiansky Ed |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, 2013 |
| Descrizione fisica | 1 online resource (665 p.) |
| Disciplina | 621.3 |
| Collana | IEEE Press series on microelectronic systems |
| Soggetto topico |
Electronic circuits
Electronic apparatus and appliances |
| ISBN |
1-118-41454-3
1-283-83507-X 1-118-41452-7 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Preface xvii -- About the Author xix -- 1 From the Bottom Up: Voltages, Currents, and Electrical Components 1 -- 1.1 An Introduction to Electric Charges and Atoms 1 -- 1.2 Electric DC Voltage and Current Sources 3 -- 1.3 Electric Components: Resistors, Inductors, and Capacitors 12 -- 1.4 Ohm's Law, Power Delivered and Power Consumed 25 -- 1.5 Capacitors 33 -- 1.6 Inductors 44 -- 1.7 Kirchhoff's Voltage Law (KVL) and Kirchhoff's Current Law (KCL) 73 -- 1.8 Summary 87 -- 2 Alternating Current Circuits 98 -- 2.1 AC Voltage and Current Sources, Root Mean Square Values (RMS), and Power 98 -- 2.2 Sinusoidal Steady State: Time and Frequency Domains 111 -- 2.3 Time Domain Equations: Frequency Domain Impedance and Phasors 123 -- 2.4 Power in AC Circuits 136 -- 2.5 Dependent Voltage and Current Sources 145 -- 2.6 Summary of Key Points 149 -- 3 Circuit Theorems and Methods of Circuit Analysis 155 -- 3.1 Introduction 155 -- 3.2 The Superposition Method 156 -- 3.3 The Thévenin Method 165 -- 3.4 Norton's Method 172 -- 3.5 The Mesh Method of Analysis 179 -- 3.6 The Nodal Method of Analysis 199 -- 3.7 Which One Is the Best Method? 210 -- 3.8 Using all the Methods 213 -- 3.9 Summary and Conclusions 225 -- 4 First- and Second-Order Circuits under Sinusoidal and Step Excitations 233 -- 4.1 Introduction 233 -- 4.2 The First-Order RC Low-Pass Filter (LPF) 235 -- 4.3 The First-Order RC High-Pass Filter (HPF) 252 -- 4.4 Second-Order Circuits 265 -- 4.5 Series RLC Second-Order Circuit 266 -- 4.6 Second-Order Circuit in Sinusoidal Steady State: Bode Plots 275 -- 4.7 Drawing the Second-Order Bode Plots Using Asymptotic Approximations 278 -- 4.8 Summary 279 -- 5 The Operational Amplifi er as a Circuit Element 287 -- 5.1 Introduction to the Operational Amplifier 287 -- 5.2 Ideal and Real Op Amps 288 -- 5.3 Brief Defi nition of Linear Amplifiers 290 -- 5.4 Linear Applications of Op Amps 294 -- 5.5 Op Amps Nonlinear Applications 331 -- 5.6 Operational Amplifi ers Nonidealities 341 -- 5.7 Op Amp Selection Criteria 343.
5.8 Summary 347 -- 6 Electronic Devices: Diodes, BJTs, and MOSFETs 354 -- 6.1 Introduction to Electronic Devices 354 -- 6.2 The Ideal Diode 355 -- 6.3 Bipolar Junction Transistors (BJT) 374 -- 6.4 Metal Oxide Field Effect Transistor (MOSFET) 420 -- 6.5 Summary 443 -- 7 Combinational Circuits 456 -- 7.1 Introduction to Digital Circuits 456 -- 7.2 Binary Numbers: a Quick Introduction 456 -- 7.3 Boolean Algebra 460 -- 7.4 Minterms: Standard or Canonical Sum of Products (SOP) Form 467 -- 7.5 Maxterms: Standard or Canonical Product of Sums (POS) Form 472 -- 7.6 Karnaugh Maps and Design Examples 473 -- 7.7 Product of Sums Simplifi cations 490 -- 7.8 Don't Care Conditions 491 -- 7.9 Logic Gates: Electrical and Timing Characteristics 495 -- 7.10 Summary 500 -- 8 Digital Design Building Blocks and More Advanced Combinational Circuits 503 -- 8.1 Combinational Circuits with More than One Output 503 -- 8.2 Decoders and Encoders 510 -- 8.3 Multiplexers and Demultiplexers (MUXes and DEMUXes) 519 -- 8.4 Signed and Unsigned Binary Numbers 527 -- 8.5 Arithmetic Circuits: Half-Adders (HA) and Full-Adders (FA) 533 -- 8.6 Carry Look Ahead (CLA) or Fast Carry Generation 543 -- 8.7 Some Short-Hand Notation for Large Logic Blocks 546 -- 8.8 Summary 547 -- 9 Sequential Logic and State Machines 550 -- 9.1 Introduction 550 -- 9.2 Latches and Flip-Flops (FF) 552 -- 9.3 Timing Characteristics of Sequential Elements 571 -- 9.4 Simple State Machines 574 -- 9.5 Synchronous State Machines General Considerations 592 -- 9.6 Summary 599 -- 10 A Simple CPU Design 603 -- 10.1 Our Simple CPU Instruction Set 603 -- 10.2 Instruction Set Details: Register Transfer Language (RTL) 605 -- 10.3 Building a Simple CPU: A Bottom-Up Approach 607 -- 10.4 Data Path Architecture: Putting the Logic Blocks Together 615 -- 10.5 The Simple CPU Controller 620 -- 10.6 CPU Timing Requirements 626 -- 10.7 Other System Pieces: Clock, Reset and Power Decoupling 628 -- 10.8 Summary 633 -- Further Reading 633 -- Problems 633 -- Index 637. |
| Record Nr. | UNINA-9910877642503321 |
|
Lipiansky Ed
|
||
| Hoboken, N.J., : Wiley, 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Electrical, electronics, and digital hardware essentials for scientists and engineers / / Ed Lipiansky
| Electrical, electronics, and digital hardware essentials for scientists and engineers / / Ed Lipiansky |
| Autore | Lipiansky Ed |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : Wiley, , 2012 |
| Descrizione fisica | 1 online resource (665 p.) |
| Disciplina | 621.381 |
| Collana | IEEE press series on microelectronic systems |
| Soggetto topico |
Electronic circuits
Electronic apparatus and appliances |
| ISBN |
1-118-41454-3
1-283-83507-X 1-118-41452-7 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Preface xvii -- About the Author xix -- 1 From the Bottom Up: Voltages, Currents, and Electrical Components 1 -- 1.1 An Introduction to Electric Charges and Atoms 1 -- 1.2 Electric DC Voltage and Current Sources 3 -- 1.3 Electric Components: Resistors, Inductors, and Capacitors 12 -- 1.4 Ohm's Law, Power Delivered and Power Consumed 25 -- 1.5 Capacitors 33 -- 1.6 Inductors 44 -- 1.7 Kirchhoff's Voltage Law (KVL) and Kirchhoff's Current Law (KCL) 73 -- 1.8 Summary 87 -- 2 Alternating Current Circuits 98 -- 2.1 AC Voltage and Current Sources, Root Mean Square Values (RMS), and Power 98 -- 2.2 Sinusoidal Steady State: Time and Frequency Domains 111 -- 2.3 Time Domain Equations: Frequency Domain Impedance and Phasors 123 -- 2.4 Power in AC Circuits 136 -- 2.5 Dependent Voltage and Current Sources 145 -- 2.6 Summary of Key Points 149 -- 3 Circuit Theorems and Methods of Circuit Analysis 155 -- 3.1 Introduction 155 -- 3.2 The Superposition Method 156 -- 3.3 The Thévenin Method 165 -- 3.4 Norton's Method 172 -- 3.5 The Mesh Method of Analysis 179 -- 3.6 The Nodal Method of Analysis 199 -- 3.7 Which One Is the Best Method? 210 -- 3.8 Using all the Methods 213 -- 3.9 Summary and Conclusions 225 -- 4 First- and Second-Order Circuits under Sinusoidal and Step Excitations 233 -- 4.1 Introduction 233 -- 4.2 The First-Order RC Low-Pass Filter (LPF) 235 -- 4.3 The First-Order RC High-Pass Filter (HPF) 252 -- 4.4 Second-Order Circuits 265 -- 4.5 Series RLC Second-Order Circuit 266 -- 4.6 Second-Order Circuit in Sinusoidal Steady State: Bode Plots 275 -- 4.7 Drawing the Second-Order Bode Plots Using Asymptotic Approximations 278 -- 4.8 Summary 279 -- 5 The Operational Amplifi er as a Circuit Element 287 -- 5.1 Introduction to the Operational Amplifier 287 -- 5.2 Ideal and Real Op Amps 288 -- 5.3 Brief Defi nition of Linear Amplifiers 290 -- 5.4 Linear Applications of Op Amps 294 -- 5.5 Op Amps Nonlinear Applications 331 -- 5.6 Operational Amplifi ers Nonidealities 341 -- 5.7 Op Amp Selection Criteria 343.
5.8 Summary 347 -- 6 Electronic Devices: Diodes, BJTs, and MOSFETs 354 -- 6.1 Introduction to Electronic Devices 354 -- 6.2 The Ideal Diode 355 -- 6.3 Bipolar Junction Transistors (BJT) 374 -- 6.4 Metal Oxide Field Effect Transistor (MOSFET) 420 -- 6.5 Summary 443 -- 7 Combinational Circuits 456 -- 7.1 Introduction to Digital Circuits 456 -- 7.2 Binary Numbers: a Quick Introduction 456 -- 7.3 Boolean Algebra 460 -- 7.4 Minterms: Standard or Canonical Sum of Products (SOP) Form 467 -- 7.5 Maxterms: Standard or Canonical Product of Sums (POS) Form 472 -- 7.6 Karnaugh Maps and Design Examples 473 -- 7.7 Product of Sums Simplifi cations 490 -- 7.8 Don't Care Conditions 491 -- 7.9 Logic Gates: Electrical and Timing Characteristics 495 -- 7.10 Summary 500 -- 8 Digital Design Building Blocks and More Advanced Combinational Circuits 503 -- 8.1 Combinational Circuits with More than One Output 503 -- 8.2 Decoders and Encoders 510 -- 8.3 Multiplexers and Demultiplexers (MUXes and DEMUXes) 519 -- 8.4 Signed and Unsigned Binary Numbers 527 -- 8.5 Arithmetic Circuits: Half-Adders (HA) and Full-Adders (FA) 533 -- 8.6 Carry Look Ahead (CLA) or Fast Carry Generation 543 -- 8.7 Some Short-Hand Notation for Large Logic Blocks 546 -- 8.8 Summary 547 -- 9 Sequential Logic and State Machines 550 -- 9.1 Introduction 550 -- 9.2 Latches and Flip-Flops (FF) 552 -- 9.3 Timing Characteristics of Sequential Elements 571 -- 9.4 Simple State Machines 574 -- 9.5 Synchronous State Machines General Considerations 592 -- 9.6 Summary 599 -- 10 A Simple CPU Design 603 -- 10.1 Our Simple CPU Instruction Set 603 -- 10.2 Instruction Set Details: Register Transfer Language (RTL) 605 -- 10.3 Building a Simple CPU: A Bottom-Up Approach 607 -- 10.4 Data Path Architecture: Putting the Logic Blocks Together 615 -- 10.5 The Simple CPU Controller 620 -- 10.6 CPU Timing Requirements 626 -- 10.7 Other System Pieces: Clock, Reset and Power Decoupling 628 -- 10.8 Summary 633 -- Further Reading 633 -- Problems 633 -- Index 637. |
| Record Nr. | UNINA-9910141368203321 |
|
Lipiansky Ed
|
||
| Hoboken, New Jersey : , : Wiley, , 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
