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Communicating process architectures 2005 [[electronic resource] ] : WoTUG-28 : proceedings of the 28th WoTUG Technical Meeting, 18-21 September 2005, Technische Universiteit Eindhoven, The Netherlands / / ed. by Jan F. Broenink ... [et al.]
| Communicating process architectures 2005 [[electronic resource] ] : WoTUG-28 : proceedings of the 28th WoTUG Technical Meeting, 18-21 September 2005, Technische Universiteit Eindhoven, The Netherlands / / ed. by Jan F. Broenink ... [et al.] |
| Pubbl/distr/stampa | Amsterdam ; ; Washington, D.C., : IOS Press, c2005 |
| Descrizione fisica | 1 online resource (416 p.) |
| Disciplina | 004.35 |
| Altri autori (Persone) | BroeninkJan F |
| Collana | Concurrent systems engineering series |
| Soggetto topico |
Parallel processing (Electronic computers)
occam (Computer program language) Transputers Computer architecture |
| ISBN |
1-280-50507-9
9786610505074 1-4237-9735-3 1-60750-144-9 600-00-0366-8 1-60129-124-8 |
| Classificazione |
54.31
54.51 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Title page; Preface; Programme Committee; Contents; Interfacing with Honeysuckle by Formal Contract; Groovy Parallel! A Return to the Spirit of occam?; On Issues of Constructing an Exception Handling Mechanism for CSP-Based Process-Oriented Concurrent Software; Automatic Handel-C Generation from MATLAB and Simulink for Motion Control with an FPGA; JCSP-Poison: Safe Termination of CSP Process Networks; jcsp.mobile: A Package Enabling Mobile Processes and Channels; CSP++: How Faithful to CSPm?; Fast Data Sharing within a Distributed, Multithreaded Control Framework for Robot Teams
Improving TCP/IP Multicasting with Message SegmentationLazy Cellular Automata with Communicating Processes; A Unifying Theory of True Concurrency Based on CSP and Lazy Observation; The Architecture of the Minimum intrusion Grid (MiG); Verification of JCSP Programs; Architecture Design Space Exploration for Streaming Applications through Timing Analysis; A Foreign-Function Interface Generator for occam-pi; Interfacing C and occam-pi; Interactive Computing with the Minimum intrusion Grid (MiG); High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog Mobile Barriers for occam-pi: Semantics, Implementation and ApplicationException Handling Mechanism in Communicating Threads for Java; R16: A New Transputer Design for FPGAs; Towards Strong Mobility in the Shared Source CLI; gCSP occam Code Generation for RMoX; Assessing Application Performance in Degraded Network Environments: An FPGA-Based Approach; Communication and Synchronization in the Cell Processor (Invited Talk); Homogeneous Multiprocessing for Consumer Electronics (Invited Talk); Handshake Technology: High Way to Low Power (Invited Talk) If Concurrency in Software Is So Simple, Why Is It So Hard? (Invited Talk)Author Index |
| Record Nr. | UNINA-9910784143503321 |
| Amsterdam ; ; Washington, D.C., : IOS Press, c2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Communicating process architectures 2008 [[electronic resource] ] : WoTUG-31 / / edited by Peter H. Welch ... [et al.]
| Communicating process architectures 2008 [[electronic resource] ] : WoTUG-31 / / edited by Peter H. Welch ... [et al.] |
| Pubbl/distr/stampa | Amsterdam ; ; Washington, D.C., : IOS Press, c2008 |
| Descrizione fisica | 1 online resource (472 p.) |
| Disciplina |
004.35
158.1 |
| Altri autori (Persone) | WelchP. H |
| Soggetto topico |
Computer architecture
occam (Computer program language) Parallel processing (Electronic computers) Transputers |
| ISBN |
661196861X
1-281-96861-7 9786611968618 1-4416-0157-0 600-00-1186-5 1-60750-368-9 |
| Classificazione |
54.31
54.51 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Title page; Preface; Editorial Board; Reviewing Committee; Contents; Part A. Invited Speakers; Types, Orthogonality and Genericity: Some Tools for Communicating Process Architectures; How to Soar with CSP; Part B. Conference Papers; A CSP Model for Mobile Channels; Communicating Scala Objects; Combining EDF Scheduling with occam Using the Toc Programming Language; Communicating Haskell Processes: Composable Explicit Concurrency Using Monads; Two-Way Protocols for occam-pi; Prioritized Service Architecture: Refinement and Visual Design; Experiments in Translating CSP--B to Handel-C
FPGA Based Control of a Production Cell SystemShared-Clock Methodology for Time-Triggered Multi-Cores; Transfer Request Broker: Resolving Input-Output Choice; Mechanical Verification of a Two-Way Sliding Window Protocol; RRABP: Point-to-Point Communication over Unreliable Components; IC2IC: a Lightweight Serial Interconnect Channel for Multiprocessor Networks; Asynchronous Active Objects in Java; JCSPre: the Robot Edition to Control LEGO NXT Robots; A Critique of JCSP Networking; Virtual Machine Based Debugging for occam-pi; Process-Oriented Collective Operations Representation and Implementation of CSP and VCR TracesCSPBuilder - CSP Based Scientific Workflow Modelling; Visual Process-Oriented Programming for Robotics; Solving the Santa Claus Problem: a Comparison of Various Concurrent Programming Techniques; Mobile Agents and Processes Using Communicating Process Architectures; YASS: a Scaleable Sensornet Simulator for Large Scale Experimentation; Modelling a Multi-Core Media Processor Using JCSP; Part C. Fringe Presentation Abstracts; How to Make a Process Invisible; Designing Animation Facilities for gCSP; Tock: One Year On Introducing JCSP Networking 2.0Mobile Processes in an Ant Simulation; Santa Claus - with Mobile Reindeer and Elves; Subject Index; Author Index |
| Record Nr. | UNINA-9910782442603321 |
| Amsterdam ; ; Washington, D.C., : IOS Press, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Conference proceedings / / International Symposium on Computer Architecture
| Conference proceedings / / International Symposium on Computer Architecture |
| Pubbl/distr/stampa | [Los Angeles], : ACM, ©1983-©1988 |
| Disciplina | 004.2/2 |
| Soggetto topico |
Computer architecture
Computerarchitectuur |
| Soggetto genere / forma | Conference papers and proceedings. |
| Classificazione | 54.31 |
| Formato | Materiale a stampa |
| Livello bibliografico | Periodico |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
Annual International Symposium on Computer Architecture conference proceedings
Proceedings of the ... Annual International Symposium on Computer architecture |
| Record Nr. | UNISA-996203170503316 |
| [Los Angeles], : ACM, ©1983-©1988 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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High Performance Embedded Architectures and Compilers [[electronic resource] ] : First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings / / edited by Tom Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer
| High Performance Embedded Architectures and Compilers [[electronic resource] ] : First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings / / edited by Tom Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer |
| Edizione | [1st ed. 2005.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 |
| Descrizione fisica | 1 online resource (XIV, 318 p.) |
| Disciplina | 004 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer arithmetic and logic units
Computer systems Compilers (Computer programs) Computer input-output equipment Logic design Microprocessors Computer architecture Arithmetic and Logic Structures Computer System Implementation Compilers and Interpreters Input/Output and Data Communications Logic Design Processor Architectures |
| Classificazione | 54.31 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications -- Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges -- Software Defined Radio – A High Performance Embedded Challenge -- I Analysis and Evaluation Techniques -- A Practical Method for Quickly Evaluating Program Optimizations -- Efficient Sampling Startup for Sampled Processor Simulation -- Enhancing Network Processor Simulation Speed with Statistical Input Sampling -- II Novel Memory and Interconnect Architectures -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation -- Streaming Sparse Matrix Compression/Decompression -- XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs -- III Security Architecture -- Memory-Centric Security Architecture -- A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management -- Arc3D: A 3D Obfuscation Architecture -- IV Novel Compiler and Runtime Techniques -- Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations -- Induction Variable Analysis with Delayed Abstractions -- Garbage Collection Hints -- V DomainSpecificArchitectures -- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors -- Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture -- A Single (Unified) Shader GPU Microarchitecture for Embedded Systems -- A Low-Power DSP-Enhanced 32-Bit EISC Processor. |
| Record Nr. | UNISA-996465731103316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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High performance embedded architectures and compilers : first international conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005 : proceedings / / Tom Conte ... [et al.] (eds.)
| High performance embedded architectures and compilers : first international conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005 : proceedings / / Tom Conte ... [et al.] (eds.) |
| Edizione | [1st ed. 2005.] |
| Pubbl/distr/stampa | Berlin, : Springer, 2005 |
| Descrizione fisica | 1 online resource (XIV, 318 p.) |
| Disciplina | 004 |
| Altri autori (Persone) | ConteTom |
| Collana | Lecture notes in computer science |
| Soggetto topico |
Embedded computer systems
High performance computing Compilers (Computer programs) Computer architecture |
| Classificazione | 54.31 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications -- Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges -- Software Defined Radio – A High Performance Embedded Challenge -- I Analysis and Evaluation Techniques -- A Practical Method for Quickly Evaluating Program Optimizations -- Efficient Sampling Startup for Sampled Processor Simulation -- Enhancing Network Processor Simulation Speed with Statistical Input Sampling -- II Novel Memory and Interconnect Architectures -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation -- Streaming Sparse Matrix Compression/Decompression -- XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs -- III Security Architecture -- Memory-Centric Security Architecture -- A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management -- Arc3D: A 3D Obfuscation Architecture -- IV Novel Compiler and Runtime Techniques -- Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations -- Induction Variable Analysis with Delayed Abstractions -- Garbage Collection Hints -- V DomainSpecificArchitectures -- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors -- Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture -- A Single (Unified) Shader GPU Microarchitecture for Embedded Systems -- A Low-Power DSP-Enhanced 32-Bit EISC Processor. |
| Altri titoli varianti | HiPEAC 2005 |
| Record Nr. | UNINA-9910484308803321 |
| Berlin, : Springer, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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