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Test Generation of Crosstalk Delay Faults in VLSI Circuits / / by S. Jayanthy, M.C. Bhuvaneswari
Test Generation of Crosstalk Delay Faults in VLSI Circuits / / by S. Jayanthy, M.C. Bhuvaneswari
Autore Jayanthy S
Edizione [1st ed. 2019.]
Pubbl/distr/stampa Singapore : , : Springer Singapore : , : Imprint : Springer, , 2019
Descrizione fisica 1 online resource (161 pages)
Disciplina 621.3950287
Soggetto topico Electronic circuits
Microprogramming 
Computer software—Reusability
Logic design
Circuits and Systems
Control Structures and Microprogramming
Performance and Reliability
Logic Design
ISBN 981-13-2493-X
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Chapter 1. Background and Review of Crosstalk Delay Fault Models and the Crosstalk Effects -- Chapter 2. Review of Test Generation Techniques for Crosstalk Delay Faults -- Chapter 3. An Automatic Test Pattern Generation Method for Crosstalk Delay Faults Using Modified PODEM and FAN Algorithm -- Chapter 4. An Automatic Test Pattern Generation Method for Crosstalk Delay Faults using Single-Objective Genetic Algorithm -- Chapter 5. An Automatic Test Pattern Generation Method for Crosstalk Delay Faults Using Single-Objective Particle Swarm Optimization -- Chapter 6. Simulation of Asynchronous Sequential Circuits using Fuzzy Delay Model -- Chapter 7. Simulation Based Test Generation for Crosstalk Delay Faults in Asynchronous Sequential Circuits.
Record Nr. UNINA-9910350312403321
Jayanthy S  
Singapore : , : Springer Singapore : , : Imprint : Springer, , 2019
Materiale a stampa
Lo trovi qui: Univ. Federico II
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VLSI Test Symposium (VTS 2000): 18th IEEE
VLSI Test Symposium (VTS 2000): 18th IEEE
Pubbl/distr/stampa [Place of publication not identified], : IEEE Computer Society Press, 2000
Descrizione fisica 1 online resource (478 pages) : illustrations
Disciplina 621.3950287
Soggetto topico Integrated circuits - Very large scale integration - Testing
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Foreword -- Organizing Committee -- Steering Committe -- Program Committee -- Reviewers -- VTS '99 Best Paper Award -- VTS '99 Best Panel Award -- Test Technology Technical Council -- Test Technology Education Program: Overview Tutorials -- Plenary Session -- Welcome Message -- Adit Singh -- Keynote Address: "Optical Internet: Industry Challenge" -- Brian McFadden -- Program Introduction -- Joan Figueras -- Invited Presentation: "Wall Street Perspective on System-on-Chip and Test Technology" -- Erach D. Desai.
Record Nr. UNISA-996218755803316
[Place of publication not identified], : IEEE Computer Society Press, 2000
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
VLSI Test Symposium (VTS 2000): 18th IEEE
VLSI Test Symposium (VTS 2000): 18th IEEE
Pubbl/distr/stampa [Place of publication not identified], : IEEE Computer Society Press, 2000
Descrizione fisica 1 online resource (478 pages) : illustrations
Disciplina 621.3950287
Soggetto topico Integrated circuits - Very large scale integration - Testing
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Foreword -- Organizing Committee -- Steering Committe -- Program Committee -- Reviewers -- VTS '99 Best Paper Award -- VTS '99 Best Panel Award -- Test Technology Technical Council -- Test Technology Education Program: Overview Tutorials -- Plenary Session -- Welcome Message -- Adit Singh -- Keynote Address: "Optical Internet: Industry Challenge" -- Brian McFadden -- Program Introduction -- Joan Figueras -- Invited Presentation: "Wall Street Perspective on System-on-Chip and Test Technology" -- Erach D. Desai.
Record Nr. UNINA-9910872661203321
[Place of publication not identified], : IEEE Computer Society Press, 2000
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui