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Communicating embedded systems [[electronic resource] ] : software and design : formal methods / / edited by Claude Jard, Olivier H. Roux
Communicating embedded systems [[electronic resource] ] : software and design : formal methods / / edited by Claude Jard, Olivier H. Roux
Edizione [1st edition]
Pubbl/distr/stampa London, : ISTE
Descrizione fisica 1 online resource (275 p.)
Disciplina 621.39/2
Altri autori (Persone) JardClaude
RouxOlivier H
Collana ISTE
Soggetto topico Embedded computer systems - Programming
Embedded computer systems - Design and construction
Computer software - Development
Formal methods (Computer science)
ISBN 1-118-55818-9
1-118-60009-6
1-118-60012-6
1-299-18745-5
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Cover; Communicating Embedded Systems; Title Page; Copyright Page; Table of Contents; Preface; Chapter 1. Models for Real-Time Embedded Systems; 1.1. Introduction; 1.1.1. Model-checking and control problems; 1.1.2. Timed models; 1.2. Notations, languages and timed transition systems; 1.3. Timed models; 1.3.1. Timed Automata; 1.3.2. Time Petri nets; 1.3.2.1. T-time Petri nets; 1.3.2.2. Timed-arc petri nets; 1.3.3. Compared expressiveness of several classes of timed models; 1.3.3.1. Bisimulation and expressiveness of timed models; 1.3.3.2. Compared expressiveness of different classes of TPN
1.3.3.3. Compared expressiveness of TA, TPN, and TAPN1.4. Models with stopwatches; 1.4.1. Formal models for scheduling aspects; 1.4.1.1. Automata and scheduling; 1.4.1.2. Time Petri nets and scheduling; 1.4.2. Stopwatch automata; 1.4.3. Scheduling time Petri nets; 1.4.4. Decidability results for stopwatch models; 1.5. Conclusion; 1.6. Bibliography; Chapter 2. Timed Model-Checking; 2.1. Introduction; 2.2. Timed models; 2.2.1. Timed transition system; 2.2.2. Timed automata; 2.2.3. Other models; 2.3. Timed logics; 2.3.1. Temporal logics CTL and LTL; 2.3.2. Timed extensions; 2.3.2.1. Timed CTL
2.3.2.2. Timed LTL2.4. Timed model-checking; 2.4.1. Model-checking LTL and CTL (untimed case); 2.4.2. Region automaton; 2.4.3. Model-checking TCTL; 2.4.4. Model-checking MTL; 2.4.5. Efficient model-checking; 2.4.6. Model-checking in practice; 2.5. Conclusion; 2.6. Bibliography; Chapter 3. Control of Timed Systems; 3.1. Introduction; 3.1.1. Verification of timed systems; 3.1.2. The controller synthesis problem; 3.1.3. From control to game; 3.1.4. Game objectives; 3.1.5. Varieties of untimed games; 3.2. Timed games; 3.2.1. Timed game automata; 3.2.2. Strategies and course of the game
3.2.2.1. The course of a timed game3.2.2.2. Strategies; 3.3. Computation of winning states and strategies; 3.3.1. Controllable predecessors; 3.3.2. Symbolic operators; 3.3.3. Symbolic computation of winning states; 3.3.4. Synthesis of winning strategies; 3.4. Zeno strategies; 3.5. Implementability; 3.5.1. Hybrid automata; 3.5.2. On the existence of non-implementable continuous controllers; 3.5.3. Recent results and open problems; 3.6. Specification of control objectives; 3.7. Optimal control; 3.7.1. TA with costs; 3.7.2. Optimal cost in timed games; 3.7.3. Computation of the optimal cost
3.7.4. Recent results and open problems3.8. Efficient algorithms for controller synthesis; 3.8.1. On-the-fly algorithms; 3.8.2. Recent results and open problems; 3.9. Partial observation; 3.10. Changing game rules...; 3.11. Bibliography; Chapter 4. Fault Diagnosis of Timed Systems; 4.1. Introduction; 4.2. Notations; 4.2.1. Timed words and timed languages; 4.2.2. Timed automata; 4.2.3. Region graph of a TA; 4.2.4. Product of TA; 4.2.5. Timed automata with faults; 4.3. Fault diagnosis problems; 4.3.1. Diagnoser; 4.3.2. The problems; 4.3.3. Necessary and sufficient condition for diagnosability
4.4. Fault diagnosis for discrete event systems
Record Nr. UNINA-9910138854403321
London, : ISTE
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Communicating embedded systems : software and design : formal methods / / edited by Claude Jard, Olivier H. Roux
Communicating embedded systems : software and design : formal methods / / edited by Claude Jard, Olivier H. Roux
Edizione [1st edition]
Pubbl/distr/stampa London, : ISTE
Descrizione fisica 1 online resource (275 p.)
Disciplina 621.39/2
Altri autori (Persone) JardClaude
RouxOlivier H
Collana ISTE
Soggetto topico Embedded computer systems - Programming
Embedded computer systems - Design and construction
Computer software - Development
Formal methods (Computer science)
ISBN 9781118558188
1118558189
9781118600092
1118600096
9781118600122
1118600126
9781299187450
1299187455
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Cover; Communicating Embedded Systems; Title Page; Copyright Page; Table of Contents; Preface; Chapter 1. Models for Real-Time Embedded Systems; 1.1. Introduction; 1.1.1. Model-checking and control problems; 1.1.2. Timed models; 1.2. Notations, languages and timed transition systems; 1.3. Timed models; 1.3.1. Timed Automata; 1.3.2. Time Petri nets; 1.3.2.1. T-time Petri nets; 1.3.2.2. Timed-arc petri nets; 1.3.3. Compared expressiveness of several classes of timed models; 1.3.3.1. Bisimulation and expressiveness of timed models; 1.3.3.2. Compared expressiveness of different classes of TPN
1.3.3.3. Compared expressiveness of TA, TPN, and TAPN1.4. Models with stopwatches; 1.4.1. Formal models for scheduling aspects; 1.4.1.1. Automata and scheduling; 1.4.1.2. Time Petri nets and scheduling; 1.4.2. Stopwatch automata; 1.4.3. Scheduling time Petri nets; 1.4.4. Decidability results for stopwatch models; 1.5. Conclusion; 1.6. Bibliography; Chapter 2. Timed Model-Checking; 2.1. Introduction; 2.2. Timed models; 2.2.1. Timed transition system; 2.2.2. Timed automata; 2.2.3. Other models; 2.3. Timed logics; 2.3.1. Temporal logics CTL and LTL; 2.3.2. Timed extensions; 2.3.2.1. Timed CTL
2.3.2.2. Timed LTL2.4. Timed model-checking; 2.4.1. Model-checking LTL and CTL (untimed case); 2.4.2. Region automaton; 2.4.3. Model-checking TCTL; 2.4.4. Model-checking MTL; 2.4.5. Efficient model-checking; 2.4.6. Model-checking in practice; 2.5. Conclusion; 2.6. Bibliography; Chapter 3. Control of Timed Systems; 3.1. Introduction; 3.1.1. Verification of timed systems; 3.1.2. The controller synthesis problem; 3.1.3. From control to game; 3.1.4. Game objectives; 3.1.5. Varieties of untimed games; 3.2. Timed games; 3.2.1. Timed game automata; 3.2.2. Strategies and course of the game
3.2.2.1. The course of a timed game3.2.2.2. Strategies; 3.3. Computation of winning states and strategies; 3.3.1. Controllable predecessors; 3.3.2. Symbolic operators; 3.3.3. Symbolic computation of winning states; 3.3.4. Synthesis of winning strategies; 3.4. Zeno strategies; 3.5. Implementability; 3.5.1. Hybrid automata; 3.5.2. On the existence of non-implementable continuous controllers; 3.5.3. Recent results and open problems; 3.6. Specification of control objectives; 3.7. Optimal control; 3.7.1. TA with costs; 3.7.2. Optimal cost in timed games; 3.7.3. Computation of the optimal cost
3.7.4. Recent results and open problems3.8. Efficient algorithms for controller synthesis; 3.8.1. On-the-fly algorithms; 3.8.2. Recent results and open problems; 3.9. Partial observation; 3.10. Changing game rules...; 3.11. Bibliography; Chapter 4. Fault Diagnosis of Timed Systems; 4.1. Introduction; 4.2. Notations; 4.2.1. Timed words and timed languages; 4.2.2. Timed automata; 4.2.3. Region graph of a TA; 4.2.4. Product of TA; 4.2.5. Timed automata with faults; 4.3. Fault diagnosis problems; 4.3.1. Diagnoser; 4.3.2. The problems; 4.3.3. Necessary and sufficient condition for diagnosability
4.4. Fault diagnosis for discrete event systems
Record Nr. UNINA-9910820091003321
London, : ISTE
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Correct Hardware Design and Verification Methods [[electronic resource] ] : IFIP WG 10.2 Advanced Research Working Conference, CHARME'93, Arles, France, May 24-26, 1993. Proceedings / / edited by George J. Milne, Laurence Pierre
Correct Hardware Design and Verification Methods [[electronic resource] ] : IFIP WG 10.2 Advanced Research Working Conference, CHARME'93, Arles, France, May 24-26, 1993. Proceedings / / edited by George J. Milne, Laurence Pierre
Edizione [1st ed. 1993.]
Pubbl/distr/stampa Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1993
Descrizione fisica 1 online resource (IX, 275 p.)
Disciplina 621.39/2
Collana Lecture Notes in Computer Science
Soggetto topico Computers
Computer hardware
Microprogramming 
Arithmetic and logic units, Computer
Computer memory systems
Input-output equipment (Computers)
Theory of Computation
Computer Hardware
Control Structures and Microprogramming
Arithmetic and Logic Structures
Memory Structures
Input/Output and Data Communications
ISBN 3-540-70655-0
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto A graph-based method for timing diagrams representation and verification -- A Petri Net approach for the analysis of VHDL descriptions -- Temporal analysis of time bounded digital systems -- Strongly-typed theory of structures and behaviours -- Verification and diagnosis of digital systems by ternary reasoning -- Logic verification of incomplete functions and design error location -- A methodology for system-level design for verifiability -- Algebraic models and the correctness of microprocessors -- Combining symbolic evaluation and object oriented approach for verifying processor-like architectures at the RT-level -- A theory of generic interpreters -- Towards verifying large(r) systems: A strategy and an experiment -- Advancements in symbolic traversal techniques -- Automatic verification of speed-independent circuit designs using the Circal system -- Correct compilation of specifications to deterministic asynchronous circuits -- DDD-FM9001: Derivation of a verified microprocessor -- Calculational derivation of a counter with bounded response time -- Towards a provably correct hardware implementation of occam -- Rewriting with constraints in T-ruby -- Embedding hardware verification within a commercial design framework -- An approach to formalization of data flow graphs.
Record Nr. UNISA-996466086203316
Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1993
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari
Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari
Autore Patmaönåapaön òTi. åAr
Pubbl/distr/stampa Piscataway, New Jersey : , : IEEE Press, , c2004
Descrizione fisica 1 PDF (xii, 455 pages) : illustrations
Disciplina 621.39/2
Altri autori (Persone) Tripura SundariB. Bala
Soggetto topico Verilog (Computer hardware description language)
Electrical Engineering
Electrical & Computer Engineering
Engineering & Applied Sciences
Soggetto non controllato Electrical and Electronics Engineering
ISBN 1-280-55707-9
9786610557073
0-471-72299-5
0-471-72300-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto PREFACE -- ACKNOWLEDGEMENTS -- 1 INTRODUCTION TO VLSI DESIGN -- 1.1 INTRODUCTION -- 1.2 CONVENTIONAL APPROACH TO DIGITAL DESIGN -- 1.3 VLSI DESIGN -- 1.4 ASIC DESIGN FLOW -- 1.5 ROLE OF HDL -- 2 INTRODUCTION TO VERILOG -- 2.1 VERILOG AS AN HDL -- 2.2 LEVELS OF DESIGN DESCRIPTION -- 2.3 CONCURRENCY -- 2.4 SIMULATION AND SYNTHESIS -- 2.5 FUNCTIONAL VERIFICATION -- 2.6 SYSTEM TASKS -- 2.7 PROGRAMMING LANGUAGE INTERFACE (PLI) -- 2.8 MODULE -- 2.9 SIMULATION AND SYNTHESIS TOOLS -- 2.10 TEST BENCHES -- 3 LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG -- 3.1 INTRODUCTION -- 3.2 KEYWORDS -- 3.3 IDENTIFIERS -- 3.4 WHITE SPACE CHARACTERS -- 3.5 COMMENTS -- 3.6 NUMBERS -- 3.7 STRINGS -- 3.8 LOGIC VALUES -- 3.9 STRENGTHS -- 3.10 DATA TYPES -- 3.11 SCALARS AND VECTORS -- 3.12 PARAMETERS -- 3.13 MEMORY -- 3.14 OPERATORS -- 3.15 SYSTEM TASKS -- 3.16 EXERCISES -- 4 GATE LEVEL MODELING - 1 -- 4.1 INTRODUCTION -- 4.2 AND GATE PRIMITIVE -- 4.3 MODULE STRUCTURE -- 4.4 OTHER GATE PRIMITIVES -- 4.5 ILLUSTRATIVE EXAMPLES -- 4.6 TRI-STATE GATES -- 4.7 ARRAY OF INSTANCES OF PRIMITIVES -- 4.8 ADDITIONAL EXAMPLES -- 4.9 EXERCISES -- 5 GATE LEVEL MODELING - 2 -- 5.1 INTRODUCTION -- 5.2 DESIGN OF FLIP-FLOPS WITH GATE PRIMITIVES -- 5.3 DELAYS -- 5.4 STRENGTHS AND CONTENTION RESOLUTION -- 5.5 NET TYPES -- 5.6 DESIGN OF BASIC CIRCUITS -- 5.7 EXERCISES -- 6 MODELING AT DATA FLOW LEVEL -- 6.1 INTRODUCTION -- 6.2 CONTINUOUS ASSIGNMENT STRUCTURES -- 6.3 DELAYS AND CONTINUOUS ASSIGNMENTS -- 6.4 ASSIGNMENT TO VECTORS -- 6.5 OPERATORS -- 6.6 ADDITIONAL EXAMPLES -- 6.7 EXERCISES -- 7 BEHAVIORAL MODELING - 1 -- 7.1 INTRODUCTION -- 7.2 OPERATIONS AND ASSIGNMENTS.0 -- 7.3 FUNCTIONAL BIFURCATION.1 -- 7.4 INITIAL CONSTRUCT -- 7.5 ALWAYS CONSTRUCT -- 7.6 EXAMPLES -- 7.7 ASSIGNMENTS WITH DELAYS -- 7.8 wait CONSTRUCT -- 7.9 MULTIPLE ALWAYS BLOCKS -- 7.10 DESIGNS AT BEHAVIORAL LEVEL -- 7.11 BLOCKING AND NONBLOCKING ASSIGNMENTS -- 7.12 THE case STATEMENT -- 7.13 SIMULATION FLOW -- 7.14 EXERCISES -- 8 BEHAVIORAL MODELING II.
8.1 INTRODUCTION -- 8.2 if AND if-else CONSTRUCTS -- 8.3 assign-deassign CONSTRUCT -- 8.4 repeat CONSTRUCT -- 8.5 for LOOP -- 8.6 THE disable CONSTRUCT -- 8.7 while LOOP -- 8.8 forever LOOP -- 8.9 PARALLEL BLOCKS -- 8.10 force-release CONSTRUCT -- 8.11 EVENT -- 8.12 EXERCISES -- 9 FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES -- 9.1 INTRODUCTIUON -- 9.2 FUNCTION -- 9.3 TASKS -- 9.4 USER-DEFINED PRIMITIVES (UDP).2 -- 9.5 EXERCISES -- 10 SWITCH LEVEL MODELING 305 -- 10.1 INTRODUCTION -- 10.2 BASIC TRANSISTOR SWITCHES.5 -- 10.3 CMOS SWITCH -- 10.4 BIDIRECTIONAL GATES -- 10.5 TIME DELAYS WITH SWITCH PRIMITIVES -- 10.6 INSTANTIATIONS WITH STRENGTHS AND DELAYS -- 10.7 STRENGTH CONTENTION WITH TRIREG NETS -- 10.8 EXERCISES -- 11 SYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES 339 -- 11.1 INTRODUCTION -- 11.2 PARAMETERS.9 -- 11.3 PATH DELAYS -- 11.4 MODULE PARAMETERS -- 11.5 SYSTEM TASKS AND FUNCTIONS -- 11.6 FILE-BASED TASKS AND FUNCTIONS -- 11.7 COMPILER DIRECTIVES -- 11.8 HIERARCHICAL ACCESS -- 11.9 GENERAL OBSERVATIONS -- 11.10 EXERCISES -- 12 QUEUES, PLAS, AND FSMS -- 12.1 INTRODUCTION -- 12.2 QUEUES -- 12.3 PROGRAMMABLE LOGIC DEVICES (PLDs) -- 12.4 DESIGN OF FINITE STATE MACHINES -- 12.5 EXERCISES -- APPENDIX A (Keywords and Their Significance) -- APPENDIX B (Truth Tables of Gates and Switches) -- REFERENCES -- INDEX.
Record Nr. UNISA-996213314303316
Patmaönåapaön òTi. åAr  
Piscataway, New Jersey : , : IEEE Press, , c2004
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari
Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari
Autore Patmaönåapaön òTi. åAr
Pubbl/distr/stampa Piscataway, New Jersey : , : IEEE Press, , c2004
Descrizione fisica 1 PDF (xii, 455 pages) : illustrations
Disciplina 621.39/2
Altri autori (Persone) Tripura SundariB. Bala
Soggetto topico Verilog (Computer hardware description language)
Electrical Engineering
Electrical & Computer Engineering
Engineering & Applied Sciences
Soggetto non controllato Electrical and Electronics Engineering
ISBN 1-280-55707-9
9786610557073
0-471-72299-5
0-471-72300-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto PREFACE -- ACKNOWLEDGEMENTS -- 1 INTRODUCTION TO VLSI DESIGN -- 1.1 INTRODUCTION -- 1.2 CONVENTIONAL APPROACH TO DIGITAL DESIGN -- 1.3 VLSI DESIGN -- 1.4 ASIC DESIGN FLOW -- 1.5 ROLE OF HDL -- 2 INTRODUCTION TO VERILOG -- 2.1 VERILOG AS AN HDL -- 2.2 LEVELS OF DESIGN DESCRIPTION -- 2.3 CONCURRENCY -- 2.4 SIMULATION AND SYNTHESIS -- 2.5 FUNCTIONAL VERIFICATION -- 2.6 SYSTEM TASKS -- 2.7 PROGRAMMING LANGUAGE INTERFACE (PLI) -- 2.8 MODULE -- 2.9 SIMULATION AND SYNTHESIS TOOLS -- 2.10 TEST BENCHES -- 3 LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG -- 3.1 INTRODUCTION -- 3.2 KEYWORDS -- 3.3 IDENTIFIERS -- 3.4 WHITE SPACE CHARACTERS -- 3.5 COMMENTS -- 3.6 NUMBERS -- 3.7 STRINGS -- 3.8 LOGIC VALUES -- 3.9 STRENGTHS -- 3.10 DATA TYPES -- 3.11 SCALARS AND VECTORS -- 3.12 PARAMETERS -- 3.13 MEMORY -- 3.14 OPERATORS -- 3.15 SYSTEM TASKS -- 3.16 EXERCISES -- 4 GATE LEVEL MODELING - 1 -- 4.1 INTRODUCTION -- 4.2 AND GATE PRIMITIVE -- 4.3 MODULE STRUCTURE -- 4.4 OTHER GATE PRIMITIVES -- 4.5 ILLUSTRATIVE EXAMPLES -- 4.6 TRI-STATE GATES -- 4.7 ARRAY OF INSTANCES OF PRIMITIVES -- 4.8 ADDITIONAL EXAMPLES -- 4.9 EXERCISES -- 5 GATE LEVEL MODELING - 2 -- 5.1 INTRODUCTION -- 5.2 DESIGN OF FLIP-FLOPS WITH GATE PRIMITIVES -- 5.3 DELAYS -- 5.4 STRENGTHS AND CONTENTION RESOLUTION -- 5.5 NET TYPES -- 5.6 DESIGN OF BASIC CIRCUITS -- 5.7 EXERCISES -- 6 MODELING AT DATA FLOW LEVEL -- 6.1 INTRODUCTION -- 6.2 CONTINUOUS ASSIGNMENT STRUCTURES -- 6.3 DELAYS AND CONTINUOUS ASSIGNMENTS -- 6.4 ASSIGNMENT TO VECTORS -- 6.5 OPERATORS -- 6.6 ADDITIONAL EXAMPLES -- 6.7 EXERCISES -- 7 BEHAVIORAL MODELING - 1 -- 7.1 INTRODUCTION -- 7.2 OPERATIONS AND ASSIGNMENTS.0 -- 7.3 FUNCTIONAL BIFURCATION.1 -- 7.4 INITIAL CONSTRUCT -- 7.5 ALWAYS CONSTRUCT -- 7.6 EXAMPLES -- 7.7 ASSIGNMENTS WITH DELAYS -- 7.8 wait CONSTRUCT -- 7.9 MULTIPLE ALWAYS BLOCKS -- 7.10 DESIGNS AT BEHAVIORAL LEVEL -- 7.11 BLOCKING AND NONBLOCKING ASSIGNMENTS -- 7.12 THE case STATEMENT -- 7.13 SIMULATION FLOW -- 7.14 EXERCISES -- 8 BEHAVIORAL MODELING II.
8.1 INTRODUCTION -- 8.2 if AND if-else CONSTRUCTS -- 8.3 assign-deassign CONSTRUCT -- 8.4 repeat CONSTRUCT -- 8.5 for LOOP -- 8.6 THE disable CONSTRUCT -- 8.7 while LOOP -- 8.8 forever LOOP -- 8.9 PARALLEL BLOCKS -- 8.10 force-release CONSTRUCT -- 8.11 EVENT -- 8.12 EXERCISES -- 9 FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES -- 9.1 INTRODUCTIUON -- 9.2 FUNCTION -- 9.3 TASKS -- 9.4 USER-DEFINED PRIMITIVES (UDP).2 -- 9.5 EXERCISES -- 10 SWITCH LEVEL MODELING 305 -- 10.1 INTRODUCTION -- 10.2 BASIC TRANSISTOR SWITCHES.5 -- 10.3 CMOS SWITCH -- 10.4 BIDIRECTIONAL GATES -- 10.5 TIME DELAYS WITH SWITCH PRIMITIVES -- 10.6 INSTANTIATIONS WITH STRENGTHS AND DELAYS -- 10.7 STRENGTH CONTENTION WITH TRIREG NETS -- 10.8 EXERCISES -- 11 SYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES 339 -- 11.1 INTRODUCTION -- 11.2 PARAMETERS.9 -- 11.3 PATH DELAYS -- 11.4 MODULE PARAMETERS -- 11.5 SYSTEM TASKS AND FUNCTIONS -- 11.6 FILE-BASED TASKS AND FUNCTIONS -- 11.7 COMPILER DIRECTIVES -- 11.8 HIERARCHICAL ACCESS -- 11.9 GENERAL OBSERVATIONS -- 11.10 EXERCISES -- 12 QUEUES, PLAS, AND FSMS -- 12.1 INTRODUCTION -- 12.2 QUEUES -- 12.3 PROGRAMMABLE LOGIC DEVICES (PLDs) -- 12.4 DESIGN OF FINITE STATE MACHINES -- 12.5 EXERCISES -- APPENDIX A (Keywords and Their Significance) -- APPENDIX B (Truth Tables of Gates and Switches) -- REFERENCES -- INDEX.
Record Nr. UNINA-9910146063303321
Patmaönåapaön òTi. åAr  
Piscataway, New Jersey : , : IEEE Press, , c2004
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari
Design through Verilog HDL / / T.R. Padmanabhan, B. Bala Tripura Sundari
Autore Patmaönåapaön òTi. åAr
Pubbl/distr/stampa Piscataway, New Jersey : , : IEEE Press, , c2004
Descrizione fisica 1 PDF (xii, 455 pages) : illustrations
Disciplina 621.39/2
Altri autori (Persone) Tripura SundariB. Bala
Soggetto topico Verilog (Computer hardware description language)
Electrical Engineering
Electrical & Computer Engineering
Engineering & Applied Sciences
Soggetto non controllato Electrical and Electronics Engineering
ISBN 1-280-55707-9
9786610557073
0-471-72299-5
0-471-72300-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto PREFACE -- ACKNOWLEDGEMENTS -- 1 INTRODUCTION TO VLSI DESIGN -- 1.1 INTRODUCTION -- 1.2 CONVENTIONAL APPROACH TO DIGITAL DESIGN -- 1.3 VLSI DESIGN -- 1.4 ASIC DESIGN FLOW -- 1.5 ROLE OF HDL -- 2 INTRODUCTION TO VERILOG -- 2.1 VERILOG AS AN HDL -- 2.2 LEVELS OF DESIGN DESCRIPTION -- 2.3 CONCURRENCY -- 2.4 SIMULATION AND SYNTHESIS -- 2.5 FUNCTIONAL VERIFICATION -- 2.6 SYSTEM TASKS -- 2.7 PROGRAMMING LANGUAGE INTERFACE (PLI) -- 2.8 MODULE -- 2.9 SIMULATION AND SYNTHESIS TOOLS -- 2.10 TEST BENCHES -- 3 LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG -- 3.1 INTRODUCTION -- 3.2 KEYWORDS -- 3.3 IDENTIFIERS -- 3.4 WHITE SPACE CHARACTERS -- 3.5 COMMENTS -- 3.6 NUMBERS -- 3.7 STRINGS -- 3.8 LOGIC VALUES -- 3.9 STRENGTHS -- 3.10 DATA TYPES -- 3.11 SCALARS AND VECTORS -- 3.12 PARAMETERS -- 3.13 MEMORY -- 3.14 OPERATORS -- 3.15 SYSTEM TASKS -- 3.16 EXERCISES -- 4 GATE LEVEL MODELING - 1 -- 4.1 INTRODUCTION -- 4.2 AND GATE PRIMITIVE -- 4.3 MODULE STRUCTURE -- 4.4 OTHER GATE PRIMITIVES -- 4.5 ILLUSTRATIVE EXAMPLES -- 4.6 TRI-STATE GATES -- 4.7 ARRAY OF INSTANCES OF PRIMITIVES -- 4.8 ADDITIONAL EXAMPLES -- 4.9 EXERCISES -- 5 GATE LEVEL MODELING - 2 -- 5.1 INTRODUCTION -- 5.2 DESIGN OF FLIP-FLOPS WITH GATE PRIMITIVES -- 5.3 DELAYS -- 5.4 STRENGTHS AND CONTENTION RESOLUTION -- 5.5 NET TYPES -- 5.6 DESIGN OF BASIC CIRCUITS -- 5.7 EXERCISES -- 6 MODELING AT DATA FLOW LEVEL -- 6.1 INTRODUCTION -- 6.2 CONTINUOUS ASSIGNMENT STRUCTURES -- 6.3 DELAYS AND CONTINUOUS ASSIGNMENTS -- 6.4 ASSIGNMENT TO VECTORS -- 6.5 OPERATORS -- 6.6 ADDITIONAL EXAMPLES -- 6.7 EXERCISES -- 7 BEHAVIORAL MODELING - 1 -- 7.1 INTRODUCTION -- 7.2 OPERATIONS AND ASSIGNMENTS.0 -- 7.3 FUNCTIONAL BIFURCATION.1 -- 7.4 INITIAL CONSTRUCT -- 7.5 ALWAYS CONSTRUCT -- 7.6 EXAMPLES -- 7.7 ASSIGNMENTS WITH DELAYS -- 7.8 wait CONSTRUCT -- 7.9 MULTIPLE ALWAYS BLOCKS -- 7.10 DESIGNS AT BEHAVIORAL LEVEL -- 7.11 BLOCKING AND NONBLOCKING ASSIGNMENTS -- 7.12 THE case STATEMENT -- 7.13 SIMULATION FLOW -- 7.14 EXERCISES -- 8 BEHAVIORAL MODELING II.
8.1 INTRODUCTION -- 8.2 if AND if-else CONSTRUCTS -- 8.3 assign-deassign CONSTRUCT -- 8.4 repeat CONSTRUCT -- 8.5 for LOOP -- 8.6 THE disable CONSTRUCT -- 8.7 while LOOP -- 8.8 forever LOOP -- 8.9 PARALLEL BLOCKS -- 8.10 force-release CONSTRUCT -- 8.11 EVENT -- 8.12 EXERCISES -- 9 FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES -- 9.1 INTRODUCTIUON -- 9.2 FUNCTION -- 9.3 TASKS -- 9.4 USER-DEFINED PRIMITIVES (UDP).2 -- 9.5 EXERCISES -- 10 SWITCH LEVEL MODELING 305 -- 10.1 INTRODUCTION -- 10.2 BASIC TRANSISTOR SWITCHES.5 -- 10.3 CMOS SWITCH -- 10.4 BIDIRECTIONAL GATES -- 10.5 TIME DELAYS WITH SWITCH PRIMITIVES -- 10.6 INSTANTIATIONS WITH STRENGTHS AND DELAYS -- 10.7 STRENGTH CONTENTION WITH TRIREG NETS -- 10.8 EXERCISES -- 11 SYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES 339 -- 11.1 INTRODUCTION -- 11.2 PARAMETERS.9 -- 11.3 PATH DELAYS -- 11.4 MODULE PARAMETERS -- 11.5 SYSTEM TASKS AND FUNCTIONS -- 11.6 FILE-BASED TASKS AND FUNCTIONS -- 11.7 COMPILER DIRECTIVES -- 11.8 HIERARCHICAL ACCESS -- 11.9 GENERAL OBSERVATIONS -- 11.10 EXERCISES -- 12 QUEUES, PLAS, AND FSMS -- 12.1 INTRODUCTION -- 12.2 QUEUES -- 12.3 PROGRAMMABLE LOGIC DEVICES (PLDs) -- 12.4 DESIGN OF FINITE STATE MACHINES -- 12.5 EXERCISES -- APPENDIX A (Keywords and Their Significance) -- APPENDIX B (Truth Tables of Gates and Switches) -- REFERENCES -- INDEX.
Record Nr. UNINA-9910830990503321
Patmaönåapaön òTi. åAr  
Piscataway, New Jersey : , : IEEE Press, , c2004
Materiale a stampa
Lo trovi qui: Univ. Federico II
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The designer's guide to VHDL / / Peter J. Ashenden
The designer's guide to VHDL / / Peter J. Ashenden
Autore Ashenden Peter J
Edizione [3rd ed.]
Pubbl/distr/stampa Amsterdam : , : Morgan Kaufmann Publishers, , [2008]
Descrizione fisica 1 online resource (933 pages)
Disciplina 621.39/2
Collana The Morgan Kaufmann series in systems on silicon
Soggetto topico VHDL (Computer hardware description language)
Electronic digital computers - Computer simulation
ISBN 1-282-28512-2
9786612285127
0-08-056885-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; The Designer's Guide to VHDL; Copyright Page; Contents; Preface; Chapter 1. Fundamental Concepts; 1.1 Modeling Digital Systems; 1.2 Domains and Levels of Modeling; 1.3 Modeling Languages; 1.4 VHDL Modeling Concepts; 1.5 Learning a New Language: Lexical Elements and Syntax; Exercises; Chapter 2. Scalar Data Types and Operations; 2.1 Constants and Variables; 2.2 Scalar Types; 2.3 Type Classification; 2.4 Attributes of Scalar Types; 2.5 Expressions and Predefined Operations; Exercises; Chapter 3. Sequential Statements; 3.1 If Statements; 3.2 Case Statements; 3.3 Null Statements
3.4 Loop Statements3.5 Assertion and Report Statements; Exercises; Chapter 4. Composite Data Types and Operations; 4.1 Arrays; 4.2 Unconstrained Array Types; 4.3 Array Operations and Referencing; 4.4 Records; Exercises; Chapter 5. Basic Modeling Constructs; 5.1 Entity Declarations and Architecture Bodies; 5.2 Behavioral Descriptions; 5.3 Structural Descriptions; 5.4 Design Processing; Exercises; Chapter 6. Subprograms; 6.1 Procedures; 6.2 Procedure Parameters; 6.3 Concurrent Procedure Call Statements; 6.4 Functions; 6.5 Overloading; 6.6 Visibility of Declarations; Exercises
Chapter 7. Packages and Use Clauses7.1 Package Declarations; 7.2 Package Bodies; 7.3 Use Clauses; Exercises; Chapter 8. Resolved Signals; 8.1 Basic Resolved Signals; 8.2 Resolved Signals, Ports, and Parameters; Exercises; Chapter 9. Predefined and Standard Packages; 9.1 The Predefined Packages standard and env; 9.2 IEEE Standard Packages; Exercises; Chapter 10 Case Study: A Pipelined Multiplier Accumulator; 10.1 Algorithm Outline; 10.2 A Behavioral Model; 10.3 A Register-Transfer-Level Model; Exercises; Chapter 11. Aliases; 11.1 Aliases for Data Objects; 11.2 Aliases for Non-Data Items
ExercisesChapter 12. Generics; 12.1 Generic Constants; 12.2 Generic Types; 12.3 Generic Lists in Packages; 12.4 Generic Lists in Subprograms; 12.5 Generic Subprograms; 12.6 Generic Packages; Exercises; Chapter 13. Components and Configurations; 13.1 Components; 13.2 Configuring Component Instances; 13.3 Configuration Specifications; Exercises; Chapter 14. Generate Statements; 14.1 Generating Iterative Structures; 14.2 Conditionally Generating Structures; 14.3 Configuration of Generate Statements; Exercises; Chapter 15. Access Types; 15.1 Access Types; 15.2 Linked Data Structures
15.3 An Ordered-Dictionary ADT Using Access TypesExercises; Chapter 16. Files and Input/Output; 16.1 Files; 16.2 The Package Textio; Exercises; Chapter 17. Case Study: A Package for Memories; 17.1 The Memories Package; 17.2 Using the Memories Package; Exercises; Chapter 18. Test Bench and Verification Features; 18.1 External Names; 18.2 Force and Release Assignments; 18.3 Embedded PSL in VHDL; Exercises; Chapter 19. Shared Variables and Protected Types; 19.1 Shared Variables and Mutual Exclusion; 19.2 Uninstantiated Methods in Protected Types; Exercises; Chapter 20. Attributes and Groups
20.1 Predefined Attributes
Record Nr. UNINA-9910453430103321
Ashenden Peter J  
Amsterdam : , : Morgan Kaufmann Publishers, , [2008]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
The designer's guide to VHDL / / Peter J. Ashenden
The designer's guide to VHDL / / Peter J. Ashenden
Autore Ashenden Peter J
Edizione [3rd ed.]
Pubbl/distr/stampa Amsterdam : , : Morgan Kaufmann Publishers, , [2008]
Descrizione fisica 1 online resource (933 pages)
Disciplina 621.39/2
Collana The Morgan Kaufmann series in systems on silicon
Soggetto topico VHDL (Computer hardware description language)
Electronic digital computers - Computer simulation
ISBN 1-282-28512-2
9786612285127
0-08-056885-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; The Designer's Guide to VHDL; Copyright Page; Contents; Preface; Chapter 1. Fundamental Concepts; 1.1 Modeling Digital Systems; 1.2 Domains and Levels of Modeling; 1.3 Modeling Languages; 1.4 VHDL Modeling Concepts; 1.5 Learning a New Language: Lexical Elements and Syntax; Exercises; Chapter 2. Scalar Data Types and Operations; 2.1 Constants and Variables; 2.2 Scalar Types; 2.3 Type Classification; 2.4 Attributes of Scalar Types; 2.5 Expressions and Predefined Operations; Exercises; Chapter 3. Sequential Statements; 3.1 If Statements; 3.2 Case Statements; 3.3 Null Statements
3.4 Loop Statements3.5 Assertion and Report Statements; Exercises; Chapter 4. Composite Data Types and Operations; 4.1 Arrays; 4.2 Unconstrained Array Types; 4.3 Array Operations and Referencing; 4.4 Records; Exercises; Chapter 5. Basic Modeling Constructs; 5.1 Entity Declarations and Architecture Bodies; 5.2 Behavioral Descriptions; 5.3 Structural Descriptions; 5.4 Design Processing; Exercises; Chapter 6. Subprograms; 6.1 Procedures; 6.2 Procedure Parameters; 6.3 Concurrent Procedure Call Statements; 6.4 Functions; 6.5 Overloading; 6.6 Visibility of Declarations; Exercises
Chapter 7. Packages and Use Clauses7.1 Package Declarations; 7.2 Package Bodies; 7.3 Use Clauses; Exercises; Chapter 8. Resolved Signals; 8.1 Basic Resolved Signals; 8.2 Resolved Signals, Ports, and Parameters; Exercises; Chapter 9. Predefined and Standard Packages; 9.1 The Predefined Packages standard and env; 9.2 IEEE Standard Packages; Exercises; Chapter 10 Case Study: A Pipelined Multiplier Accumulator; 10.1 Algorithm Outline; 10.2 A Behavioral Model; 10.3 A Register-Transfer-Level Model; Exercises; Chapter 11. Aliases; 11.1 Aliases for Data Objects; 11.2 Aliases for Non-Data Items
ExercisesChapter 12. Generics; 12.1 Generic Constants; 12.2 Generic Types; 12.3 Generic Lists in Packages; 12.4 Generic Lists in Subprograms; 12.5 Generic Subprograms; 12.6 Generic Packages; Exercises; Chapter 13. Components and Configurations; 13.1 Components; 13.2 Configuring Component Instances; 13.3 Configuration Specifications; Exercises; Chapter 14. Generate Statements; 14.1 Generating Iterative Structures; 14.2 Conditionally Generating Structures; 14.3 Configuration of Generate Statements; Exercises; Chapter 15. Access Types; 15.1 Access Types; 15.2 Linked Data Structures
15.3 An Ordered-Dictionary ADT Using Access TypesExercises; Chapter 16. Files and Input/Output; 16.1 Files; 16.2 The Package Textio; Exercises; Chapter 17. Case Study: A Package for Memories; 17.1 The Memories Package; 17.2 Using the Memories Package; Exercises; Chapter 18. Test Bench and Verification Features; 18.1 External Names; 18.2 Force and Release Assignments; 18.3 Embedded PSL in VHDL; Exercises; Chapter 19. Shared Variables and Protected Types; 19.1 Shared Variables and Mutual Exclusion; 19.2 Uninstantiated Methods in Protected Types; Exercises; Chapter 20. Attributes and Groups
20.1 Predefined Attributes
Record Nr. UNINA-9910782360203321
Ashenden Peter J  
Amsterdam : , : Morgan Kaufmann Publishers, , [2008]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
The designer's guide to VHDL / / Peter J. Ashenden
The designer's guide to VHDL / / Peter J. Ashenden
Autore Ashenden Peter J
Edizione [3rd ed.]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008
Descrizione fisica 1 online resource (933 pages)
Disciplina 621.39/2
Collana The Morgan Kaufmann series in systems on silicon
Soggetto topico VHDL (Computer hardware description language)
Electronic digital computers - Computer simulation
ISBN 9786612285127
9781282285125
1282285122
9780080568850
0080568858
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; The Designer's Guide to VHDL; Copyright Page; Contents; Preface; Chapter 1. Fundamental Concepts; 1.1 Modeling Digital Systems; 1.2 Domains and Levels of Modeling; 1.3 Modeling Languages; 1.4 VHDL Modeling Concepts; 1.5 Learning a New Language: Lexical Elements and Syntax; Exercises; Chapter 2. Scalar Data Types and Operations; 2.1 Constants and Variables; 2.2 Scalar Types; 2.3 Type Classification; 2.4 Attributes of Scalar Types; 2.5 Expressions and Predefined Operations; Exercises; Chapter 3. Sequential Statements; 3.1 If Statements; 3.2 Case Statements; 3.3 Null Statements
3.4 Loop Statements3.5 Assertion and Report Statements; Exercises; Chapter 4. Composite Data Types and Operations; 4.1 Arrays; 4.2 Unconstrained Array Types; 4.3 Array Operations and Referencing; 4.4 Records; Exercises; Chapter 5. Basic Modeling Constructs; 5.1 Entity Declarations and Architecture Bodies; 5.2 Behavioral Descriptions; 5.3 Structural Descriptions; 5.4 Design Processing; Exercises; Chapter 6. Subprograms; 6.1 Procedures; 6.2 Procedure Parameters; 6.3 Concurrent Procedure Call Statements; 6.4 Functions; 6.5 Overloading; 6.6 Visibility of Declarations; Exercises
Chapter 7. Packages and Use Clauses7.1 Package Declarations; 7.2 Package Bodies; 7.3 Use Clauses; Exercises; Chapter 8. Resolved Signals; 8.1 Basic Resolved Signals; 8.2 Resolved Signals, Ports, and Parameters; Exercises; Chapter 9. Predefined and Standard Packages; 9.1 The Predefined Packages standard and env; 9.2 IEEE Standard Packages; Exercises; Chapter 10 Case Study: A Pipelined Multiplier Accumulator; 10.1 Algorithm Outline; 10.2 A Behavioral Model; 10.3 A Register-Transfer-Level Model; Exercises; Chapter 11. Aliases; 11.1 Aliases for Data Objects; 11.2 Aliases for Non-Data Items
ExercisesChapter 12. Generics; 12.1 Generic Constants; 12.2 Generic Types; 12.3 Generic Lists in Packages; 12.4 Generic Lists in Subprograms; 12.5 Generic Subprograms; 12.6 Generic Packages; Exercises; Chapter 13. Components and Configurations; 13.1 Components; 13.2 Configuring Component Instances; 13.3 Configuration Specifications; Exercises; Chapter 14. Generate Statements; 14.1 Generating Iterative Structures; 14.2 Conditionally Generating Structures; 14.3 Configuration of Generate Statements; Exercises; Chapter 15. Access Types; 15.1 Access Types; 15.2 Linked Data Structures
15.3 An Ordered-Dictionary ADT Using Access TypesExercises; Chapter 16. Files and Input/Output; 16.1 Files; 16.2 The Package Textio; Exercises; Chapter 17. Case Study: A Package for Memories; 17.1 The Memories Package; 17.2 Using the Memories Package; Exercises; Chapter 18. Test Bench and Verification Features; 18.1 External Names; 18.2 Force and Release Assignments; 18.3 Embedded PSL in VHDL; Exercises; Chapter 19. Shared Variables and Protected Types; 19.1 Shared Variables and Mutual Exclusion; 19.2 Uninstantiated Methods in Protected Types; Exercises; Chapter 20. Attributes and Groups
20.1 Predefined Attributes
Record Nr. UNINA-9910968241303321
Ashenden Peter J  
Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Designing digital computing systems with Verilog / / David J. Lilja and Sachin S. Sapatnekar
Designing digital computing systems with Verilog / / David J. Lilja and Sachin S. Sapatnekar
Autore Lilja David J
Pubbl/distr/stampa Cambridge ; ; New York, : Cambridge University Press, 2005
Descrizione fisica 1 online resource (ix, 160 pages) : digital, PDF file(s)
Disciplina 621.39/2
Altri autori (Persone) SapatnekarSachin S. <1967->
Soggetto topico Verilog (Computer hardware description language)
Electronic digital computers - Design and construction
ISBN 1-107-16031-6
1-280-74962-8
9786610749621
0-511-26247-7
0-511-26486-0
0-511-26558-1
0-511-26328-7
0-511-33160-6
0-511-60705-9
0-511-26409-7
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Cover; Half-title; Title; Copyright; Contents; Preface; 1 Controlling complexity; 2 A Verilogical place to start; 3 Defining the instruction set architecture; 4 Algorithmic behavioral modeling; 5 Building an assembler for VeSPA; 6 Pipelining; 7 Implementation of the pipelined processor; 8 Verification; APPENDIX A The VeSPA instruction set architecture (ISA); APPENDIX B The VASM assembler; Index
Record Nr. UNINA-9911006647203321
Lilja David J  
Cambridge ; ; New York, : Cambridge University Press, 2005
Materiale a stampa
Lo trovi qui: Univ. Federico II
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