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2002 IEEE International Conference on Computer Design : VLSI in computers and processors : proceedings : September 16-18, 2002, Freiburg, Germany
| 2002 IEEE International Conference on Computer Design : VLSI in computers and processors : proceedings : September 16-18, 2002, Freiburg, Germany |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2002 |
| Disciplina | 621.39/16 |
| Soggetto topico |
Microcomputers - Design and construction
Electronic digital computers - Circuits Integrated circuits - Very large scale integration Computer engineering Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996200837903316 |
| [Place of publication not identified], : IEEE Computer Society, 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2002 IEEE International Conference on Computer Design : VLSI in computers and processors : proceedings : September 16-18, 2002, Freiburg, Germany
| 2002 IEEE International Conference on Computer Design : VLSI in computers and processors : proceedings : September 16-18, 2002, Freiburg, Germany |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2002 |
| Disciplina | 621.39/16 |
| Soggetto topico |
Microcomputers - Design and construction
Electronic digital computers - Circuits Integrated circuits - Very large scale integration Computer engineering Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910872979803321 |
| [Place of publication not identified], : IEEE Computer Society, 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
The Book of overclocking [[electronic resource] ] : tweak your PC to unleash its power / / Scott Wainner and Robert Richmond
| The Book of overclocking [[electronic resource] ] : tweak your PC to unleash its power / / Scott Wainner and Robert Richmond |
| Autore | Wainner Scott |
| Pubbl/distr/stampa | San Francisco, : No Starch Press, 2003 |
| Descrizione fisica | xv, 251 p |
| Disciplina | 621.39/16 |
| Altri autori (Persone) | RichmondRobert <1980-> |
| Soggetto topico |
Microcomputers - Upgrading
Computer organization High performance computing |
| Soggetto genere / forma | Electronic books. |
| ISBN | 1-59327-017-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910456337703321 |
Wainner Scott
|
||
| San Francisco, : No Starch Press, 2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
The Book of overclocking [[electronic resource] ] : tweak your PC to unleash its power / / Scott Wainner and Robert Richmond
| The Book of overclocking [[electronic resource] ] : tweak your PC to unleash its power / / Scott Wainner and Robert Richmond |
| Autore | Wainner Scott |
| Pubbl/distr/stampa | San Francisco, : No Starch Press, 2003 |
| Descrizione fisica | xv, 251 p |
| Disciplina | 621.39/16 |
| Altri autori (Persone) | RichmondRobert <1980-> |
| Soggetto topico |
Microcomputers - Upgrading
Computer organization High performance computing |
| ISBN | 1-59327-017-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910780127003321 |
|
Wainner Scott
|
||
| San Francisco, : No Starch Press, 2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
The Book of overclocking : tweak your PC to unleash its power / / Scott Wainner and Robert Richmond
| The Book of overclocking : tweak your PC to unleash its power / / Scott Wainner and Robert Richmond |
| Autore | Wainner Scott |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | San Francisco, : No Starch Press, 2003 |
| Descrizione fisica | xv, 251 p |
| Disciplina | 621.39/16 |
| Altri autori (Persone) | RichmondRobert <1980-> |
| Soggetto topico |
Microcomputers - Upgrading
Computer organization High performance computing |
| ISBN | 1-59327-017-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Intro -- BRIEF CONTENTS -- CONTENTS IN DETAIL -- 1 WHAT THE COMPUTER INDUSTRY DOES NOT WANT YOU TO KNOW -- 2 OVERCLOCKING VERSUS INDUSTRY HYPE: TECHNICAL BACKGROUND -- 3 TECHNICAL THEORY: EVOLUTION OF THE INTEGRATED CIRCUIT -- 4 HOW TO OVERCLOCK -- 5 COOLING -- 6 INTEL OVERCLOCKING -- 7 AMD OVERCLOCKING -- 8 VIA / CYRIX OVERCLOCKING -- 9 BENCHMARK TESTING -- 10 TROUBLESHOOTING -- 11 FINAL THOUGHTS -- APPENDIX -- INDEX -- UPDATES -- ABOUT THE AUTHORS. |
| Record Nr. | UNINA-9910828869103321 |
|
Wainner Scott
|
||
| San Francisco, : No Starch Press, 2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Dedicated digital processors [[electronic resource] ] : methods in hardware/software system design / / F. Mayer-Lindenberg
| Dedicated digital processors [[electronic resource] ] : methods in hardware/software system design / / F. Mayer-Lindenberg |
| Autore | Mayer-Lindenberg F |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : J. Wiley, c2004 |
| Descrizione fisica | 1 online resource (316 p.) |
| Disciplina |
621.39/16
621.3916 |
| Soggetto topico |
Microprocessors - Design and construction
Computer software |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-26941-3
9786610269419 0-470-09282-3 0-470-09284-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
DEDICATED DIGITAL PROCESSORS; Contents; Preface; 1 Digital Computer Basics; 1.1 Data Encoding; 1.1.1 Encoding Numbers; 1.1.2 Code Conversions and More Codes; 1.2 Algorithms and Algorithmic Notations; 1.2.1 Functional Composition and the Data Flow; 1.2.2 Composition by Cases and the Control Flow; 1.2.3 Alternative Algorithms; 1.3 Boolean Functions; 1.3.1 Sets of Elementary Boolean Operations; 1.3.2 Gate Complexity and Simplification of Boolean Algorithms; 1.3.3 Combined and Universal Functions; 1.4 Timing, Synchronization and Memory; 1.4.1 Processing Time and Throughput of Composite Circuits
1.4.2 Serial and Parallel Processing1.4.3 Synchronization; 1.5 Aspects of System Design; 1.5.1 Architectures for Digital Systems; 1.5.2 Application Modeling; 1.5.3 Design Metrics; 1.6 Summary; Exercises; 2 Hardware Elements; 2.1 Transistors, Gates and Flip-Flops; 2.1.1 Implementing Gates with Switches; 2.1.2 Registers and Synchronization Signals; 2.1.3 Power Consumption and Related Design Rules; 2.1.4 Pulse Generation and Interfacing; 2.2 Chip Technology; 2.2.1 Memory Bus Interface; 2.2.2 Semiconductor Memory Devices; 2.2.3 Processors and Single-Chip Systems; 2.2.4 Configurable Logic, FPGA 2.3 Chip Level and Circuit Board-Level Design2.3.1 Chip Versus Board-Level Design; 2.3.2 IP-Based Design; 2.3.3 Configurable Boards and Interconnections; 2.3.4 Testing; 2.4 Summary; Exercises; 3 Hardware Design Using VHDL; 3.1 Hardware Design Languages; 3.2 Entities and Signals; 3.3 Functional Behavior of Building Blocks; 3.4 Structural Architecture Definitions; 3.5 Timing Behavior and Simulation; 3.6 Test Benches; 3.7 Synthesis Aspects; 3.8 Summary; Exercises; 4 Operations on Numbers; 4.1 Single Bit Binary Adders and Multipliers; 4.2 Fixed Point Add, Subtract, and Compare 4.3 Add and Subtract for Redundant Codes4.4 Binary Multiplication; 4.5 Sequential Adders, Multipliers and Multiply-Add Structures; 4.6 Distributed Arithmetic; 4.7 Division and Square Root; 4.8 Floating Point Operations and Functions; 4.9 Polynomial Arithmetic; 4.10 Summary; Exercises; 5 Sequential Control Circuits; 5.1 Mealy and Moore Automata; 5.2 Scheduling, Operand Selection and the Storage Automaton; 5.3 Designing the Control Automaton; 5.4 Sequencing with Counter and Shift Register Circuits; 5.5 Implementing the Control Flow; 5.6 Synchronization; 5.7 Summary; Exercises 6 Sequential Processors6.1 Designing for ALU Efficiency; 6.1.1 Multifunction ALU Circuits; 6.1.2 Pipelining; 6.2 The Memory Subsystem; 6.2.1 Pipelined Memory Accesses, Registers, and the Von Neumann Architecture; 6.2.2 Instruction Set Architectures and Memory Requirements; 6.2.3 Caches and Virtual Memory, Soft Caching; 6.3 Simple Programmable Processor Designs; 6.3.1 CPU1 - The Basic Control Function; 6.3.2 CPU2 - An Efficient Processor for FPGA-based Systems; 6.4 Interrupt Processing and Context Switching; 6.5 Interfacing Techniques; 6.5.1 Pipelining Input and Output 6.5.2 Parallel and Serial Interfaces, Counters and Timers |
| Record Nr. | UNINA-9910145770203321 |
|
Mayer-Lindenberg F
|
||
| Hoboken, N.J., : J. Wiley, c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Dedicated digital processors [[electronic resource] ] : methods in hardware/software system design / / F. Mayer-Lindenberg
| Dedicated digital processors [[electronic resource] ] : methods in hardware/software system design / / F. Mayer-Lindenberg |
| Autore | Mayer-Lindenberg F |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : J. Wiley, c2004 |
| Descrizione fisica | 1 online resource (316 p.) |
| Disciplina |
621.39/16
621.3916 |
| Soggetto topico |
Microprocessors - Design and construction
Computer software |
| ISBN |
1-280-26941-3
9786610269419 0-470-09282-3 0-470-09284-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
DEDICATED DIGITAL PROCESSORS; Contents; Preface; 1 Digital Computer Basics; 1.1 Data Encoding; 1.1.1 Encoding Numbers; 1.1.2 Code Conversions and More Codes; 1.2 Algorithms and Algorithmic Notations; 1.2.1 Functional Composition and the Data Flow; 1.2.2 Composition by Cases and the Control Flow; 1.2.3 Alternative Algorithms; 1.3 Boolean Functions; 1.3.1 Sets of Elementary Boolean Operations; 1.3.2 Gate Complexity and Simplification of Boolean Algorithms; 1.3.3 Combined and Universal Functions; 1.4 Timing, Synchronization and Memory; 1.4.1 Processing Time and Throughput of Composite Circuits
1.4.2 Serial and Parallel Processing1.4.3 Synchronization; 1.5 Aspects of System Design; 1.5.1 Architectures for Digital Systems; 1.5.2 Application Modeling; 1.5.3 Design Metrics; 1.6 Summary; Exercises; 2 Hardware Elements; 2.1 Transistors, Gates and Flip-Flops; 2.1.1 Implementing Gates with Switches; 2.1.2 Registers and Synchronization Signals; 2.1.3 Power Consumption and Related Design Rules; 2.1.4 Pulse Generation and Interfacing; 2.2 Chip Technology; 2.2.1 Memory Bus Interface; 2.2.2 Semiconductor Memory Devices; 2.2.3 Processors and Single-Chip Systems; 2.2.4 Configurable Logic, FPGA 2.3 Chip Level and Circuit Board-Level Design2.3.1 Chip Versus Board-Level Design; 2.3.2 IP-Based Design; 2.3.3 Configurable Boards and Interconnections; 2.3.4 Testing; 2.4 Summary; Exercises; 3 Hardware Design Using VHDL; 3.1 Hardware Design Languages; 3.2 Entities and Signals; 3.3 Functional Behavior of Building Blocks; 3.4 Structural Architecture Definitions; 3.5 Timing Behavior and Simulation; 3.6 Test Benches; 3.7 Synthesis Aspects; 3.8 Summary; Exercises; 4 Operations on Numbers; 4.1 Single Bit Binary Adders and Multipliers; 4.2 Fixed Point Add, Subtract, and Compare 4.3 Add and Subtract for Redundant Codes4.4 Binary Multiplication; 4.5 Sequential Adders, Multipliers and Multiply-Add Structures; 4.6 Distributed Arithmetic; 4.7 Division and Square Root; 4.8 Floating Point Operations and Functions; 4.9 Polynomial Arithmetic; 4.10 Summary; Exercises; 5 Sequential Control Circuits; 5.1 Mealy and Moore Automata; 5.2 Scheduling, Operand Selection and the Storage Automaton; 5.3 Designing the Control Automaton; 5.4 Sequencing with Counter and Shift Register Circuits; 5.5 Implementing the Control Flow; 5.6 Synchronization; 5.7 Summary; Exercises 6 Sequential Processors6.1 Designing for ALU Efficiency; 6.1.1 Multifunction ALU Circuits; 6.1.2 Pipelining; 6.2 The Memory Subsystem; 6.2.1 Pipelined Memory Accesses, Registers, and the Von Neumann Architecture; 6.2.2 Instruction Set Architectures and Memory Requirements; 6.2.3 Caches and Virtual Memory, Soft Caching; 6.3 Simple Programmable Processor Designs; 6.3.1 CPU1 - The Basic Control Function; 6.3.2 CPU2 - An Efficient Processor for FPGA-based Systems; 6.4 Interrupt Processing and Context Switching; 6.5 Interfacing Techniques; 6.5.1 Pipelining Input and Output 6.5.2 Parallel and Serial Interfaces, Counters and Timers |
| Record Nr. | UNINA-9910829873703321 |
|
Mayer-Lindenberg F
|
||
| Hoboken, N.J., : J. Wiley, c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Dedicated digital processors : methods in hardware/software system design / / F. Mayer-Lindenberg
| Dedicated digital processors : methods in hardware/software system design / / F. Mayer-Lindenberg |
| Autore | Mayer-Lindenberg F |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : J. Wiley, c2004 |
| Descrizione fisica | 1 online resource (316 p.) |
| Disciplina | 621.39/16 |
| Soggetto topico |
Microprocessors - Design and construction
Computer software |
| ISBN |
1-280-26941-3
9786610269419 0-470-09282-3 0-470-09284-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
DEDICATED DIGITAL PROCESSORS; Contents; Preface; 1 Digital Computer Basics; 1.1 Data Encoding; 1.1.1 Encoding Numbers; 1.1.2 Code Conversions and More Codes; 1.2 Algorithms and Algorithmic Notations; 1.2.1 Functional Composition and the Data Flow; 1.2.2 Composition by Cases and the Control Flow; 1.2.3 Alternative Algorithms; 1.3 Boolean Functions; 1.3.1 Sets of Elementary Boolean Operations; 1.3.2 Gate Complexity and Simplification of Boolean Algorithms; 1.3.3 Combined and Universal Functions; 1.4 Timing, Synchronization and Memory; 1.4.1 Processing Time and Throughput of Composite Circuits
1.4.2 Serial and Parallel Processing1.4.3 Synchronization; 1.5 Aspects of System Design; 1.5.1 Architectures for Digital Systems; 1.5.2 Application Modeling; 1.5.3 Design Metrics; 1.6 Summary; Exercises; 2 Hardware Elements; 2.1 Transistors, Gates and Flip-Flops; 2.1.1 Implementing Gates with Switches; 2.1.2 Registers and Synchronization Signals; 2.1.3 Power Consumption and Related Design Rules; 2.1.4 Pulse Generation and Interfacing; 2.2 Chip Technology; 2.2.1 Memory Bus Interface; 2.2.2 Semiconductor Memory Devices; 2.2.3 Processors and Single-Chip Systems; 2.2.4 Configurable Logic, FPGA 2.3 Chip Level and Circuit Board-Level Design2.3.1 Chip Versus Board-Level Design; 2.3.2 IP-Based Design; 2.3.3 Configurable Boards and Interconnections; 2.3.4 Testing; 2.4 Summary; Exercises; 3 Hardware Design Using VHDL; 3.1 Hardware Design Languages; 3.2 Entities and Signals; 3.3 Functional Behavior of Building Blocks; 3.4 Structural Architecture Definitions; 3.5 Timing Behavior and Simulation; 3.6 Test Benches; 3.7 Synthesis Aspects; 3.8 Summary; Exercises; 4 Operations on Numbers; 4.1 Single Bit Binary Adders and Multipliers; 4.2 Fixed Point Add, Subtract, and Compare 4.3 Add and Subtract for Redundant Codes4.4 Binary Multiplication; 4.5 Sequential Adders, Multipliers and Multiply-Add Structures; 4.6 Distributed Arithmetic; 4.7 Division and Square Root; 4.8 Floating Point Operations and Functions; 4.9 Polynomial Arithmetic; 4.10 Summary; Exercises; 5 Sequential Control Circuits; 5.1 Mealy and Moore Automata; 5.2 Scheduling, Operand Selection and the Storage Automaton; 5.3 Designing the Control Automaton; 5.4 Sequencing with Counter and Shift Register Circuits; 5.5 Implementing the Control Flow; 5.6 Synchronization; 5.7 Summary; Exercises 6 Sequential Processors6.1 Designing for ALU Efficiency; 6.1.1 Multifunction ALU Circuits; 6.1.2 Pipelining; 6.2 The Memory Subsystem; 6.2.1 Pipelined Memory Accesses, Registers, and the Von Neumann Architecture; 6.2.2 Instruction Set Architectures and Memory Requirements; 6.2.3 Caches and Virtual Memory, Soft Caching; 6.3 Simple Programmable Processor Designs; 6.3.1 CPU1 - The Basic Control Function; 6.3.2 CPU2 - An Efficient Processor for FPGA-based Systems; 6.4 Interrupt Processing and Context Switching; 6.5 Interfacing Techniques; 6.5.1 Pipelining Input and Output 6.5.2 Parallel and Serial Interfaces, Counters and Timers |
| Record Nr. | UNINA-9910876980503321 |
|
Mayer-Lindenberg F
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||
| Hoboken, N.J., : J. Wiley, c2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
The definitive guide to the ARM cortex-M0 [[electronic resource] /] / Joseph Yiu
| The definitive guide to the ARM cortex-M0 [[electronic resource] /] / Joseph Yiu |
| Autore | Yiu Joseph |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Newnes, 2011 |
| Descrizione fisica | 1 online resource (553 p.) |
| Disciplina |
621.39/16
621.3916 |
| Soggetto topico |
Embedded computer systems
Microprocessors |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-283-52645-X
9786613838902 0-12-385478-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; The Definitive Guide to the ARM Cortex-M0; Copyright; Contents; Foreword; Preface; Acknowledgments; Conventions; Terms and Abbreviations; Chapter 1 Introduction; Why Cortex-M0?; Application of the Cortex-M0 Processors; Background of ARM and ARM processors; Cortex-M0 Processor Specification and ARM Architecture; ARM Processors and the ARM Ecosystem; Getting Started with the Cortex-M0 Processor; Organization of This Book and Resources; Chapter 2 Cortex-M0 Technical Overview; General Information on the Cortex-M0 Processor; The ARM Cortex-M0 Processor Features
Advantages of the Cortex-M0 ProcessorLow-Power Applications; Cortex-M0 Software Portability; Chapter 3 Architecture; Overview; Programmer's Model; Memory System Overview; Stack Memory Operations; Exceptions and Interrupts; Nested Vectored Interrupt Controller (NVIC); System Control Block (SCB); Program Image and Startup Sequence; Chapter 4 Introduction to Cortex-M0 Programming; Introduction to Embedded System Programming; Inputs and Outputs; Development Flow; C Programming and Assembly Programming; What Is in a Program Image?; C Programming: Data Types; Accessing Peripherals in C Cortex Microcontroller Software Interface Standard (CMSIS)Benefits of CMSIS; Chapter 5 Instruction Set; Background of ARM and Thumb Instruction Set; Assembly Basics; Pseudo Instructions; Chapter 6 Instruction Usage Examples; Overview; Program Control; Data Accesses; Data Type Conversion; Data Processing; Chapter 7 Memory System; Overview; Memory Map; Program Memory, Boot Loader, and Memory Remapping; Data Memory; Little Endian and Big Endian Support; Memory Attributes; Chapter 8 Exceptions and Interrupts; What Are Exceptions and Interrupts?; Exception Types on the Cortex-M0 Processor Exception Priority DefinitionVector Table; Exception Sequence Overview; EXC_RETURN; Details of Exception Entry Sequence; Details of Exception Exit Sequence; Chapter 9 Interrupt Control and System Control; Overview of the NVIC and System Control Block Features; Interrupt Enable and Clear Enable; Interrupt Pending and Clear Pending; Interrupt Priority Level; Generic Assembly Code for Interrupt Control; Exception Masking Register (PRIMASK); Interrupt Inputs and Pending Behavior; Interrupt Latency; Control Registers for System Exceptions; System Control Registers Chapter 10 Operating System Support FeaturesOverview of the OS Support Features; The SysTick Timer; SysTick Registers; Process Stack and Process Stack Pointer; SVC; PendSV; Chapter 11 Low-Power Features; Low-Power Embedded System Overview; Low-Power Advantages of the Cortex-M0 Processor; Overview of the Low-Power Features; Sleep Modes; Wait-for-Event (WFE) and Wait-for-Interrupt (WFI); Sleep-on-Exit Feature; Wakeup Interrupt Controller; Chapter 12 Fault Handling; Fault Exception Overview; Analyze a Fault; Accidental Switching to ARM State; Error Handling in Real Applications; Lockup Preventing Lockup |
| Record Nr. | UNINA-9910465513203321 |
|
Yiu Joseph
|
||
| Amsterdam ; ; Boston, : Newnes, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
The definitive guide to the ARM cortex-M0 [[electronic resource] /] / Joseph Yiu
| The definitive guide to the ARM cortex-M0 [[electronic resource] /] / Joseph Yiu |
| Autore | Yiu Joseph |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Newnes, 2011 |
| Descrizione fisica | 1 online resource (553 p.) |
| Disciplina |
621.39/16
621.3916 |
| Soggetto topico |
Embedded computer systems
Microprocessors |
| ISBN |
1-283-52645-X
9786613838902 0-12-385478-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; The Definitive Guide to the ARM Cortex-M0; Copyright; Contents; Foreword; Preface; Acknowledgments; Conventions; Terms and Abbreviations; Chapter 1 Introduction; Why Cortex-M0?; Application of the Cortex-M0 Processors; Background of ARM and ARM processors; Cortex-M0 Processor Specification and ARM Architecture; ARM Processors and the ARM Ecosystem; Getting Started with the Cortex-M0 Processor; Organization of This Book and Resources; Chapter 2 Cortex-M0 Technical Overview; General Information on the Cortex-M0 Processor; The ARM Cortex-M0 Processor Features
Advantages of the Cortex-M0 ProcessorLow-Power Applications; Cortex-M0 Software Portability; Chapter 3 Architecture; Overview; Programmer's Model; Memory System Overview; Stack Memory Operations; Exceptions and Interrupts; Nested Vectored Interrupt Controller (NVIC); System Control Block (SCB); Program Image and Startup Sequence; Chapter 4 Introduction to Cortex-M0 Programming; Introduction to Embedded System Programming; Inputs and Outputs; Development Flow; C Programming and Assembly Programming; What Is in a Program Image?; C Programming: Data Types; Accessing Peripherals in C Cortex Microcontroller Software Interface Standard (CMSIS)Benefits of CMSIS; Chapter 5 Instruction Set; Background of ARM and Thumb Instruction Set; Assembly Basics; Pseudo Instructions; Chapter 6 Instruction Usage Examples; Overview; Program Control; Data Accesses; Data Type Conversion; Data Processing; Chapter 7 Memory System; Overview; Memory Map; Program Memory, Boot Loader, and Memory Remapping; Data Memory; Little Endian and Big Endian Support; Memory Attributes; Chapter 8 Exceptions and Interrupts; What Are Exceptions and Interrupts?; Exception Types on the Cortex-M0 Processor Exception Priority DefinitionVector Table; Exception Sequence Overview; EXC_RETURN; Details of Exception Entry Sequence; Details of Exception Exit Sequence; Chapter 9 Interrupt Control and System Control; Overview of the NVIC and System Control Block Features; Interrupt Enable and Clear Enable; Interrupt Pending and Clear Pending; Interrupt Priority Level; Generic Assembly Code for Interrupt Control; Exception Masking Register (PRIMASK); Interrupt Inputs and Pending Behavior; Interrupt Latency; Control Registers for System Exceptions; System Control Registers Chapter 10 Operating System Support FeaturesOverview of the OS Support Features; The SysTick Timer; SysTick Registers; Process Stack and Process Stack Pointer; SVC; PendSV; Chapter 11 Low-Power Features; Low-Power Embedded System Overview; Low-Power Advantages of the Cortex-M0 Processor; Overview of the Low-Power Features; Sleep Modes; Wait-for-Event (WFE) and Wait-for-Interrupt (WFI); Sleep-on-Exit Feature; Wakeup Interrupt Controller; Chapter 12 Fault Handling; Fault Exception Overview; Analyze a Fault; Accidental Switching to ARM State; Error Handling in Real Applications; Lockup Preventing Lockup |
| Record Nr. | UNINA-9910791978103321 |
|
Yiu Joseph
|
||
| Amsterdam ; ; Boston, : Newnes, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
