Info
- Utilizzare la checkbox di selezione a fianco di ciascun documento per attivare le funzionalità di stampa, invio email, download nei formati disponibili del (i) record.
Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission / / by Nereo Markulic, Kuba Raczkowski, Jan Craninckx, Piet Wambacq
| Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission / / by Nereo Markulic, Kuba Raczkowski, Jan Craninckx, Piet Wambacq |
| Autore | Markulic Nereo |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (156 pages) |
| Disciplina | 621.3815364 |
| Collana | Analog Circuits and Signal Processing |
| Soggetto topico |
Electronic circuits
Electronics Microelectronics Circuits and Systems Electronic Circuits and Devices Electronics and Microelectronics, Instrumentation |
| ISBN | 3-030-10958-5 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1. Introduction -- Chapter 2. A Digital-to-Time Converter based Subsampling PLL for Fractional Synthesis -- Chapter 3. A Background-Calibrated Subsampling PLL for Phase/Frequency Modulation -- Chapter 4. A Background-Calibrated Digital Subsampling Polar Transmitter -- Chapter 5. Conclusion and Future Outlook. |
| Record Nr. | UNINA-9910337640503321 |
Markulic Nereo
|
||
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Monolithic phase-locked loops and clock recovery circuits : theory and design / edited by Behzad Razavi
| Monolithic phase-locked loops and clock recovery circuits : theory and design / edited by Behzad Razavi |
| Pubbl/distr/stampa | New York, : IEEE press, \1996! |
| Descrizione fisica | IX, 498 p. ; 29 cm |
| Disciplina | 621.3815364 |
| Soggetto topico | Circuiti integrati |
| ISBN | 0780311493 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNICAS-MIL0301450 |
| New York, : IEEE press, \1996! | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Cassino e del Lazio Meridionale | ||
| ||
Noise-shaping all-digital phase-locked loops : modeling, simulation, analysis and design / / Francesco Brandonisio, Michael Peter Kennedy
| Noise-shaping all-digital phase-locked loops : modeling, simulation, analysis and design / / Francesco Brandonisio, Michael Peter Kennedy |
| Autore | Brandonisio Francesco |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , 2014 |
| Descrizione fisica | 1 online resource (xiii, 177 pages) : illustrations (some color) |
| Disciplina | 621.3815364 |
| Collana | Analog Circuits and Signal Processing |
| Soggetto topico |
Phase-locked loops
Electronic digital computers - Circuits - Design and construction |
| ISBN | 3-319-03659-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Phase Digitization in All-Digital PLLs -- A Unifying Framework for TDC Architectures -- Analytical Predictions of Phase Noise in ADPLLs -- Advantages of Noise Shaping and Dither -- Efficient Modeling and Simulation of Accumulator-Based ADPLLs -- Modelling and Estimating Phase Noise with Matlab. |
| Record Nr. | UNINA-9910299495603321 |
|
Brandonisio Francesco
|
||
| Cham, Switzerland : , : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Phase lock loops and frequency synthesis [[electronic resource] /] / Věnceslav F. Kroupa
| Phase lock loops and frequency synthesis [[electronic resource] /] / Věnceslav F. Kroupa |
| Autore | Kroupa Věnceslav F. <1923-> |
| Pubbl/distr/stampa | New York, : J. Wiley, 2003 |
| Descrizione fisica | 1 online resource (336 p.) |
| Disciplina |
621.3815/364
621.3815364 621.382 |
| Soggetto topico |
Phase-locked loops
Frequency synthesizers |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-27201-5
9786610272013 0-470-29946-0 0-470-86512-1 0-470-01410-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Phase Lock Loops and Frequency Synthesis; Contents; Preface; 1 Basic Equations of the PLLs; 1.1 Introduction; 1.2 Basic Equations of the PLLs; 1.3 Solution of the Basic PLL Equation in the Time Domain; 1.3.1 Solution in the Closed Form; 1.3.2 Linearized Solution; 1.4 Solution of Basic PLL Equations in the Frequency Domain; 1.5 Order and Type of PLLs; 1.5.1 Order of PLLs; 1.5.2 Type of PLLs; 1.5.3 Steady State Errors; 1.6 Block Diagram Algebra; References; 2 PLLs of the First and Second Order; 2.1 PLLs of the First Order; 2.2 PLLs of the Second Order; 2.2.1 A Simple RC Filter
2.2.2 Phase Lag-lead RRC or RCC Filter2.3 PLLs of the Second Order of Type 2; 2.3.1 PLLs of the Second Order of Type 2 with Voltage Output PD; 2.3.2 PLLs of the Second Order of Type 2 with Current Output Phase Detector; 2.4 Second-order PLLs with Frequency Dividers in the Feedback Path; References; 3 PLLs of the Third and Higher Orders; 3.1 General Open-loop Transfer Function G(s); 3.1.1 Additional RC Section; 3.1.2 Two RC Sections; 3.1.3 Active Second-order Low-pass Filter; 3.1.4 Twin-T RC Filter; 3.1.5 PLLs with a Selective Filter in the Feedback Path; 3.1.6 Time Delays in PLLs 3.2 Higher-order Type 2 PLLs3.2.1 Third-order Loops: Lag-lead Filter with Additional RC Section; 3.2.2 Third-order Loop: Second-order Lag Filter Plus RC Section; 3.2.3 Fourth-order Loops; 3.2.4 Fifth-order Loops; 3.3 PLLs with Transmission Blocks in the Feedback Path; 3.3.1 Divider in the Feedback Path; 3.3.2 IF Filter in the Feedback Path; 3.3.3 IF Filter and Divider in the Feedback Path; 3.4 Sampled Higher-order Loops; 3.4.1 Third-order Loops with the Current Output Phase Detector; 3.5 Higher-order Loops of Type 3; 3.6 Computer Design of a Higher-order PLL; References 4 Stability of the PLL Systems4.1 Hurwitz Criterion of Stability; 4.2 Computation of the Roots of the Polynomial P(s); 4.3 Expansion of the Function 1/[1 + G(s)] into a Sum of Simple Fractions; 4.3.1 Polynomial S(s) Contains Simple Roots Only; 4.3.2 Polynomial S(s) Contains a Pair of Complex Roots; 4.3.3 Polynomial S(s) Contains Multiple-order Roots; 4.4 The Root-locus Method; 4.5 Frequency Analysis of the Transfer Functions - Bode Plots; 4.5.1 Bode Plots; 4.5.2 Polar Diagrams; 4.6 Nyquist Criterion of Stability; 4.7 The Effective Damping Factor; 4.8 Appendix; References; 5 Tracking 5.1 Transients in PLLs5.1.1 Transients in First-order PLLs; 5.1.2 Transients in Second-order PLLs; 5.1.3 Transients in Higher-order Loops; 5.2 Periodic Changes; 5.2.1 Phase Modulation of the Input Signal; 5.2.2 Frequency Modulation of the Input Signal; 5.3 Discrete Spurious Signals; 5.3.1 Small Discrete Spurious Signals at the Input; 5.3.2 Small Spurious Signals at the Output of the Phase Detector; 5.3.3 Small Spurious Signals at the Output of the PLLs; References; 6 Working Ranges of PLLs; 6.1 Hold-in Range; 6.1.1 Phase Detector with the Sine Wave Output; 6.1.2 The PD with Triangular Output 6.1.3 The PD with a Sawtooth Wave Output |
| Record Nr. | UNINA-9910143229003321 |
|
Kroupa Věnceslav F. <1923->
|
||
| New York, : J. Wiley, 2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Phase lock loops and frequency synthesis [[electronic resource] /] / Věnceslav F. Kroupa
| Phase lock loops and frequency synthesis [[electronic resource] /] / Věnceslav F. Kroupa |
| Autore | Kroupa Věnceslav F. <1923-> |
| Pubbl/distr/stampa | New York, : J. Wiley, 2003 |
| Descrizione fisica | 1 online resource (336 p.) |
| Disciplina |
621.3815/364
621.3815364 621.382 |
| Soggetto topico |
Phase-locked loops
Frequency synthesizers |
| ISBN |
1-280-27201-5
9786610272013 0-470-29946-0 0-470-86512-1 0-470-01410-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Phase Lock Loops and Frequency Synthesis; Contents; Preface; 1 Basic Equations of the PLLs; 1.1 Introduction; 1.2 Basic Equations of the PLLs; 1.3 Solution of the Basic PLL Equation in the Time Domain; 1.3.1 Solution in the Closed Form; 1.3.2 Linearized Solution; 1.4 Solution of Basic PLL Equations in the Frequency Domain; 1.5 Order and Type of PLLs; 1.5.1 Order of PLLs; 1.5.2 Type of PLLs; 1.5.3 Steady State Errors; 1.6 Block Diagram Algebra; References; 2 PLLs of the First and Second Order; 2.1 PLLs of the First Order; 2.2 PLLs of the Second Order; 2.2.1 A Simple RC Filter
2.2.2 Phase Lag-lead RRC or RCC Filter2.3 PLLs of the Second Order of Type 2; 2.3.1 PLLs of the Second Order of Type 2 with Voltage Output PD; 2.3.2 PLLs of the Second Order of Type 2 with Current Output Phase Detector; 2.4 Second-order PLLs with Frequency Dividers in the Feedback Path; References; 3 PLLs of the Third and Higher Orders; 3.1 General Open-loop Transfer Function G(s); 3.1.1 Additional RC Section; 3.1.2 Two RC Sections; 3.1.3 Active Second-order Low-pass Filter; 3.1.4 Twin-T RC Filter; 3.1.5 PLLs with a Selective Filter in the Feedback Path; 3.1.6 Time Delays in PLLs 3.2 Higher-order Type 2 PLLs3.2.1 Third-order Loops: Lag-lead Filter with Additional RC Section; 3.2.2 Third-order Loop: Second-order Lag Filter Plus RC Section; 3.2.3 Fourth-order Loops; 3.2.4 Fifth-order Loops; 3.3 PLLs with Transmission Blocks in the Feedback Path; 3.3.1 Divider in the Feedback Path; 3.3.2 IF Filter in the Feedback Path; 3.3.3 IF Filter and Divider in the Feedback Path; 3.4 Sampled Higher-order Loops; 3.4.1 Third-order Loops with the Current Output Phase Detector; 3.5 Higher-order Loops of Type 3; 3.6 Computer Design of a Higher-order PLL; References 4 Stability of the PLL Systems4.1 Hurwitz Criterion of Stability; 4.2 Computation of the Roots of the Polynomial P(s); 4.3 Expansion of the Function 1/[1 + G(s)] into a Sum of Simple Fractions; 4.3.1 Polynomial S(s) Contains Simple Roots Only; 4.3.2 Polynomial S(s) Contains a Pair of Complex Roots; 4.3.3 Polynomial S(s) Contains Multiple-order Roots; 4.4 The Root-locus Method; 4.5 Frequency Analysis of the Transfer Functions - Bode Plots; 4.5.1 Bode Plots; 4.5.2 Polar Diagrams; 4.6 Nyquist Criterion of Stability; 4.7 The Effective Damping Factor; 4.8 Appendix; References; 5 Tracking 5.1 Transients in PLLs5.1.1 Transients in First-order PLLs; 5.1.2 Transients in Second-order PLLs; 5.1.3 Transients in Higher-order Loops; 5.2 Periodic Changes; 5.2.1 Phase Modulation of the Input Signal; 5.2.2 Frequency Modulation of the Input Signal; 5.3 Discrete Spurious Signals; 5.3.1 Small Discrete Spurious Signals at the Input; 5.3.2 Small Spurious Signals at the Output of the Phase Detector; 5.3.3 Small Spurious Signals at the Output of the PLLs; References; 6 Working Ranges of PLLs; 6.1 Hold-in Range; 6.1.1 Phase Detector with the Sine Wave Output; 6.1.2 The PD with Triangular Output 6.1.3 The PD with a Sawtooth Wave Output |
| Record Nr. | UNINA-9910829852303321 |
|
Kroupa Věnceslav F. <1923->
|
||
| New York, : J. Wiley, 2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Phase-lock basics / / by William F. Egan
| Phase-lock basics / / by William F. Egan |
| Autore | Egan William F |
| Edizione | [2nd ed.] |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : John Wiley, , 2008 |
| Descrizione fisica | 1 online resource (473 p.) |
| Disciplina | 621.3815364 |
| Soggetto topico |
Phase-locked loops
Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
1-281-09415-3
9786611094157 0-470-17873-6 0-470-17871-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Pt. 1. Phase Lock Without Noise. -- 1. Introduction (p. 3) -- 2. The Basic Loop (p. 15) -- 3. Loop Components (p. 29) -- 4. Loop Response (p. 59) -- 5. Loop Stability (p. 71) -- 6. Transient Response (p. 87) -- 7. Modulation Response (p. 111) -- 8. Acquisition (p. 137) -- 9. Acquisition Aids (p. 171) -- 10. Applications a Extensions (p. 189) -- Pt. 2. Phase Lock in Noise. -- 11. Phase Modulation By Noise (p. 233) -- 12. Response to Phase Noise (p. 251) -- 13. Representation of Additive Noise (p. 271) -- 14. Loop Response to Additive Noise (p. 287) -- 15. Phase-Locked Loop as a Demodulator (p. 297) -- 16. Parameter Variation Due to Noise (p. 319) -- 17. Cycle Skipping Due to Noise (p. 335) -- 18. Nonlinear Operation in a Locked Loop (p. 359) -- 19. Acquisition Aids in the Presence of Noise (p. 377) -- 20. Bandlimited Noise (p. 395) -- 21. Further Information (p. 415) |
| Record Nr. | UNINA-9910144583203321 |
|
Egan William F
|
||
| Hoboken, New Jersey : , : John Wiley, , 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Phase-lock basics / / by William F. Egan
| Phase-lock basics / / by William F. Egan |
| Autore | Egan William F |
| Edizione | [2nd ed.] |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : John Wiley, , 2008 |
| Descrizione fisica | 1 online resource (473 p.) |
| Disciplina | 621.3815364 |
| Soggetto topico |
Phase-locked loops
Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN |
1-281-09415-3
9786611094157 0-470-17873-6 0-470-17871-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Pt. 1. Phase Lock Without Noise. -- 1. Introduction (p. 3) -- 2. The Basic Loop (p. 15) -- 3. Loop Components (p. 29) -- 4. Loop Response (p. 59) -- 5. Loop Stability (p. 71) -- 6. Transient Response (p. 87) -- 7. Modulation Response (p. 111) -- 8. Acquisition (p. 137) -- 9. Acquisition Aids (p. 171) -- 10. Applications a Extensions (p. 189) -- Pt. 2. Phase Lock in Noise. -- 11. Phase Modulation By Noise (p. 233) -- 12. Response to Phase Noise (p. 251) -- 13. Representation of Additive Noise (p. 271) -- 14. Loop Response to Additive Noise (p. 287) -- 15. Phase-Locked Loop as a Demodulator (p. 297) -- 16. Parameter Variation Due to Noise (p. 319) -- 17. Cycle Skipping Due to Noise (p. 335) -- 18. Nonlinear Operation in a Locked Loop (p. 359) -- 19. Acquisition Aids in the Presence of Noise (p. 377) -- 20. Bandlimited Noise (p. 395) -- 21. Further Information (p. 415) |
| Record Nr. | UNINA-9910830143903321 |
|
Egan William F
|
||
| Hoboken, New Jersey : , : John Wiley, , 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Phase-locked loop engineering handbook for integrated circuits / / Stanley Goldman
| Phase-locked loop engineering handbook for integrated circuits / / Stanley Goldman |
| Autore | Goldman Stanley J. |
| Pubbl/distr/stampa | Boston : , : Artech House, , ©2007 |
| Descrizione fisica | 1 online resource (572 p.) |
| Disciplina | 621.3815364 |
| Collana | Artech House microwave library |
| Soggetto topico |
Integrated circuits - Design and construction
Phase-locked loops |
| Soggetto genere / forma | Electronic books. |
| ISBN | 1-59693-155-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Phase-Locked Loop Engineering Handbook for Integrated Circuits; Contents vii; Preface xiii; Acknowledgments xxi; Chapter 1 Getting Started with PLLs 1; Chapter 2 System Analysis 15; Chapter 3 System Requirements 35; Chapter 4 Components, Part 1-Dividers and Oscillators 163; Chapter 5 Components, Part 2-Detectors and Other Circuits 235; Chapter 6 Loop-Compensation Synthesis Revisited 307; Chapter 7 Test and Measurement 353; Chapater 8 Simulation 405; Chapter 9 Applications and Extensions 445; Appendix A Letter Symbols 529; Appendix B Glossary 533; About the Author 541; Index 543 |
| Record Nr. | UNINA-9910454386903321 |
|
Goldman Stanley J.
|
||
| Boston : , : Artech House, , ©2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Phase-locked loop engineering handbook for integrated circuits / / Stanley Goldman
| Phase-locked loop engineering handbook for integrated circuits / / Stanley Goldman |
| Autore | Goldman Stanley J. |
| Pubbl/distr/stampa | Boston : , : Artech House, , ©2007 |
| Descrizione fisica | 1 online resource (572 p.) |
| Disciplina | 621.3815364 |
| Collana | Artech House microwave library |
| Soggetto topico |
Integrated circuits - Design and construction
Phase-locked loops |
| ISBN | 1-59693-155-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Phase-Locked Loop Engineering Handbook for Integrated Circuits; Contents vii; Preface xiii; Acknowledgments xxi; Chapter 1 Getting Started with PLLs 1; Chapter 2 System Analysis 15; Chapter 3 System Requirements 35; Chapter 4 Components, Part 1-Dividers and Oscillators 163; Chapter 5 Components, Part 2-Detectors and Other Circuits 235; Chapter 6 Loop-Compensation Synthesis Revisited 307; Chapter 7 Test and Measurement 353; Chapater 8 Simulation 405; Chapter 9 Applications and Extensions 445; Appendix A Letter Symbols 529; Appendix B Glossary 533; About the Author 541; Index 543 |
| Record Nr. | UNINA-9910782299303321 |
|
Goldman Stanley J.
|
||
| Boston : , : Artech House, , ©2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Phaselock techniques [[electronic resource] /] / Floyd M. Gardner
| Phaselock techniques [[electronic resource] /] / Floyd M. Gardner |
| Autore | Gardner Floyd Martin <1929-> |
| Edizione | [3rd ed.] |
| Pubbl/distr/stampa | Hoboken, NJ, : John Wiley, 2005 |
| Descrizione fisica | 1 online resource (449 p.) |
| Disciplina |
621.3815/364
621.3815364 |
| Soggetto topico | Phase-locked loops |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-27731-9
9786610277315 0-471-73269-9 0-471-73268-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
PHASELOCK TECHNIQUES; CONTENTS; PREFACE; NOTATION; 1 INTRODUCTION; 1.1 Salient Properties of PLLs; 1.1.1 Bandwidth; 1.1.2 Linearity; 1.2 Organization of the Book; 1.3 Annotated Bibliography; 1.3.1 Books; 1.3.2 Reprint Volumes; 1.3.3 Journal Special Issues; 2 TRANSFER FUNCTIONS OF ANALOG PLLs; 2.1 Basic Transfer Functions; 2.1.1 Transfer Functions of Individual Elements; 2.1.2 Combined Transfer Functions; 2.1.3 Characteristic Equation; 2.1.4 Nomenclature, Coefficients, and Units; 2.2 Second-Order PLLs; 2.2.1 Loop Filters; 2.2.2 Order and Type; 2.2.3 Loop Parameters; 2.2.4 Frequency Response
2.3 Other Loop Types and Orders2.3.1 General Definition of Loop Gain K; 2.3.2 Examples of Type 1 PLLs; 2.3.3 Examples of Type 2 PLLs; 2.3.4 Higher-Type PLLs; Reference; 3 GRAPHICAL AIDS; 3.1 Root-Locus Plots; 3.1.1 Description of Root-Locus Plots; 3.1.2 Stability Criterion; 3.1.3 Root Loci of Type 1 PLLs; 3.1.4 Root Loci of Type 2 PLLs; 3.1.5 Root Loci of Type 3 PLLs; 3.1.6 Root Loci of Higher-Order PLLs; 3.1.7 Effect of Loop Delay on Root Locus; 3.2 Bode Plots; 3.2.1 Presentation Options; 3.2.2 Stability; 3.2.3 Bode Plots of Type 1 PLLs; 3.2.4 Bode Plots of Type 2 PLLs 3.2.5 Bode Plots of Type 3 PLLs3.3 Nyquist Diagrams; 3.4 Nichols Charts; 3.4.1 Stability Criterion; 3.4.2 M-Contours; 3.4.3 Examples of Nichols Charts; 3.5 Closed-Loop Frequency-Response Curves; Appendix 3A: Salient Features of Root Loci; 3A.1 Branches of Root Loci; 3A.2 Locus on the Real Axis; 3A.3 Locus Intersections with Axes; Appendix 3B: Formats of the Open-Loop Transfer Function G(s); 3B.1 Proportional-Plus-Integral Section; 3B.2 High-Frequency Section; 3B.3 Calculations; Appendix 3C: Closed-Loop Frequency Responses; 3C.1 Frequency-Response Formulas 3C.2 Example Frequency-Response GraphsReferences; 4 DIGITAL PLLs: TRANSFER FUNCTIONS AND RELATED TOOLS; 4.1 Distinctive Properties of Digital PLLs; 4.2 Digital Transfer Function; 4.2.1 Configuration of a Digital PLL; 4.2.2 Difference Equations; 4.2.3 z-Transforms of the Loop Elements; 4.2.4 Loop Filter; 4.2.5 Loop Transfer Functions; 4.2.6 Poles and Zeros; 4.3 Loop Stability; 4.3.1 Type 1 DPLLs; 4.3.2 Type 2 DPLLs; 4.3.3 Type 3 DPLLs; 4.4 Root-Locus Plots; 4.4.1 Root Loci of Type 1 DPLLs; 4.4.2 Root Loci of Type 2 DPLLs; 4.4.3 Root Loci of Type 3 DPLLs 4.5 DPLL Frequency Responses: Formulation4.6 Bode Plots and Nichols Charts; 4.6.1 Basis of Bode Plots; 4.6.2 Bode Stability Criteria; 4.6.3 Bode Plots of Example DPLLs; 4.6.4 Nichols Chart Example; 4.7 Time-Continuous Approximation for a DPLL; 4.8 Frequency-Response Examples; 4.8.1 Effect of Delay; 4.8.2 Effect of Bandwidth; 4.9 Lowpass Filters in the Loop; 4.9.1 Infinite Impulse Response Lowpass Filter; 4.9.2 Finite Impulse Response Lowpass Filter; Appendix 4A: Stability of Digital Phaselock Loops; 4A.1 Type 1 DPLL; 4A.2 Type 2 DPLL; Reference; 5 TRACKING; 5.1 Linear Tracking 5.1.1 Steady-State Phase Errors |
| Record Nr. | UNINA-9910143574703321 |
|
Gardner Floyd Martin <1929->
|
||
| Hoboken, NJ, : John Wiley, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
