Pubbl/distr/stampa	New York, New York : , : IEEE, , 2020
Descrizione fisica	1 online resource (641 pages)
Disciplina	621.381531
Soggetto topico	Printed circuits - Design and construction
ISBN	1-5044-6355-2
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Altri titoli varianti	1481-2019 - IEEE Standard for Integrated Circuit
Record Nr.	UNINA-9910389549503321

Pubbl/distr/stampa	[Place of publication not identified], : I E E E, 2007
Descrizione fisica	1 online resource
Disciplina	621.381531
Soggetto topico	Printed circuits Signal theory (Telecommunication)
ISBN	1-5090-8232-8 1-4244-1224-2
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Record Nr.	UNISA-996215960703316

Autore	Bogatin Eric
Pubbl/distr/stampa	Norwood : , : Artech House, , 2021
Descrizione fisica	1 online resource (521 pages)
Disciplina	621.381531
Soggetto topico	Printed circuits
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	BOGATIN'S PRACTICAL GUIDE to PROTOTYPE BREADBOARD and PCB DESIGN -- Table of Contents -- Chapter 1 A Getting-Started Guide -- 1.1 Who This Book Is For -- 1.2 Getting Stuff Done -- 1.3 Cost-Performace Trade-offs -- 1.4 Errors, Best Practices, and Habits -- 1.5 Learn to Design-in Success -- 1.6 A Getting-Started Guide for Signal Integrity -- 1.7 The Seven-Step Process -- 1.8 Risk Management and Mitigation -- 1.9 Two Risk Management Design Strategies -- 1.0 Master of Murphy's Law -- 1.11 Proof of Concept -- 1.12 Practice Questions -- Chapter 2 PCB Technology -- 2.1 PCB, PWB, or PCA? -- 2.2 Physical Design of a PCB -- 2.3 Vias Technologies -- 2.4 Thermal and Thermal Relief Vias -- 2.5 Other Layers -- 2.6 The Soldermask Layer -- 2.7 Surface Finishes -- 2.8 The Silk Screen -- 2.9 What the Fab Vendor Needs -- 2.10 Practice Questions -- Chapter 3 Signal Integrity and Interconnects -- 3.1 Transparent Interconnects -- 3.2 When Interconnets are NOT Transparent -- 3.3 Where Signal Integrity Lives -- 3.4 Six Categories of Electrical Noise -- 3.5 Families of SI/PI/EMI Problems -- 3.6 In Principle and In Practice -- 3.7 Net Classes and Interconnect Problems -- 3.9 Design for X -- 3.10 Practice Questions -- Chapter 4 Electrical Properties of Interconnects -- 4.1 Ideal vs Real Circuit Elements -- 4.2 Equivalent Electrical Circuit Models -- 4.3 Parasitic Extraction of R, L, and C Elements -- 4.4 Describing Cross Talk -- 4.5 Estimating Mutual Inductance -- 4.6 Training Your Engineer's Mind's Eye -- 4.7 Electrically Long Interconnects -- 4.8 Electrically Short and Electrically Long -- 4.9 Practice Questions -- Chapter 5 Trace Width Considerations: Max Current -- 5.1 Best design practices -- 5.2 Minimum Fabrication Trace Width -- 5.3 Copper Thickness as Ounces of Copper -- 5.4 Maximum Current Handling of a Trace -- 5.5 Maximum Current Through a Via. 5.6 Thermal Runaway with Constant Current -- 5.7 Practice Questions -- Chapter 6 Trace Width Considerations: Series Resistance -- 6.1 Resistance of Any Uniform Conductor -- 6.2 Sheet Resistance of a Copper Layer -- 6.3 Measuring Very Low Resistances -- 6.4 Voltage Drop Across Traces -- 6.5 The Thevenin Model of a Voltage Source -- 6.6 How Much Trace Resistance Is too Much? -- 6.7 The Resistance of a Via -- 6.8 Resistance of a Thermal Relief Via -- 6.9 Practice Questions -- Chapter 7 The Seven Steps in Creating a PCB -- 7.1 Step 1: Plan of Record -- 7.2 Step 2: Create the BOM -- 7.3 Step 3: Complete the Schematic -- 7.4 Step 4: Complete the Layout, Order the Parts -- 7.5 Steps 5 and 6: Assembly and Bring-Up -- 7.6 Step 7: Documentation -- 7.7 Practice Questions -- Chapter 8 Step 1, POR: Risk Mitigation -- 8.1 Visualize the Entire Project Before You Begin -- 8.2 Avoid Feature Creep -- 8.3 Estimate Everything You Can -- 8.4 Preliminary BOM: Critical Components -- 8.5 Risk Assessment -- 8.6 Risk Mitigation: Tented Vias -- 8.7 Risk Mitigation: Qualified Parts -- 8.8 Practice Questions -- Chapter 9 Risk Reduction: Datasheets, Reverse Engineering, and Component Selection -- 9.1 Take Responsibility for Your Design -- 9.2 Reducing the Risk of a Design Problem -- 9.3 Understand Your Circuit -- 9.4 Read Datasheets Critically -- 9.5 Build Simple Evaluation Prototypes -- 9.6 Reverse Engineer Components -- 9.7 Reuse Parts -- 9.8 Practice Questions -- Chapter 10 Risk Reduction: Virtual and Real Prototypes -- 10.1 Getting Started with Circuit Simulation -- 10.2 Practice Safe Simulation -- 10.3 Simulating a 555 Circuit -- 10.4 Purchase an Evaluation Board -- 10.5 Real Prototypes with Modules -- 10.6 Practice Questions -- Chapter 11 Risk Reduction: Prototyping with a Solderless Breadboard -- 11.1 Build a Real Prototype -- 11.2 Solderless Breadboards for POC. 11.3 Features of a Solderless Breadboard -- 11.4 Bandwidth Limitations -- 11.5 A Simple Breakout Board -- 11.6 The Mini Solderless Breadboard -- 11.7 Best Wiring Habits -- 11.8 Habit #1: Consistent Column Assignments -- 11.9 Habit #2: Color Code the Wires -- 11.10 Habit #3: Keep Signal Traces Short -- 11.11 Habit #4: Avoid a Shared Return Path -- 11.12 Habit #5: Route Signal-Return Pairs -- 11.13 Habit #6: Keep Component Leads Short -- 11.14 Practice Questions -- Chapter 12 Switching Noise and Return Path Routing -- 12.1 The Origin of Switching Noise -- 12.2 Signal-Return Path Loops -- 12.3 Where Does Return Current Flow? -- 12.4 A Plane as a Return Path -- 12.5 Ground -- 12.6 Avoid Gaps in the Return Plane -- 12.7 Summary of the Best design practices -- 12.8 Practice Questions -- Chapter 13 Power Delivery -- 13.1 Origin of Power Rail Switching Noise -- 13.2 Calculating Loop Inductance -- 13.3 Measuring PDN Switching Noise -- 13.4 The Role of Decoupling Capacitors -- 13.5 Where Do Decoupling Capacitors Go? -- 13.6 The Power Delivery Path -- 13.7 Inrush Current -- 13.8 Summary of the Eight Habits for Using a SSB -- 13.9 Practice Questions -- Chapter 14 Design for Performance: The PDN on a PCB -- 14.1 VRM specifications -- 14.2 Voltage Regulator Module -- 14.3 Self- and Mutual-Aggression Noise -- 14.4 Power and Ground Loop Inductance -- 14.5 Decoupling Capacitors -- 14.6 A Decoupling Capacitor Myth -- Part 1 -- 14.7 A Decoupling Capacitor Myth -- Part 2 -- 14.8 Routing for Power Distribution -- 14.9 Ferrite Beads -- 14.10 Summary of the Best design practices -- 14.11 Practice Questions -- Chapter 15 Risk Reduction: Design for Bring-Up -- 15.1 Test is Too General a Term -- 15.2 What Does It Mean to "Work"? -- 15.3 Design for Bring-Up -- 15.4 Add Design for Bring-Up Features -- 15.5 Jumper Switches -- 15.6 LED indicators -- 15.7 Test Points. 15.8 The Power Rail as a Diagnostic -- 15.9 Practice Questions -- Chapter 16 Risk Reduction: Design Reviews -- 16.1 The Preliminary Design Review -- 16.2 The Critical Design Review -- 16.3 DRC for DFM in the CDR -- 16.4 DRC for Signal Integrity -- 16.5 Layout Review -- 16.6 Practice Questions -- Chapter 17 Step 2: Surface-Mount or Through-Hole Parts -- 17.1 Through-Hole and Surface-Mount -- 17.2 Types of SMT Parts -- 17.3 Integrated Circuit Components -- 17.4 Practice Questions -- Chapter 18 Finding the One Part in a Million -- 18.1 An Important Selection Process -- 18.2 Trade-offs in Selecting Parts -- 18.3 The Search Order to Select a Part -- 18.4 Selecting Resistors -- 18.5 Selecting Capacitors -- 18.6 The BOM -- 18.7 Summary of the Best Design Practices -- 18.8 Selecting Parts for Automated Assembly -- 18.9 Practice Questions -- Chapter 19 Step 3: Schematic Capture and Final BOM -- 19.1 Picking a Project Name -- 19.2 Schematic Capture -- 19.3 Take Ownership of Reference Designs -- 19.4 Add Options to Your Schematic -- 19.5 Best design practices for Schematic Entry -- 19.6 Design Review and ERC -- 19.7 Practice Questions -- Chapter 20 Step 4: Layout - Setting Up the Board -- 20.1 Layout -- 20.2 Board Dimensions -- 20.3 The Layers in a Board Stack -- 20.4 Negative and Positive Layers -- 20.5 Examples of Some Fab Shop DFM Features -- 20.6 Setting Up Design Constraints -- 20.7 Thermal Reliefs in Pads and Vias -- 20.8 Set Up Board Size and Keepout Layer -- 20.9 Practice Questions -- Chapter 21 Floor Planning and Routing Priority -- 21.1 Part Placement -- 21.2 The Order of Placement and Routing -- 21.3 First Priority: Ground Plane on the Bottom Layer -- 21.4 Second Priority: Decoupling Capacitors -- 21.5 Third Priority: Ground Connections -- 21.6 Fourth Priority: Digital Signals, Congested Signals -- 21.7 Fifth Priority: Power Paths. 21.8 The Silk Screen -- 21.9 Check the Soldermask -- 21.10 Soldermask Color -- 21.11 Layout - Critical Design Review -- 21.12 Practice Questions -- Chapter 22 Six Common Misconceptions about Routing -- 22.1 Myth #1: Avoid 90 Deg Corners -- 22.2 Myth #2: Add Copper Pour on Signal Layers -- 22.3 Myth #3: Use Different Value Decoupling Capacitors -- 22.4 Myth #4: Split Ground Plan -- 22.5 Myth #5: Use Power Planes -- 22.6 Myth #6: Use 50 Ohm Impedance Traces -- 22.7 Practice Questions -- Chapter 23 Four-Layer Boards -- 23.1 Two-Layer Stack-Ups -- 23.2 A 4-Layer Board -- 23.3 Four-Layer Stack-Up Options -- 23.4 Stack-Up Options with Two Planes -- 23.5 The Recommended 4-Layer Stack-Up -- 23.6 When Signals Change Return Planes -- 23.7 Practice Questions -- Chapter 24 Release the Board to the Fab Shop -- 24.1 Gerber Files -- 24.2 Cost Adders -- 24.3 Board Release Checklist -- 24.4 Practice Questions -- Chapter 25 Step 6: Bring-Up -- 25.1 Does Your Widget Work? -- 25.2 Prototype or Production Testing -- 25.3 Design for Bring-Up -- 25.4 Find the Root Cause -- 25.5 Problems to Expect -- 25.6 Troubleshoot Like a Detective -- 25.7 Trick #1: Recreate the Problem -- 25.8 Trick #2: Seen This Problem Before? -- 25.9 Trick #3: Round Up the Usual Suspects -- 25.10 Trick #4: Three Possible Explanations -- 25.11 A Methodology -- 25.12 Forensic Analysis -- 25.13 Coding Issues -- 25.14 Practice Questions -- Chapter 26 Step 7: Documentation -- Chapter 27 Concluding Comments -- Chapter 28 About Eric Bogatin.
Record Nr.	UNINA-9910794629003321

Pubbl/distr/stampa	London, : ISTE
Descrizione fisica	1 online resource (348 p.)
Disciplina	621.3815/31 621.381531 621.39
Altri autori (Persone)	KriefFrancine
Collana	ISTE
Soggetto topico	Networks on a chip
Soggetto genere / forma	Electronic books.
ISBN	1-118-55762-X 1-299-31539-9 1-118-61851-3
Classificazione	ST 153
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Cover; Communicating Embedded Systems; Title Page; Copyright Page; Table of Contents; General Introduction; Chapter 1. Introduction to Embedded Systems; 1.1. Introduction; 1.2. Embedded system: a definition; 1.3. Properties of an embedded system; 1.4. The significance of Moore's Law; 1.5. Embedded systems and the system on silicon; 1.6. Embedded systems and communications; 1.7. Embedded systems and security; 1.8. Embedded systems and time constraints; 1.9. Embedded systems and free software; 1.10. Embedded systems and their design; 1.11. An example of multimedia embedded system design 1.12. Conclusion1.13. Bibliography; Chapter 2. Quality-of-Service Routing in Mobile Ad Hoc Networks; 2.1. Introduction; 2.2. Mobile ad hoc networks: concepts, characteristics, challenges; 2.2.1. Concepts and basic principles; 2.2.2. Limits and challenges; 2.2.3. MAC protocols for ad hoc networks; 2.2.4. Node mobility and location; 2.3. QoS routing: general considerations; 2.3.1. Functions of routing protocols; 2.3.2. Classification of routing protocols; 2.3.3. Expected routing protocol properties; 2.3.4. QoS routing problems; 2.4. Best-effort routing protocols in MANETs 2.4.1. Criteria for routing protocol classification2.4.2. Presentation of routing protocols; 2.5. QoS routing in MANETs; 2.5.1. Approaches for QoS routing; 2.5.2. Resource reservation; 2.5.3. Examples of reservation methods; 2.5.4. Estimation models; 2.5.5. Presentation of the main QoS routing protocols; 2.6. Conclusion; 2.7. Bibliography; Chapter 3. Self-Management of Ad Hoc Sensor Networks; 3.1. Introduction; 3.2. Wireless sensor networks; 3.2.1. Fields of application for sensor networks; 3.2.2. The principal components in a sensor; 3.2.3. Importance of energy in sensor networks 3.2.4. Transmission technologies3.2.5. Routing algorithms; 3.2.6. Main commercial offerings; 3.2.7. Key issues; 3.2.8. Projects on sensor networks; 3.3. Autonomic sensor networks; 3.3.1. Autonomic networking; 3.3.2. Self-configuration of sensor networks; 3.3.3. Self-healing of sensor networks; 3.3.4. Self-optimization of sensor networks; 3.3.5. Self-protection of sensor networks; 3.3.6. Projects relating to autonomy in sensor networks; 3.4. An example of self-configuration; 3.4.1. Energy optimization and automatic classification; 3.4.2. The LEA2C energy optimization algorithm 3.4.3. Performance evaluation of the LEA2C algorithm3.4.4. Improvements to the LEA2C algorithm; 3.5. Conclusion; 3.6. Bibliography; Chapter 4. RFID Technology; 4.1. Introduction; 4.2. Automatic identification systems; 4.2.1. Barcodes; 4.2.2. Optical character recognition (OCR) systems; 4.2.3. Biometric identification; 4.2.4. Microchip cards; 4.2.5. RFID systems; 4.3. The components of an RFID system; 4.4. The different types of RFID systems; 4.4.1. Bottom of the range RFID systems; 4.4.2. Mid-range RFID systems; 4.4.3. Top of the range RFID systems; 4.5. RF ranges; 4.6. Information security 4.6.1. Symmetric mutual authentication
Record Nr.	UNINA-9910139247003321

Autore	Mitzner, Kraig
Pubbl/distr/stampa	Amsterdam ; Boston, : Elsevier, : Newnes, 2007
Descrizione fisica	XIX, 508 p. : ill. in parte color. ; 24 cm + 1 CD-ROM
Disciplina	621.3815 621.381531
Soggetto topico	Circuiti stampati - Progettazione
ISBN	0750682140 9780750682145
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Record Nr.	UNISANNIO-NAP0522822