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Advanced frequency synthesis by phase lock / / William F. Egan
| Advanced frequency synthesis by phase lock / / William F. Egan |
| Autore | Egan William F |
| Pubbl/distr/stampa | Hoboken, New Jersey, : Wiley, 2011 |
| Descrizione fisica | 1 online resource (314 p.) |
| Disciplina | 621.3815/486 |
| Soggetto topico |
Frequency synthesizers
Phase-locked loops |
| ISBN |
9786613337535
9781283337533 1283337533 9781118171158 1118171152 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Frontmatter -- Introduction -- Fractional-N and Basic S? Synthesizers -- Other Spurious Reduction Techniques -- Defects in S? Synthesizers -- Other S? Architectures -- Simulation -- Diophantine Synthesizer -- Operation at Extreme Bandwidths -- All-Digital Frequency Synthesizers -- Appendix A: All Digital -- Appendix C: Fractional Cancellation -- Appendix E: Excess PPSD -- Appendix F: References to -- Appendix G: Using Gsmpl -- Appendix H: Sample-and-Hold Circuit -- Appendix L: Loop Response -- Appendix M: Mash PPSD -- Appendix N: Sampled Noise -- Appendix O: Oscillator Spectrums -- Appendix P: Phase Detectors -- Appendix Q: Quantization PPSD -- Appendix R: Reference Frequency Spurs -- Appendix S: Spectrum Analysis -- Appendix T: Toolboxes -- Appendix U: Noise Produced by Charge Pump Current Unbalance (Mismatch) -- Appendix W: Getting Files from the Wiley Internet Site -- Appendix X: Some Tables -- End Notes -- References -- Index. |
| Record Nr. | UNINA-9911020046303321 |
Egan William F
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| Hoboken, New Jersey, : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
All-digital frequency synthesizer in deep-submicron CMOS / / Robert Bogdan Staszewski, Poras T. Balasara
| All-digital frequency synthesizer in deep-submicron CMOS / / Robert Bogdan Staszewski, Poras T. Balasara |
| Autore | Staszewski Robert Bogdan <1965-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley-Interscience, c2006 |
| Descrizione fisica | 1 online resource (281 p.) |
| Disciplina | 621.3815/486 |
| Altri autori (Persone) | BalsaraPoras T. <1961-> |
| Soggetto topico |
Frequency synthesizers - Design and construction
Wireless communication systems - Equipment and supplies - Design and construction Metal oxide semiconductors, Complementary - Design and construction |
| ISBN |
9786610654390
9781280654398 1280654392 9780470041956 0470041951 9780470041949 0470041943 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
ALL-DIGITAL FREQUENCY SYNTHESIZER IN DEEP-SUBMICRON CMOS; CONTENTS; PREFACE; Acknowledgments; 1 INTRODUCTION; 1.1 Frequency Synthesis; 1.1.1 Noise in Oscillators; 1.1.2 Frequency Synthesis Techniques; 1.2 Frequency Synthesizer as an Integral Part of an RF Transceiver; 1.2.1 Transmitter; 1.2.2 Receiver; 1.2.3 Toward Direct Transmitter Modulation; 1.3 Frequency Synthesizers for Mobile Communications; 1.3.1 Integer-N PLL Architecture; 1.3.2 Fractional-N PLL Architecture; 1.3.3 Toward an All-Digital PLL Approach; 1.4 Implementation of an RF Synthesizer
1.4.1 CMOS vs. Traditional RF Process Technologies1.4.2 Deep-Submicron CMOS; 1.4.3 Digitally Intensive Approach; 1.4.4 System Integration; 1.4.5 System Integration Challenges for Deep-Submicron CMOS; 2 DIGITALLY CONTROLLED OSCILLATOR; 2.1 Varactor in a Deep-Submicron CMOS Process; 2.2 Fully Digital Control of Oscillating Frequency; 2.3 LC Tank; 2.4 Oscillator Core; 2.5 Open-Loop Narrowband Digital-to-Frequency Conversion; 2.6 Example Implementation; 2.7 Time-Domain Mathematical Model of a DCO; 2.8 Summary; 3 NORMALIZED DCO; 3.1 Oscillator Transfer Function and Gain; 3.2 DCO Gain Estimation 3.3 DCO Gain Normalization3.4 Principle of Synchronously Optimal DCO Tuning Word Retiming; 3.5 Time Dithering of DCO Tuning Input; 3.5.1 Oscillator Tune Time Dithering Principle; 3.5.2 Direct Time Dithering of Tuning Input; 3.5.3 Update Clock Dithering Scheme; 3.6 Implementation of PVT and Acquisition DCO Bits; 3.7 Implementation of Tracking DCO Bits; 3.7.1 High-Speed Dithering of Fractional Varactors; 3.7.2 Dynamic Element Matching of Varactors; 3.7.3 DCO Varactor Rearrangement; 3.8 Time-Domain Model; 3.9 Summary; 4 ALL-DIGITAL PHASE-LOCKED LOOP; 4.1 Phase-Domain Operation 4.2 Reference Clock Retiming4.3 Phase Detection; 4.3.1 Difference Mode of ADPLL Operation; 4.3.2 Integer-Domain Operation; 4.4 Modulo Arithmetic of the Reference and Variable Phases; 4.4.1 Variable-Phase Accumulator (PV Block); 4.5 Time-to-Digital Converter; 4.5.1 Frequency Reference Edge Estimation; 4.6 Fractional Error Estimator; 4.6.1 Fractional-Division Ratio Compensation; 4.6.2 TDC Resolution Effect on Estimated Frequency Resolution; 4.6.3 Active Removal of Fractional Spurs Through TDC (Optional); 4.7 Frequency Reference Retiming by a DCO Clock; 4.7.1 Sense Amplifier-Based Flip-Flop 4.7.2 General Idea of Clock Retiming4.7.3 Implementation; 4.7.4 Time-Deferred Calculation of the Variable Phase (Optional); 4.8 Loop Gain Factor; 4.8.1 Phase-Error Dynamic Range; 4.9 Phase-Domain ADPLL Architecture; 4.9.1 Close-in Spurs Due to Injection Pulling; 4.10 PLL Frequency Response; 4.10.1 Conversion Between the s- and z-Domains; 4.11 Noise and Error Sources; 4.11.1 TDC Resolution Effect on Phase Noise; 4.11.2 Phase Noise Due to DCO ΣΔ Dithering; 4.12 Type II ADPLL; 4.12.1 PLL Frequency Response of a Type II Loop; 4.13 Higher-Order ADPLL; 4.13.1 PLL Stability Analysis 4.14 Nonlinear Differential Term of an ADPLL |
| Record Nr. | UNINA-9911019333403321 |
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Staszewski Robert Bogdan <1965->
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| Hoboken, N.J., : Wiley-Interscience, c2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Architectures for RF frequency synthesizers
| Architectures for RF frequency synthesizers |
| Autore | Vaucher Cicero S |
| Pubbl/distr/stampa | Boston, MA : , : Springer US, , 2002 |
| Descrizione fisica | 1 online resource (XXVI, 250 p. 27 illus.) |
| Disciplina | 621.3815/486 |
| Collana | The Kluwer international series in engineering and computer science Architectures for RF frequency synthesizers |
| Soggetto topico |
Frequency synthesizers - Design and construction
Radio frequency oscillators Phase-locked loops Integrated circuits Radio frequency integrated circuits Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| Soggetto genere / forma | Electronic books. |
| ISBN | 0-306-47955-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Tuning System Specifications -- Single-Loop Architectures -- Wide-Band Tuning System Architectures -- Adaptive PLL Architecture Combining High Spectral Purity and Fast Settling Time -- Architecture and Circuit Design of Programmable Dividers -- Conclusions. |
| Record Nr. | UNINA-9910450040003321 |
|
Vaucher Cicero S
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||
| Boston, MA : , : Springer US, , 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Architectures for RF frequency synthesizers
| Architectures for RF frequency synthesizers |
| Autore | Vaucher Cicero S |
| Pubbl/distr/stampa | Boston, MA : , : Springer US, , 2002 |
| Descrizione fisica | 1 online resource (XXVI, 250 p. 27 illus.) |
| Disciplina | 621.3815/486 |
| Collana | The Kluwer international series in engineering and computer science Architectures for RF frequency synthesizers |
| Soggetto topico |
Frequency synthesizers - Design and construction
Radio frequency oscillators Phase-locked loops Integrated circuits Radio frequency integrated circuits Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN | 0-306-47955-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Tuning System Specifications -- Single-Loop Architectures -- Wide-Band Tuning System Architectures -- Adaptive PLL Architecture Combining High Spectral Purity and Fast Settling Time -- Architecture and Circuit Design of Programmable Dividers -- Conclusions. |
| Record Nr. | UNINA-9910783114603321 |
|
Vaucher Cicero S
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||
| Boston, MA : , : Springer US, , 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Automated calibration of modulated frequency synthesizers [[electronic resource] /] / Dan McMahill
| Automated calibration of modulated frequency synthesizers [[electronic resource] /] / Dan McMahill |
| Autore | McMahill Dan |
| Edizione | [1st ed. 2002.] |
| Pubbl/distr/stampa | Boston, : Kluwer Academic, c2002 |
| Descrizione fisica | 1 online resource (173 p.) |
| Disciplina | 621.3815/486 |
| Collana | The Kluwer international series in engineering and computer science ;Analog circuits and signal processing |
| Soggetto topico |
Frequency synthesizers - Calibration
Frequency synthesizers - Automatic control |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-280-20003-0
9786610200030 0-306-47516-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Architectures -- System Requirements -- Automatic Calibration System -- Implementation Details -- Experimental Results -- Summary and Conclusions. |
| Record Nr. | UNINA-9910454811503321 |
|
McMahill Dan
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||
| Boston, : Kluwer Academic, c2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Automated Calibration of Modulated Frequency Synthesizers [[electronic resource] /] / by Dan McMahill
| Automated Calibration of Modulated Frequency Synthesizers [[electronic resource] /] / by Dan McMahill |
| Autore | McMahill Dan |
| Edizione | [1st ed. 2002.] |
| Pubbl/distr/stampa | New York, NY : , : Springer US : , : Imprint : Springer, , 2002 |
| Descrizione fisica | 1 online resource (173 p.) |
| Disciplina | 621.3815/486 |
| Collana | The Springer International Series in Engineering and Computer Science |
| Soggetto topico |
Electronic circuits
Electrical engineering Electronic Circuits and Systems Electrical and Electronic Engineering |
| ISBN |
1-280-20003-0
9786610200030 0-306-47516-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Architectures -- System Requirements -- Automatic Calibration System -- Implementation Details -- Experimental Results -- Summary and Conclusions. |
| Record Nr. | UNINA-9910780035503321 |
|
McMahill Dan
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||
| New York, NY : , : Springer US : , : Imprint : Springer, , 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Frequency acquisition techniques for phase locked loop / / author Daniel Talbot
| Frequency acquisition techniques for phase locked loop / / author Daniel Talbot |
| Autore | Talbot Daniel (Daniel B.) |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : John Wiley & Sons, Inc., , [2012] |
| Descrizione fisica | 1 online resource (238 p.) |
| Disciplina |
621.3815/486
621.382 |
| Soggetto topico |
Frequency synthesizers
Phase-locked loops |
| ISBN |
1-118-38330-3
1-283-59323-8 9786613905680 1-118-38331-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Preface xi -- 1 Introduction 1 -- 2 A Review of PLL Fundamentals 3 -- 2.1 What is a PLL?, 3 -- 2.2 Second-Order PLL, 7 -- 2.3 Second-Order PLL Type One, 7 -- 2.4 Second-Order PLL Type Two, 7 -- 2.5 Higher-Order PLL's, 8 -- 2.6 Disturbances, 8 -- 2.7 Frequency Steering and Capture, 9 -- 2.8 Effect of DC Offsets or Noise Prior to the Loop Filter, 10 -- 2.9 Injection-Locked Oscillations, 15 -- 3 Simulating the PLL Linear Operation Mode 17 -- 3.1 Linear Model, 17 -- 3.2 A Word About Damping, 19 -- 4 Sideband Suppression Filtering 21 -- 4.1 Reference Sidebands and VCO Pushing, 21 -- 4.2 Superiority of the Cauer (or Elliptical) Filter, 22 -- 5 Pros and Cons of Sampled Data Phase Detection 25 -- 5.1 What are the Forms of Sampled Data Phase Detectors?, 25 -- 5.2 A. Ramp and Sample Analog Phase Detector, 25 -- 5.3 B. The RF Sampling Phase Detector, 28 -- 5.4 C. Edge-Triggered S-R Flip-Flop, 29 -- 5.5 D. Edge-Triggered Flip-Flop Ensemble, 31 -- 5.6 E. Sample and Hold as a Phase Detector, 31 -- 6 Phase Compression 33 -- 7 Hard Limiting of a Signal Plus Noise 35 -- 8 Phase Noise and Other Spurious Interferers 39 -- 8.1 The Mechanism for Phase Noise in an Oscillator, 42 -- 8.2 Additive Noise in an FM Channel and the Bowtie, 42 -- 8.3 Importance of FM Theory to Frequency Acquisition, 45 -- 9 Impulse Modulation and Noise Aliasing 47 -- 9.1 Impulse Train Spectrum, 47 -- 9.2 Sampling Phase Detector Noise, 47 -- 9.3 Spur Aliasing, 50 -- 10 Time and Phase Jitter, Heterodyning, and Multiplication 53 -- 10.1 Heterodyning and Resulting Time Jitter, 53 -- 10.2 Frequency Multiplication and Angle Modulation Index, 54 -- 10.3 Frequency Multiplication's Role in Carrier Recovery, 54 -- 11 Carrier Recovery Applications and Acquisition 57 -- 11.1 Frequency Multiplier Carrier Recovery in General, 57 -- 11.2 The Simplest Form of Costas PLL, 59 -- 11.3 Higher Level Quadrature Demodulation Costas PLL, 61 -- 11.4 False Lock in BPSK Costas PLL, 62 -- 11.5 Additional Measures for Prevention of False Locking, 65.
11.6 False Lock Prevention Using DC Offset, 72 -- 12 Notes on Sweep Methods 73 -- 12.1 Sweep Waveform Superimposed Directly on VCO Input, 73 -- 12.2 Maximum Sweep Rate (Acceleration), 74 -- 12.3 False Lock due to High-Order Filtering, 77 -- 12.4 Sweep Waveform Applied Directly to PLL Loop Integrator, 79 -- 12.5 Self-Sweeping PLL, 79 -- 13 Nonsweep Acquisition Methods 85 -- 13.1 Delay Line Frequency Discriminator, 85 -- 13.2 The Fully Unbalanced Quadricorrelator, 87 -- 13.3 The Fully Balanced Quadricorrelator, 88 -- 13.4 The Multipulse Balanced Quadricorrelator, 89 -- 13.5 Conclusion Regarding Pulsed Frequency Detection, 91 -- 13.6 Quadricorrelator Linearity, 92 -- 13.7 Limiter Asymmetry due to DC Offset, 97 -- 13.8 Taylor Series Demonstrates Second-Order-Caused DC Offset, 100 -- 13.9 Third-Order Intermodulation Distortion and Taylor Series, 101 -- 14 AM Rejection in Frequency Detection Schemes 105 -- 14.1 AM Rejection with Limiter and Interferer, 105 -- 14.2 AM Rejection of the Balanced Limiter/Quadricorrelator Versus the Limiter/Discriminator in the Presence of a Single Spur, 106 -- 14.3 Impairment due to Filter Response Tilt (Asymmetry), 110 -- 14.4 Bandpass Filter Geometric and Arithmetic Symmetry, 114 -- 14.5 Comments on Degree of Scrutiny, 117 -- 15 Interfacing the Frequency Discriminator to the PLL 119 -- 15.1 Continuous Connection: Pros and Cons, 119 -- 15.2 Connection to PLL via a Dead Band, 120 -- 15.3 Switched Connection, 121 -- 16 Actual Frequency Discriminator Implementations 125 -- 16.1 Quadricorrelator, Low-Frequency Implementation, 125 -- 16.2 Frequency Ratio Calculating Circuit for Wide-Bandwidth Use, 128 -- 16.3 Dividing the Frequency and Resultant Implementation, 131 -- 16.4 Marriage of Both Frequency and Phaselock Loops, 135 -- 16.5 Comments on Spurs' Numerical Influence on the VCO, 141 -- 16.6 Frequency Compression, 143 -- 17 Clock Recovery Using a PLL 145 -- 17.1 PLL Only, 145 -- 17.2 PLL with Sideband Crystal Filter(s), 152 -- 17.3 PLL with Sideband Cavity Filter, 153. 17.4 The Hogge Phase Detector, 161 -- 17.5 Bang-Bang Phase Detectors, 162 -- 18 Frequency Synthesis Applications 165 -- 18.1 Direct Frequency Synthesis with Wadley Loop, 166 -- 18.2 Indirect Frequency Synthesis with PLLs, 173 -- 18.3 Simple Frequency Acquisition Improvement for a PLL, 175 -- 18.4 Hybrid Frequency Synthesis with DDS and PLL, 176 -- 18.5 Phase Noise Considerations, 181 -- 18.6 Pros and Cons of DDS-Augmented Synthesis, 185 -- 18.7 Multiple Loops, 185 -- 18.8 Reference Signal Considerations and Filtering, 186 -- 18.9 SNR of Various Phase Detectors, 187 -- 18.10 Phase Detector Dead Band (Dead Zone) and Remediation, 187 -- 18.11 Sideband Energy due to DC Offset Following Phase Detector, 191 -- 18.12 Brute Force PLL Frequency Acquisition via Speedup, 193 -- 18.13 Short-Term and Long-Term Settling, 193 -- 18.14 N-over-M Synthesis, 193 -- 19 Injection Pulling of Multiple VCO's as in a Serdes 195 -- 19.1 Allowable Coupling Between any Two VCOs Versus Q and BW, 195 -- 19.2 Topology Suggestion for Eliminating the Injection Pulling, 195 -- 20 Digital PLL Example 199 -- 21 Conclusion 203 -- References 205 -- Index 209. |
| Record Nr. | UNINA-9910141433803321 |
|
Talbot Daniel (Daniel B.)
|
||
| Hoboken, New Jersey : , : John Wiley & Sons, Inc., , [2012] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Frequency acquisition techniques for phase locked loop / / author Daniel Talbot
| Frequency acquisition techniques for phase locked loop / / author Daniel Talbot |
| Autore | Talbot Daniel (Daniel B.) |
| Pubbl/distr/stampa | Hoboken, New Jersey : , : John Wiley & Sons, Inc., , [2012] |
| Descrizione fisica | 1 online resource (238 p.) |
| Disciplina |
621.3815/486
621.382 |
| Soggetto topico |
Frequency synthesizers
Phase-locked loops |
| ISBN |
1-118-38330-3
1-283-59323-8 9786613905680 1-118-38331-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Preface xi -- 1 Introduction 1 -- 2 A Review of PLL Fundamentals 3 -- 2.1 What is a PLL?, 3 -- 2.2 Second-Order PLL, 7 -- 2.3 Second-Order PLL Type One, 7 -- 2.4 Second-Order PLL Type Two, 7 -- 2.5 Higher-Order PLL's, 8 -- 2.6 Disturbances, 8 -- 2.7 Frequency Steering and Capture, 9 -- 2.8 Effect of DC Offsets or Noise Prior to the Loop Filter, 10 -- 2.9 Injection-Locked Oscillations, 15 -- 3 Simulating the PLL Linear Operation Mode 17 -- 3.1 Linear Model, 17 -- 3.2 A Word About Damping, 19 -- 4 Sideband Suppression Filtering 21 -- 4.1 Reference Sidebands and VCO Pushing, 21 -- 4.2 Superiority of the Cauer (or Elliptical) Filter, 22 -- 5 Pros and Cons of Sampled Data Phase Detection 25 -- 5.1 What are the Forms of Sampled Data Phase Detectors?, 25 -- 5.2 A. Ramp and Sample Analog Phase Detector, 25 -- 5.3 B. The RF Sampling Phase Detector, 28 -- 5.4 C. Edge-Triggered S-R Flip-Flop, 29 -- 5.5 D. Edge-Triggered Flip-Flop Ensemble, 31 -- 5.6 E. Sample and Hold as a Phase Detector, 31 -- 6 Phase Compression 33 -- 7 Hard Limiting of a Signal Plus Noise 35 -- 8 Phase Noise and Other Spurious Interferers 39 -- 8.1 The Mechanism for Phase Noise in an Oscillator, 42 -- 8.2 Additive Noise in an FM Channel and the Bowtie, 42 -- 8.3 Importance of FM Theory to Frequency Acquisition, 45 -- 9 Impulse Modulation and Noise Aliasing 47 -- 9.1 Impulse Train Spectrum, 47 -- 9.2 Sampling Phase Detector Noise, 47 -- 9.3 Spur Aliasing, 50 -- 10 Time and Phase Jitter, Heterodyning, and Multiplication 53 -- 10.1 Heterodyning and Resulting Time Jitter, 53 -- 10.2 Frequency Multiplication and Angle Modulation Index, 54 -- 10.3 Frequency Multiplication's Role in Carrier Recovery, 54 -- 11 Carrier Recovery Applications and Acquisition 57 -- 11.1 Frequency Multiplier Carrier Recovery in General, 57 -- 11.2 The Simplest Form of Costas PLL, 59 -- 11.3 Higher Level Quadrature Demodulation Costas PLL, 61 -- 11.4 False Lock in BPSK Costas PLL, 62 -- 11.5 Additional Measures for Prevention of False Locking, 65.
11.6 False Lock Prevention Using DC Offset, 72 -- 12 Notes on Sweep Methods 73 -- 12.1 Sweep Waveform Superimposed Directly on VCO Input, 73 -- 12.2 Maximum Sweep Rate (Acceleration), 74 -- 12.3 False Lock due to High-Order Filtering, 77 -- 12.4 Sweep Waveform Applied Directly to PLL Loop Integrator, 79 -- 12.5 Self-Sweeping PLL, 79 -- 13 Nonsweep Acquisition Methods 85 -- 13.1 Delay Line Frequency Discriminator, 85 -- 13.2 The Fully Unbalanced Quadricorrelator, 87 -- 13.3 The Fully Balanced Quadricorrelator, 88 -- 13.4 The Multipulse Balanced Quadricorrelator, 89 -- 13.5 Conclusion Regarding Pulsed Frequency Detection, 91 -- 13.6 Quadricorrelator Linearity, 92 -- 13.7 Limiter Asymmetry due to DC Offset, 97 -- 13.8 Taylor Series Demonstrates Second-Order-Caused DC Offset, 100 -- 13.9 Third-Order Intermodulation Distortion and Taylor Series, 101 -- 14 AM Rejection in Frequency Detection Schemes 105 -- 14.1 AM Rejection with Limiter and Interferer, 105 -- 14.2 AM Rejection of the Balanced Limiter/Quadricorrelator Versus the Limiter/Discriminator in the Presence of a Single Spur, 106 -- 14.3 Impairment due to Filter Response Tilt (Asymmetry), 110 -- 14.4 Bandpass Filter Geometric and Arithmetic Symmetry, 114 -- 14.5 Comments on Degree of Scrutiny, 117 -- 15 Interfacing the Frequency Discriminator to the PLL 119 -- 15.1 Continuous Connection: Pros and Cons, 119 -- 15.2 Connection to PLL via a Dead Band, 120 -- 15.3 Switched Connection, 121 -- 16 Actual Frequency Discriminator Implementations 125 -- 16.1 Quadricorrelator, Low-Frequency Implementation, 125 -- 16.2 Frequency Ratio Calculating Circuit for Wide-Bandwidth Use, 128 -- 16.3 Dividing the Frequency and Resultant Implementation, 131 -- 16.4 Marriage of Both Frequency and Phaselock Loops, 135 -- 16.5 Comments on Spurs' Numerical Influence on the VCO, 141 -- 16.6 Frequency Compression, 143 -- 17 Clock Recovery Using a PLL 145 -- 17.1 PLL Only, 145 -- 17.2 PLL with Sideband Crystal Filter(s), 152 -- 17.3 PLL with Sideband Cavity Filter, 153. 17.4 The Hogge Phase Detector, 161 -- 17.5 Bang-Bang Phase Detectors, 162 -- 18 Frequency Synthesis Applications 165 -- 18.1 Direct Frequency Synthesis with Wadley Loop, 166 -- 18.2 Indirect Frequency Synthesis with PLLs, 173 -- 18.3 Simple Frequency Acquisition Improvement for a PLL, 175 -- 18.4 Hybrid Frequency Synthesis with DDS and PLL, 176 -- 18.5 Phase Noise Considerations, 181 -- 18.6 Pros and Cons of DDS-Augmented Synthesis, 185 -- 18.7 Multiple Loops, 185 -- 18.8 Reference Signal Considerations and Filtering, 186 -- 18.9 SNR of Various Phase Detectors, 187 -- 18.10 Phase Detector Dead Band (Dead Zone) and Remediation, 187 -- 18.11 Sideband Energy due to DC Offset Following Phase Detector, 191 -- 18.12 Brute Force PLL Frequency Acquisition via Speedup, 193 -- 18.13 Short-Term and Long-Term Settling, 193 -- 18.14 N-over-M Synthesis, 193 -- 19 Injection Pulling of Multiple VCO's as in a Serdes 195 -- 19.1 Allowable Coupling Between any Two VCOs Versus Q and BW, 195 -- 19.2 Topology Suggestion for Eliminating the Injection Pulling, 195 -- 20 Digital PLL Example 199 -- 21 Conclusion 203 -- References 205 -- Index 209. |
| Record Nr. | UNINA-9910830451403321 |
|
Talbot Daniel (Daniel B.)
|
||
| Hoboken, New Jersey : , : John Wiley & Sons, Inc., , [2012] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Frequency Acquisition Techniques for phase locked loops / / by Daniel B. Talbot
| Frequency Acquisition Techniques for phase locked loops / / by Daniel B. Talbot |
| Autore | Talbot Daniel (Daniel B.) |
| Pubbl/distr/stampa | Piscataway, NJ, : IEEE Press |
| Descrizione fisica | 1 online resource (238 p.) |
| Disciplina |
621.3815/486
621.382 |
| Soggetto topico |
Frequency synthesizers
Phase-locked loops |
| ISBN |
9786613905680
9781118383308 1118383303 9781283593236 1283593238 9781118383315 1118383311 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Preface xi -- 1 Introduction 1 -- 2 A Review of PLL Fundamentals 3 -- 2.1 What is a PLL?, 3 -- 2.2 Second-Order PLL, 7 -- 2.3 Second-Order PLL Type One, 7 -- 2.4 Second-Order PLL Type Two, 7 -- 2.5 Higher-Order PLL's, 8 -- 2.6 Disturbances, 8 -- 2.7 Frequency Steering and Capture, 9 -- 2.8 Effect of DC Offsets or Noise Prior to the Loop Filter, 10 -- 2.9 Injection-Locked Oscillations, 15 -- 3 Simulating the PLL Linear Operation Mode 17 -- 3.1 Linear Model, 17 -- 3.2 A Word About Damping, 19 -- 4 Sideband Suppression Filtering 21 -- 4.1 Reference Sidebands and VCO Pushing, 21 -- 4.2 Superiority of the Cauer (or Elliptical) Filter, 22 -- 5 Pros and Cons of Sampled Data Phase Detection 25 -- 5.1 What are the Forms of Sampled Data Phase Detectors?, 25 -- 5.2 A. Ramp and Sample Analog Phase Detector, 25 -- 5.3 B. The RF Sampling Phase Detector, 28 -- 5.4 C. Edge-Triggered S-R Flip-Flop, 29 -- 5.5 D. Edge-Triggered Flip-Flop Ensemble, 31 -- 5.6 E. Sample and Hold as a Phase Detector, 31 -- 6 Phase Compression 33 -- 7 Hard Limiting of a Signal Plus Noise 35 -- 8 Phase Noise and Other Spurious Interferers 39 -- 8.1 The Mechanism for Phase Noise in an Oscillator, 42 -- 8.2 Additive Noise in an FM Channel and the Bowtie, 42 -- 8.3 Importance of FM Theory to Frequency Acquisition, 45 -- 9 Impulse Modulation and Noise Aliasing 47 -- 9.1 Impulse Train Spectrum, 47 -- 9.2 Sampling Phase Detector Noise, 47 -- 9.3 Spur Aliasing, 50 -- 10 Time and Phase Jitter, Heterodyning, and Multiplication 53 -- 10.1 Heterodyning and Resulting Time Jitter, 53 -- 10.2 Frequency Multiplication and Angle Modulation Index, 54 -- 10.3 Frequency Multiplication's Role in Carrier Recovery, 54 -- 11 Carrier Recovery Applications and Acquisition 57 -- 11.1 Frequency Multiplier Carrier Recovery in General, 57 -- 11.2 The Simplest Form of Costas PLL, 59 -- 11.3 Higher Level Quadrature Demodulation Costas PLL, 61 -- 11.4 False Lock in BPSK Costas PLL, 62 -- 11.5 Additional Measures for Prevention of False Locking, 65.
11.6 False Lock Prevention Using DC Offset, 72 -- 12 Notes on Sweep Methods 73 -- 12.1 Sweep Waveform Superimposed Directly on VCO Input, 73 -- 12.2 Maximum Sweep Rate (Acceleration), 74 -- 12.3 False Lock due to High-Order Filtering, 77 -- 12.4 Sweep Waveform Applied Directly to PLL Loop Integrator, 79 -- 12.5 Self-Sweeping PLL, 79 -- 13 Nonsweep Acquisition Methods 85 -- 13.1 Delay Line Frequency Discriminator, 85 -- 13.2 The Fully Unbalanced Quadricorrelator, 87 -- 13.3 The Fully Balanced Quadricorrelator, 88 -- 13.4 The Multipulse Balanced Quadricorrelator, 89 -- 13.5 Conclusion Regarding Pulsed Frequency Detection, 91 -- 13.6 Quadricorrelator Linearity, 92 -- 13.7 Limiter Asymmetry due to DC Offset, 97 -- 13.8 Taylor Series Demonstrates Second-Order-Caused DC Offset, 100 -- 13.9 Third-Order Intermodulation Distortion and Taylor Series, 101 -- 14 AM Rejection in Frequency Detection Schemes 105 -- 14.1 AM Rejection with Limiter and Interferer, 105 -- 14.2 AM Rejection of the Balanced Limiter/Quadricorrelator Versus the Limiter/Discriminator in the Presence of a Single Spur, 106 -- 14.3 Impairment due to Filter Response Tilt (Asymmetry), 110 -- 14.4 Bandpass Filter Geometric and Arithmetic Symmetry, 114 -- 14.5 Comments on Degree of Scrutiny, 117 -- 15 Interfacing the Frequency Discriminator to the PLL 119 -- 15.1 Continuous Connection: Pros and Cons, 119 -- 15.2 Connection to PLL via a Dead Band, 120 -- 15.3 Switched Connection, 121 -- 16 Actual Frequency Discriminator Implementations 125 -- 16.1 Quadricorrelator, Low-Frequency Implementation, 125 -- 16.2 Frequency Ratio Calculating Circuit for Wide-Bandwidth Use, 128 -- 16.3 Dividing the Frequency and Resultant Implementation, 131 -- 16.4 Marriage of Both Frequency and Phaselock Loops, 135 -- 16.5 Comments on Spurs' Numerical Influence on the VCO, 141 -- 16.6 Frequency Compression, 143 -- 17 Clock Recovery Using a PLL 145 -- 17.1 PLL Only, 145 -- 17.2 PLL with Sideband Crystal Filter(s), 152 -- 17.3 PLL with Sideband Cavity Filter, 153. 17.4 The Hogge Phase Detector, 161 -- 17.5 Bang-Bang Phase Detectors, 162 -- 18 Frequency Synthesis Applications 165 -- 18.1 Direct Frequency Synthesis with Wadley Loop, 166 -- 18.2 Indirect Frequency Synthesis with PLLs, 173 -- 18.3 Simple Frequency Acquisition Improvement for a PLL, 175 -- 18.4 Hybrid Frequency Synthesis with DDS and PLL, 176 -- 18.5 Phase Noise Considerations, 181 -- 18.6 Pros and Cons of DDS-Augmented Synthesis, 185 -- 18.7 Multiple Loops, 185 -- 18.8 Reference Signal Considerations and Filtering, 186 -- 18.9 SNR of Various Phase Detectors, 187 -- 18.10 Phase Detector Dead Band (Dead Zone) and Remediation, 187 -- 18.11 Sideband Energy due to DC Offset Following Phase Detector, 191 -- 18.12 Brute Force PLL Frequency Acquisition via Speedup, 193 -- 18.13 Short-Term and Long-Term Settling, 193 -- 18.14 N-over-M Synthesis, 193 -- 19 Injection Pulling of Multiple VCO's as in a Serdes 195 -- 19.1 Allowable Coupling Between any Two VCOs Versus Q and BW, 195 -- 19.2 Topology Suggestion for Eliminating the Injection Pulling, 195 -- 20 Digital PLL Example 199 -- 21 Conclusion 203 -- References 205 -- Index 209. |
| Record Nr. | UNINA-9911019576103321 |
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Talbot Daniel (Daniel B.)
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| Piscataway, NJ, : IEEE Press | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Low-voltage CMOS RF frequency synthesizers / / Howard Cam Luong and Gerry Chi Tak Leung [[electronic resource]]
| Low-voltage CMOS RF frequency synthesizers / / Howard Cam Luong and Gerry Chi Tak Leung [[electronic resource]] |
| Autore | Luong Howard C (Howard Cam) |
| Pubbl/distr/stampa | Cambridge : , : Cambridge University Press, , 2004 |
| Descrizione fisica | 1 online resource (xvii, 180 pages) : digital, PDF file(s) |
| Disciplina | 621.3815/486 |
| Soggetto topico |
Frequency synthesizers - Design and construction
Metal oxide semiconductors, Complementary - Design and construction |
| ISBN |
1-107-15045-0
1-280-54060-5 9786610540600 0-511-21493-6 0-511-21672-6 0-511-21135-X 0-511-31546-5 0-511-54114-7 0-511-21312-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | ; 1. Introduction -- ; 2. Synthesizer fundamentals -- ; 3. Design of building blocks -- ; 4. Low-voltage design considerations and techniques -- ; 5. Behavioral simulation -- ; 6. A 2 V 900 MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers -- ; 7. A 1.5 V 900 MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications -- ; 8. A 1 V 5.2 GHz fully integrated CMOS synthesizer for WLAN IEEE 802.11a. |
| Record Nr. | UNINA-9910457721703321 |
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Luong Howard C (Howard Cam)
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| Cambridge : , : Cambridge University Press, , 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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