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10th anniversary compendium of papers from Asian Test Symposium : proceedings : 1992-2001
| 10th anniversary compendium of papers from Asian Test Symposium : proceedings : 1992-2001 |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2001 |
| Disciplina | 621.3815/48 |
| Soggetto topico |
Electronic digital computers - Testing - Circuits
Electronic circuits - Testing Fault-tolerant computing Electrical & Computer Engineering Engineering & Applied Sciences Electrical Engineering |
| ISBN | 0-7695-1233-X |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | ATS 2001 compendium |
| Record Nr. | UNISA-996217253003316 |
| [Place of publication not identified], : IEEE Computer Society, 2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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2005 IEEE International Test Conference (ITC) : 8-10 November, 2005, Austin, TX
| 2005 IEEE International Test Conference (ITC) : 8-10 November, 2005, Austin, TX |
| Pubbl/distr/stampa | [Place of publication not identified], : Institute of Electrical and Electronics Engineers, 2005 |
| Disciplina | 621.3815/48 |
| Soggetto topico |
Integrated circuits - Testing
Semiconductors - Testing Electronics Electrical Engineering Electrical & Computer Engineering Engineering & Applied Sciences |
| ISBN | 1-5090-9767-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996204068103316 |
| [Place of publication not identified], : Institute of Electrical and Electronics Engineers, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2005 IEEE International Test Conference (ITC) : 8-10 November, 2005, Austin, TX
| 2005 IEEE International Test Conference (ITC) : 8-10 November, 2005, Austin, TX |
| Pubbl/distr/stampa | [Place of publication not identified], : Institute of Electrical and Electronics Engineers, 2005 |
| Disciplina | 621.3815/48 |
| Soggetto topico |
Integrated circuits - Testing
Semiconductors - Testing Electronics Electrical Engineering Electrical & Computer Engineering Engineering & Applied Sciences |
| ISBN |
9781509097678
1509097678 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910146829703321 |
| [Place of publication not identified], : Institute of Electrical and Electronics Engineers, 2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2006 IEEE International Test Conference : Santa Clara, CA : 22-27 October 2006
| 2006 IEEE International Test Conference : Santa Clara, CA : 22-27 October 2006 |
| Pubbl/distr/stampa | IEEE |
| Disciplina | 621.3815/48 |
| Soggetto topico |
Integrated circuits - Testing
Electronic digital computers - Circuits - Testing Telecommunication Radio frequency |
| ISBN | 1-5090-9088-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
Autonomic Computing
2006 IEEE International Test Conference |
| Record Nr. | UNISA-996281106603316 |
| IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2006 IEEE International Test Conference : Santa Clara, CA : 22-27 October 2006
| 2006 IEEE International Test Conference : Santa Clara, CA : 22-27 October 2006 |
| Pubbl/distr/stampa | IEEE |
| Disciplina | 621.3815/48 |
| Soggetto topico |
Integrated circuits - Testing
Electronic digital computers - Circuits - Testing Telecommunication Radio frequency |
| ISBN |
9781509090884
1509090886 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
Autonomic Computing
2006 IEEE International Test Conference |
| Record Nr. | UNINA-9910142706203321 |
| IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Comprehensive functional verification : the complete industry cycle [[electronic resource] /] / Bruce Wile, John C. Goss, Wolfgang Roesner
| Comprehensive functional verification : the complete industry cycle [[electronic resource] /] / Bruce Wile, John C. Goss, Wolfgang Roesner |
| Autore | Wile Bruce |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Morgan Kaufmann, c2005 |
| Descrizione fisica | 1 online resource (702 p.) |
| Disciplina | 621.3815/48 |
| Altri autori (Persone) |
GossJohn C
RoesnerW (Wolfgang) |
| Collana | Systems on Silicon |
| Soggetto topico |
Circuits integrats - Verificació
Integrated circuits - Verification Computer engineering |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-00839-7
9786611008390 1-4237-2233-7 9780080476643 0-08-047664-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Cover; Author Bios; FOREWORD; Table of contents; PREFACE; ACKNOWLEDGEMENTS; PART I: INTRODUCTION TO VERIFICATION; PART II: SIMULATION-BASED VERIFICATION; PART III: FORMAL VERIFICATION; PART IV: COMPREHENSIVE VERIFICATION; PART V: CASE STUDIES; VERIFICATION GLOSSARY; REFERENCES; SUBJECT INDEX |
| Record Nr. | UNINA-9910458499603321 |
Wile Bruce
|
||
| Amsterdam ; ; Boston, : Elsevier/Morgan Kaufmann, c2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Comprehensive functional verification : the complete industry cycle [[electronic resource] /] / Bruce Wile, John C. Goss, Wolfgang Roesner
| Comprehensive functional verification : the complete industry cycle [[electronic resource] /] / Bruce Wile, John C. Goss, Wolfgang Roesner |
| Autore | Wile Bruce |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Elsevier/Morgan Kaufmann, c2005 |
| Descrizione fisica | 1 online resource (702 p.) |
| Disciplina | 621.3815/48 |
| Altri autori (Persone) |
GossJohn C
RoesnerW (Wolfgang) |
| Collana | Systems on Silicon |
| Soggetto topico |
Circuits integrats - Verificació
Integrated circuits - Verification Computer engineering |
| ISBN |
1-281-00839-7
9786611008390 1-4237-2233-7 9780080476643 0-08-047664-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Cover; Author Bios; FOREWORD; Table of contents; PREFACE; ACKNOWLEDGEMENTS; PART I: INTRODUCTION TO VERIFICATION; PART II: SIMULATION-BASED VERIFICATION; PART III: FORMAL VERIFICATION; PART IV: COMPREHENSIVE VERIFICATION; PART V: CASE STUDIES; VERIFICATION GLOSSARY; REFERENCES; SUBJECT INDEX |
| Record Nr. | UNINA-9910784566503321 |
|
Wile Bruce
|
||
| Amsterdam ; ; Boston, : Elsevier/Morgan Kaufmann, c2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Digital logic testing and simulation / / Alexander Miczo
| Digital logic testing and simulation / / Alexander Miczo |
| Autore | Miczo Alexander |
| Edizione | [2nd ed.] |
| Pubbl/distr/stampa | Hoboken, NJ, : Wiley-Interscience, c2003 |
| Descrizione fisica | 1 online resource (697 p.) |
| Disciplina | 621.3815/48 |
| Soggetto topico | Digital electronics - Testing |
| ISBN |
9786610366101
9781280366109 1280366109 9780470357125 0470357126 9780471457770 0471457779 9780471457787 0471457787 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
DIGITAL LOGIC TESTING AND SIMULATION; CONTENTS; Preface; 1 Introduction; 1.1 Introduction; 1.2 Quality; 1.3 The Test; 1.4 The Design Process; 1.5 Design Automation; 1.6 Estimating Yield; 1.7 Measuring Test Effectiveness; 1.8 The Economics of Test; 1.9 Case Studies; 1.9.1 The Effectiveness of Fault Simulation; 1.9.2 Evaluating Test Decisions; 1.10 Summary; Problems; References; 2 Simulation; 2.1 Introduction; 2.2 Background; 2.3 The Simulation Hierarchy; 2.4 The Logic Symbols; 2.5 Sequential Circuit Behavior; 2.6 The Compiled Simulator; 2.6.1 Ternary Simulation
2.6.2 Sequential Circuit Simulation2.6.3 Timing Considerations; 2.6.4 Hazards; 2.6.5 Hazard Detection; 2.7 Event-Driven Simulation; 2.7.1 Zero-Delay Simulation; 2.7.2 Unit-Delay Simulation; 2.7.3 Nominal-Delay Simulation; 2.8 Multiple-Valued Simulation; 2.9 Implementing the Nominal-Delay Simulator; 2.9.1 The Scheduler; 2.9.2 The Descriptor Cell; 2.9.3 Evaluation Techniques; 2.9.4 Race Detection in Nominal-Delay Simulation; 2.9.5 Min-Max Timing; 2.10 Switch-Level Simulation; 2.11 Binary Decision Diagrams; 2.11.1 Introduction; 2.11.2 The Reduce Operation; 2.11.3 The Apply Operation 2.12 Cycle Simulation2.13 Timing Verification; 2.13.1 Path Enumeration; 2.13.2 Block-Oriented Analysis; 2.14 Summary; Problems; References; 3 Fault Simulation; 3.1 Introduction; 3.2 Approaches to Testing; 3.3 Analysis of a Faulted Circuit; 3.3.1 Analysis at the Component Level; 3.3.2 Gate-Level Symbols; 3.3.3 Analysis at the Gate Level; 3.4 The Stuck-At Fault Model; 3.4.1 The AND Gate Fault Model; 3.4.2 The OR Gate Fault Model; 3.4.3 The Inverter Fault Model; 3.4.4 The Tri-State Fault Model; 3.4.5 Fault Equivalence and Dominance; 3.5 The Fault Simulator: An Overview 3.6 Parallel Fault Processing3.6.1 Parallel Fault Simulation; 3.6.2 Performance Enhancements; 3.6.3 Parallel Pattern Single Fault Propagation; 3.7 Concurrent Fault Simulation; 3.7.1 An Example of Concurrent Simulation; 3.7.2 The Concurrent Fault Simulation Algorithm; 3.7.3 Concurrent Fault Simulation: Further Considerations; 3.8 Delay Fault Simulation; 3.9 Differential Fault Simulation; 3.10 Deductive Fault Simulation; 3.11 Statistical Fault Analysis; 3.12 Fault Simulation Performance; 3.13 Summary; Problems; References; 4 Automatic Test Pattern Generation; 4.1 Introduction 4.2 The Sensitized Path4.2.1 The Sensitized Path: An Example; 4.2.2 Analysis of the Sensitized Path Method; 4.3 The D-Algorithm; 4.3.1 The D-Algorithm: An Analysis; 4.3.2 The Primitive D-Cubes of Failure; 4.3.3 Propagation D-Cubes; 4.3.4 Justification and Implication; 4.3.5 The D-Intersection; 4.4 Testdetect; 4.5 The Subscripted D-Algorithm; 4.6 PODEM; 4.7 FAN; 4.8 Socrates; 4.9 The Critical Path; 4.10 Critical Path Tracing; 4.11 Boolean Differences; 4.12 Boolean Satisfiability; 4.13 Using BDDs for ATPG; 4.13.1 The BDD XOR Operation; 4.13.2 Faulting the BDD Graph; 4.14 Summary; Problems References |
| Record Nr. | UNINA-9911019685803321 |
|
Miczo Alexander
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| Hoboken, NJ, : Wiley-Interscience, c2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Eleventh IEEE European Test Symposium : ETS 2006 : proceedings : 21-24 May, 2006, [Hilton Hotel] Southampton, United Kingdom
| Eleventh IEEE European Test Symposium : ETS 2006 : proceedings : 21-24 May, 2006, [Hilton Hotel] Southampton, United Kingdom |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society Press, 2006 |
| Disciplina | 621.3815/48 |
| Soggetto topico |
Integrated circuits - Testing
Electrical Engineering Electrical & Computer Engineering Engineering & Applied Sciences |
| ISBN | 1-5090-9624-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996197572703316 |
| [Place of publication not identified], : IEEE Computer Society Press, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Eleventh IEEE European Test Symposium : ETS 2006 : proceedings : 21-24 May, 2006, [Hilton Hotel] Southampton, United Kingdom
| Eleventh IEEE European Test Symposium : ETS 2006 : proceedings : 21-24 May, 2006, [Hilton Hotel] Southampton, United Kingdom |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society Press, 2006 |
| Disciplina | 621.3815/48 |
| Soggetto topico |
Integrated circuits - Testing
Electrical Engineering Electrical & Computer Engineering Engineering & Applied Sciences |
| ISBN |
9781509096244
1509096248 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910145618803321 |
| [Place of publication not identified], : IEEE Computer Society Press, 2006 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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