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Advanced Nanoscale MOSFET Architectures : Current Trends and Future Perspectives
Advanced Nanoscale MOSFET Architectures : Current Trends and Future Perspectives
Autore Biswas Kalyan
Edizione [1st ed.]
Pubbl/distr/stampa Newark : , : John Wiley & Sons, Incorporated, , 2024
Descrizione fisica 1 online resource (339 pages)
Disciplina 621.3815/284
Altri autori (Persone) SarkarAngsuman
Soggetto topico Metal oxide semiconductor field-effect transistors
Nanotechnology
ISBN 9781394188956
1394188951
9781394188970
1394188978
9781394188987
1394188986
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Cover -- Title Page -- Copyright -- Contents -- About the Editors -- List of Contributors -- Preface -- Acknowledgments -- Chapter 1 Emerging MOSFET Technologies -- 1.1 Introduction: Transistor Action -- 1.2 MOSFET Scaling -- 1.3 Challenges in Scaling the MOSFET -- 1.4 Emerging MOSFET Architectures -- 1.4.1 Tunnel FET -- 1.4.2 Nanowire FET -- 1.4.3 Nanosheet FET -- 1.4.4 Negative Capacitance FET -- 1.4.5 Graphene FET -- 1.4.6 III-V Material‐based MOSFETS -- 1.4.7 HEMT -- 1.4.8 Strain Engineered MOSFETs -- 1.5 Organization of this Book -- References -- Chapter 2 MOSFET: Device Physics and Operation -- 2.1 Introduction to MOSFET -- 2.2 Advantages of MOSFET -- 2.3 Applications of MOSFETs -- 2.4 Types of MOSFETs -- 2.4.1 P‐Channel and N‐Channel MOSFET -- 2.4.2 MOSFET Working Operation -- 2.5 Band Diagram of MOSFET -- 2.5.1 Accumulation Layer -- 2.5.2 Depletion Layer -- 2.5.3 Inversion Layer -- 2.6 MOSFET Regions of Operation -- 2.6.1 N‐Channel Depletion MOSFET -- 2.6.2 P‐Channel depletion MOSFET -- 2.6.3 Operating Regions of P‐Channel Depletion MOSFET -- 2.6.4 Enhancement MOSFET -- 2.6.5 N‐Channel Enhancement MOSFET -- 2.6.6 P‐Channel Enhancement MOSFET -- 2.7 Scaling of MOSFET -- 2.7.1 Types of Scaling -- 2.8 Short‐channel Effects -- 2.8.1 Drain‐induced Barrier Lowering -- 2.8.2 Gate‐induced Drain Leakage -- 2.9 Body Bias Effect -- 2.9.1 Salient Feature of Body Bias -- 2.9.2 Significance of Body Bias -- 2.9.3 Body Bias Verification -- 2.10 Advancement of MOSFET Structures -- References -- Chapter 3 High‐κ Dielectrics in Next Generation VLSI/Mixed Signal Circuits -- 3.1 Introduction to Gate Dielectrics -- 3.2 High‐κ Dielectrics in Metal-Oxide-Semiconductor Capacitors -- 3.3 High‐κ Dielectrics in Metal Insulator Metal (MIM) Capacitors -- 3.3.1 High‐κ Dielectrics for Mixed Signal Circuits.
3.3.2 High‐κ Dielectrics as Stacks for Resistive Random Access Memories -- 3.4 MOSFETs Scaling and the Need of High‐κ -- 3.5 High‐κ Dielectrics in Next Generation Transistors -- 3.5.1 Planar-Nano Scale Field Effect Transistor -- 3.5.2 Silicon on Insulator -- 3.5.3 FIN Field Effect Transistor -- 3.5.4 Tunnel Field Effect Transistor -- 3.5.5 Negative Capacitance Field Effect Transistor -- References -- Chapter 4 Consequential Effects of Trap Charges on Dielectric Defects for MU‐G FET -- 4.1 Introduction -- 4.2 TID Effects Overview -- 4.3 Application Area of Device for TID Effect Analysis -- 4.4 Near the Earth: Trapped Radiation -- 4.5 Ionizing Radiation Effect in Silicon Dioxide (SiO2) -- 4.6 TID Effects in CMOS -- 4.7 TID Effects in Bipolar Devices -- 4.8 Understanding and Modeling a‐SiO2 Physics -- 4.9 Hydrogen (H2) Reaction with Trapped Charges at Insulator -- 4.10 Pre‐Existing Trap Density and their Respective Location -- 4.11 Use of High‐K Dielectric in MU‐G FET -- 4.12 Properties of Trap in the High‐K with Interfacial Layer -- 4.13 Trap Extraction Techniques -- 4.13.1 Capacitance Inversion Technique (CIT) -- 4.13.2 Charge Pumping Technique (CPT) -- 4.14 Conclusion -- References -- Chapter 5 Strain Engineering for Highly Scaled MOSFETs -- 5.1 Introduction -- 5.2 Simulation Approach -- 5.2.1 Strain Mapping -- 5.2.2 Mechanical Strain Modeling -- 5.2.3 Piezoresistivity Effect -- 5.2.4 Strain Induced Carrier Mobility -- 5.3 Case Study -- 5.3.1 Stress/Strain Engineering in Bulk‐Si FinFETs -- 5.3.1.1 Performance Analysis of Bulk‐Si FinFET -- 5.3.1.2 Effects of Fin Geometry Variations -- 5.3.2 Nanosheet -- 5.3.2.1 Impact of Mechanical Stress -- 5.3.2.2 Strained Engineering with Embedded Source/Drain Stressor -- 5.3.3 Extremely Thin SOI MOSFETs -- 5.4 Conclusions -- References.
Chapter 6 TCAD Analysis of Linearity Performance on Modified Ferroelectric Layer in FET Device with Spacer -- 6.1 Introduction -- 6.2 Simulation and Structure of Device -- 6.3 Results and Analysis -- 6.4 Conclusion -- Acknowledgment -- References -- Chapter 7 Electrically Doped Nano Devices: A First Principle Paradigm -- 7.1 Introduction -- 7.2 Electrical Doping -- 7.3 First Principle -- 7.3.1 DFT -- 7.3.2 NEGF -- 7.4 Molecular Simulation -- 7.5 Conclusion -- References -- Chapter 8 Tunnel FET: Principles and Operations -- 8.1 Introduction to Quantum Mechanics and Principles of Tunneling -- 8.2 Tunnel Field‐Effect Transistor -- 8.3 Challenges of Tunnel Field‐Effect Transistor -- 8.3.1 Low On‐state Current -- 8.3.2 Drain‐Induced Barrier Thinning Effect -- 8.3.3 Ambipolarity -- 8.3.4 Trap‐Assisted Tunneling -- 8.4 Techniques for Improving Electrical Performance of Tunnel Field‐Effect Transistor -- 8.4.1 Doping Engineering -- 8.4.2 Material Engineering -- 8.4.3 Geometry and Structure Engineering -- 8.5 Conclusion -- References -- Chapter 9 GaN Devices for Optoelectronics Applications -- 9.1 Introduction -- 9.2 Properties of GaN‐Based Material -- 9.2.1 Bandgap of GaN -- 9.2.2 Critical Electric Field of GaN -- 9.2.3 ON‐resistance of GaN -- 9.2.4 Two‐dimensional Electron Gas Formation at AlGaN/GaN Interface -- 9.3 GaN LEDs -- 9.3.1 Different Colors LEDs -- 9.3.2 μ‐LEDs -- 9.3.3 Micro‐LEDs with GaN‐based N‐doped Quantum Barriers -- 9.3.4 Blue Light Emission in GaN‐based LEDs -- 9.3.5 Characteristics -- 9.4 GaN Lasers -- 9.4.1 Blue Laser Diodes -- 9.5 GaN HEMTs for Optoelectronics -- 9.6 GaN Sensors -- References -- Chapter 10 First Principles Theoretical Design on Graphene‐Based Field‐Effect Transistors -- 10.1 Introduction -- 10.2 Graphene -- 10.2.1 Electronic Structure -- 10.2.2 Scanning Tunneling Microscopy -- 10.2.3 Electronic Transport.
10.3 Graphene/h‐BN Hybrid Structure -- 10.3.1 Atomic Structure -- 10.3.2 Structure and Energetics -- 10.3.3 Electronic Structure -- 10.3.4 Scanning Tunneling Microscopy -- 10.4 Conclusions -- Acknowledgments -- References -- Chapter 11 Performance Analysis of Nanosheet Transistors for Analog ICs -- 11.1 Introduction -- 11.2 Evolution of Nanosheet Transistors -- 11.2.1 Short‐Channel Effects and Their Mitigation -- 11.2.2 The FinFET Technology -- 11.2.3 Advent of Nanosheet Transistors -- 11.3 TCAD Modeling of Nanosheet Transistor -- 11.4 Transistor's Analog Performance Parameters -- 11.4.1 Transconductance -- 11.4.2 Output Conductance -- 11.4.3 Intrinsic Gain -- 11.4.4 Transconductance Efficiency -- 11.4.5 Discharge Time -- 11.4.6 Small Signal Capacitances and AC Model -- 11.4.7 Transit Frequency -- 11.5 Challenges and Perspectives of Modern Analog Design -- References -- Chapter 12 Low‐Power Analog Amplifier Design using MOS Transistor in the Weak Inversion Mode -- 12.1 Introduction -- 12.2 Review of the Theory of Weak Inversion Mode Operation of MOS Transistor -- 12.2.1 Drain Current Model in the Weak Inversion Mode -- 12.2.2 Concept of Inversion Coefficient -- 12.2.3 Parameter Extraction -- 12.2.3.1 Technology Current Constant Io -- 12.2.3.2 Sub‐threshold Swing Factor η -- 12.2.4 Small Signal Parameters in Weak Inversion Region -- 12.3 Design Steps for Transistor Sizing Using the IC -- 12.4 Design Examples -- 12.4.1 Design of a Common Source Amplifier -- 12.4.2 Single‐Ended Operational Transconductance Amplifier -- 12.4.2.1 Implementation and Simulation Result -- 12.5 Summary -- References -- Chapter 13 Ultra‐conductive Junctionless Tunnel Field‐effect Transistor‐based Biosensor with Negative Capacitance -- 13.1 Introduction -- 13.2 Importance of SS and ION/IOFF in Biosensing -- 13.3 Importance of Dopingless Source and Drain in High Conductivity.
13.4 Relation of Negative Capacitance with Non‐hysteresis and Effect on Biosensing -- 13.5 Variation of Source Material on Biosensing -- 13.6 Importance of Dual Gate and Ferroelectricity on Biosensing -- 13.7 Effect of Dual Material Gate on Biosensing -- References -- Chapter 14 Conclusion and Future Perspectives -- 14.1 Applications -- 14.1.1 Opportunities in Big Data -- 14.1.2 Fight Against Environment Change -- 14.1.3 Creation of Graphene -- 14.1.4 Nano Systems -- 14.1.5 Nanosensors -- 14.2 Some Recent Developments -- 14.3 Future Perspectives -- 14.4 Conclusion -- References -- Index -- EULA.
Record Nr. UNINA-9911020043303321
Biswas Kalyan  
Newark : , : John Wiley & Sons, Incorporated, , 2024
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Charge-based MOS transistor modeling : the EKV model for low-power and RF IC design / / Christian C. Enz, Eric A. Vittoz
Charge-based MOS transistor modeling : the EKV model for low-power and RF IC design / / Christian C. Enz, Eric A. Vittoz
Autore Enz Christian
Pubbl/distr/stampa Chichester, England ; ; Hoboken, NJ, : John Wiley, c2006
Descrizione fisica 1 online resource (329 p.)
Disciplina 621.3815/284
Altri autori (Persone) VittozEric A. <1938->
Soggetto topico Metal oxide semiconductors - Mathematical models
Metal oxide semiconductor field-effect transistors - Mathematical models
ISBN 9786610649938
9781280649936
1280649933
9780470855461
0470855460
9780470855454
0470855452
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Charge-based MOS Transistor Modeling; Contents; Foreword; Preface; List of Symbols; 1 Introduction; 1.1 The Importance of Device Modeling for IC Design; 1.2 A Short History of the EKV MOS Transistor Model; 1.3 The Book Structure; Part I The Basic Long-Channel Intrinsic Charge-Based Model; 2 Definitions; 2.1 The N-channel Transistor Structure; 2.2 Definition of Charges, Current, Potential, and Electric Fields; 2.3 Transistor Symbol and P-Channel Transistor; 3 The Basic Charge Model; 3.1 Poisson's Equation and Gradual Channel Approximation; 3.2 Surface Potential as a Function of Gate Voltage
3.3 Gate Capacitance3.4 Charge Sheet Approximation; 3.5 Density of Mobile Inverted Charge; 3.5.1 Mobile Charge as a Function of Gate Voltage and Surface Potential; 3.5.2 Mobile Charge as a Function of Channel Voltage and Surface Potential; 3.6 Charge-Potential Linearization; 3.6.1 Linearization of Qi (s); 3.6.2 Linearized Bulk Depletion Charge Qb; 3.6.3 Strong Inversion Approximation; 3.6.4 Evaluation of the Slope Factor; 3.6.5 Compact Model Parameters; 4 Static Drain Current; 4.1 Drain Current Expression; 4.2 Forward and Reverse Current Components; 4.3 Modes of Operation
4.4 Model of Drain Current Based on Charge Linearization4.4.1 Expression Valid for All Levels of Inversion; 4.4.2 Compact Model Parameters; 4.4.3 Inversion Coefficient; 4.4.4 Approximation of the Drain Current in Strong Inversion; 4.4.5 Approximation of the Drain Current in Weak Inversion; 4.4.6 Alternative Continuous Models; 4.5 Fundamental Property: Validity and Application; 4.5.1 Generalization of Drain Current Expression; 4.5.2 Domain of Validity; 4.5.3 Causes of Degradation; 4.5.4 Concept of Pseudo-Resistor; 4.6 Channel Length Modulation; 4.6.1 Effective Channel Length
4.6.2 Weak Inversion4.6.3 Strong Inversion; 4.6.4 Geometrical Effects; 5 The Small-Signal Model; 5.1 The Static Small-Signal Model; 5.1.1 Transconductances; 5.1.2 Residual Output Conductance in Saturation; 5.1.3 Equivalent Circuit; 5.1.4 The Normalized Transconductance to Drain Current Ratio; 5.2 A General NQS Small-Signal Model; 5.3 The QS Dynamic Small-Signal Model; 5.3.1 Intrinsic Capacitances; 5.3.2 Transcapacitances; 5.3.3 Complete QS Circuit; 5.3.4 Domains of Validity of the Different Models; 6 The Noise Model; 6.1 Noise Calculation Methods; 6.1.1 General Expression
6.1.2 Long-Channel Simplification6.2 Low-Frequency Channel Thermal Noise; 6.2.1 Drain Current Thermal Noise PSD; 6.2.2 Thermal Noise Excess Factor Definitions; 6.2.3 Circuit Examples; 6.3 Flicker Noise; 6.3.1 Carrier Number Fluctuations (Mc Worther Model); 6.3.2 Mobility Fluctuations (Hooge Model); 6.3.3 Additional Contributions Due to the Source and Drain Access Resistances; 6.3.4 Total 1/f Noise at the Drain; 6.3.5 Scaling Properties; 6.4 Appendices; Appendix: The Nyquist and Bode Theorems; Appendix: General Noise Expression; 7 Temperature Effects and Matching; 7.1 Introduction
7.2 Temperature Effects
Record Nr. UNINA-9911020157903321
Enz Christian  
Chichester, England ; ; Hoboken, NJ, : John Wiley, c2006
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
FeFET Devices, Trends, Technology and Applications
FeFET Devices, Trends, Technology and Applications
Autore Raj Balwinder
Edizione [1st ed.]
Pubbl/distr/stampa Newark : , : John Wiley & Sons, Incorporated, , 2025
Descrizione fisica 1 online resource (353 pages)
Disciplina 621.3815/284
Altri autori (Persone) RahiShiromani Balmukund
YadavNandakishor
Collana Semiconductor devices and their applications
Soggetto topico Field-effect transistors
Ferroelectric devices
ISBN 9781394287307
1394287305
9781394287284
1394287283
9781394287291
1394287291
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9911020036703321
Raj Balwinder  
Newark : , : John Wiley & Sons, Incorporated, , 2025
Materiale a stampa
Lo trovi qui: Univ. Federico II
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GaN Power Devices for Efficient Power Conversion
GaN Power Devices for Efficient Power Conversion
Autore Lidow Alex
Edizione [4th ed.]
Pubbl/distr/stampa Newark : , : John Wiley & Sons, Incorporated, , 2024
Descrizione fisica 1 online resource (499 pages)
Disciplina 621.3815/284
Altri autori (Persone) de RooijMichael
GlaserJohn (Electrical engineer)
PozoAlejandro
ZhangShengke
PalmaMarco
ReuschDavid
StrydomJohan
Soggetto topico Field-effect transistors
Power transistors
Gallium nitride
ISBN 9781394286973
139428697X
9781394286966
1394286961
9781394286980
1394286988
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNINA-9911019229803321
Lidow Alex  
Newark : , : John Wiley & Sons, Incorporated, , 2024
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
GaN transistors for efficient power conversion / / Alex Lidow [and three others]
GaN transistors for efficient power conversion / / Alex Lidow [and three others]
Autore Lidow Alex
Edizione [Second edition.]
Pubbl/distr/stampa Chichester, England : , : Wiley, , 2015
Descrizione fisica 1 online resource (269 pages)
Disciplina 621.3815/284
Collana THEi Wiley ebooks.
Soggetto topico Field-effect transistors
Gallium nitride
ISBN 1-118-84479-3
1-118-84478-5
1-118-84477-7
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto GaN Transistors for Efficient Power Conversion; Contents; Foreword; Acknowledgments; 1 GaN Technology Overview; 1.1 Silicon Power MOSFETs 1976-2010; 1.2 The GaN Journey Begins; 1.3 Why Gallium Nitride?; 1.3.1 Band Gap (Eg); 1.3.2 Critical Field (Ecrit); 1.3.3 On-Resistance (RDS(on)); 1.3.4 The Two-Dimensional Electron Gas; 1.4 The Basic GaN Transistor Structure; 1.4.1 Recessed Gate Enhancement-Mode Structure; 1.4.2 Implanted Gate Enhancement-Mode Structure; 1.4.3 pGaN Gate Enhancement-Mode Structure; 1.4.4 Cascode Hybrid Enhancement-Mode Structure; 1.4.5 Reverse Conduction in HEMT Transistors
1.5 Building a GaN Transistor 1.5.1 Substrate Material Selection; 1.5.2 Growing the Heteroepitaxy; 1.5.3 Processing the Wafer; 1.5.4 Making Electrical Connection to the Outside World; 1.6 Summary; References; 2 GaN Transistor Electrical Characteristics; 2.1 Introduction; 2.2 Key Device Parameters; 2.2.1 Breakdown Voltage (BVDSS) and Leakage Current (IDSS); 2.2.2 On-Resistance (RDS(on)); 2.2.3 Threshold Voltage (VGS(th) or Vth); 2.3 Capacitance and Charge; 2.4 Reverse Conduction; 2.5 Thermal Resistance; 2.6 Transient Thermal Impedance; 2.7 Summary; References; 3 Driving GaN Transistors
3.1 Introduction 3.2 Gate Drive Voltage; 3.3 Bootstrapping and Floating Supplies; 3.4 dv/dt Immunity; 3.5 di/dt Immunity; 3.6 Ground Bounce; 3.7 Common Mode Current; 3.8 Gate Driver Edge Rate; 3.9 Driving Cascode GaN Devices; 3.10 Summary; References; 4 Layout Considerations for GaN Transistor Circuits; 4.1 Introduction; 4.2 Minimizing Parasitic Inductance; 4.3 Conventional Power Loop Designs; 4.4 Optimizing the Power Loop; 4.5 Paralleling GaN Transistors; 4.5.1 Paralleling GaN Transistors for a Single Switch; 4.5.2 Paralleling GaN Transistors for Half-Bridge Applications; 4.6 Summary
References 5 Modeling and Measurement of GaN Transistors; 5.1 Introduction; 5.2 Electrical Modeling; 5.2.1 Basic Modeling; 5.2.2 Limitations of Basic Modeling; 5.2.3 Limitations of Circuit Modeling; 5.3 Thermal Modeling; 5.3.1 Improving Thermal Performance; 5.3.2 Modeling of Multiple Die; 5.3.3 Modeling of Complex Systems; 5.4 Measuring GaN Transistor Performance; 5.4.1 Voltage Measurement Requirements; 5.4.2 Current Measurement Requirement; 5.5 Summary; References; 6 Hard-Switching Topologies; 6.1 Introduction; 6.2 Hard-Switching Loss Analysis; 6.2.1 Switching Losses
6.2.2 Output Capacitance (COSS) Losses 6.2.3 Gate Charge (QG) Losses; 6.2.4 Reverse Conduction Losses (PSD); 6.2.5 Reverse Recovery (QRR) Losses; 6.2.6 Total Hard-Switching Losses; 6.2.7 Hard-Switching Figure of Merit; 6.3 External Factors Impacting Hard-Switching Losses; 6.3.1 Impact of Common-Source Inductance; 6.3.2 Impact of High Frequency Power-Loop Inductance on Device Losses; 6.4 Reducing Body Diode Conduction Losses in GaN Transistors; 6.5 Frequency Impact on Magnetics; 6.5.1 Transformers; 6.5.2 Inductors; 6.6 Buck Converter Example; 6.6.1 Output Capacitance Losses
6.6.2 Gate Losses (PG)
Record Nr. UNINA-9910792134303321
Lidow Alex  
Chichester, England : , : Wiley, , 2015
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
GaN transistors for efficient power conversion / / Alex Lidow [and three others]
GaN transistors for efficient power conversion / / Alex Lidow [and three others]
Autore Lidow Alex
Edizione [Second edition.]
Pubbl/distr/stampa Chichester, England : , : Wiley, , 2015
Descrizione fisica 1 online resource (269 pages)
Disciplina 621.3815/284
Collana THEi Wiley ebooks.
Soggetto topico Field-effect transistors
Gallium nitride
ISBN 1-118-84479-3
1-118-84478-5
1-118-84477-7
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto GaN Transistors for Efficient Power Conversion; Contents; Foreword; Acknowledgments; 1 GaN Technology Overview; 1.1 Silicon Power MOSFETs 1976-2010; 1.2 The GaN Journey Begins; 1.3 Why Gallium Nitride?; 1.3.1 Band Gap (Eg); 1.3.2 Critical Field (Ecrit); 1.3.3 On-Resistance (RDS(on)); 1.3.4 The Two-Dimensional Electron Gas; 1.4 The Basic GaN Transistor Structure; 1.4.1 Recessed Gate Enhancement-Mode Structure; 1.4.2 Implanted Gate Enhancement-Mode Structure; 1.4.3 pGaN Gate Enhancement-Mode Structure; 1.4.4 Cascode Hybrid Enhancement-Mode Structure; 1.4.5 Reverse Conduction in HEMT Transistors
1.5 Building a GaN Transistor 1.5.1 Substrate Material Selection; 1.5.2 Growing the Heteroepitaxy; 1.5.3 Processing the Wafer; 1.5.4 Making Electrical Connection to the Outside World; 1.6 Summary; References; 2 GaN Transistor Electrical Characteristics; 2.1 Introduction; 2.2 Key Device Parameters; 2.2.1 Breakdown Voltage (BVDSS) and Leakage Current (IDSS); 2.2.2 On-Resistance (RDS(on)); 2.2.3 Threshold Voltage (VGS(th) or Vth); 2.3 Capacitance and Charge; 2.4 Reverse Conduction; 2.5 Thermal Resistance; 2.6 Transient Thermal Impedance; 2.7 Summary; References; 3 Driving GaN Transistors
3.1 Introduction 3.2 Gate Drive Voltage; 3.3 Bootstrapping and Floating Supplies; 3.4 dv/dt Immunity; 3.5 di/dt Immunity; 3.6 Ground Bounce; 3.7 Common Mode Current; 3.8 Gate Driver Edge Rate; 3.9 Driving Cascode GaN Devices; 3.10 Summary; References; 4 Layout Considerations for GaN Transistor Circuits; 4.1 Introduction; 4.2 Minimizing Parasitic Inductance; 4.3 Conventional Power Loop Designs; 4.4 Optimizing the Power Loop; 4.5 Paralleling GaN Transistors; 4.5.1 Paralleling GaN Transistors for a Single Switch; 4.5.2 Paralleling GaN Transistors for Half-Bridge Applications; 4.6 Summary
References 5 Modeling and Measurement of GaN Transistors; 5.1 Introduction; 5.2 Electrical Modeling; 5.2.1 Basic Modeling; 5.2.2 Limitations of Basic Modeling; 5.2.3 Limitations of Circuit Modeling; 5.3 Thermal Modeling; 5.3.1 Improving Thermal Performance; 5.3.2 Modeling of Multiple Die; 5.3.3 Modeling of Complex Systems; 5.4 Measuring GaN Transistor Performance; 5.4.1 Voltage Measurement Requirements; 5.4.2 Current Measurement Requirement; 5.5 Summary; References; 6 Hard-Switching Topologies; 6.1 Introduction; 6.2 Hard-Switching Loss Analysis; 6.2.1 Switching Losses
6.2.2 Output Capacitance (COSS) Losses 6.2.3 Gate Charge (QG) Losses; 6.2.4 Reverse Conduction Losses (PSD); 6.2.5 Reverse Recovery (QRR) Losses; 6.2.6 Total Hard-Switching Losses; 6.2.7 Hard-Switching Figure of Merit; 6.3 External Factors Impacting Hard-Switching Losses; 6.3.1 Impact of Common-Source Inductance; 6.3.2 Impact of High Frequency Power-Loop Inductance on Device Losses; 6.4 Reducing Body Diode Conduction Losses in GaN Transistors; 6.5 Frequency Impact on Magnetics; 6.5.1 Transformers; 6.5.2 Inductors; 6.6 Buck Converter Example; 6.6.1 Output Capacitance Losses
6.6.2 Gate Losses (PG)
Record Nr. UNINA-9910808289103321
Lidow Alex  
Chichester, England : , : Wiley, , 2015
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Junctionless Field-Effect Transistors : Design, Modeling, and Simulation / / Shubham Sahay, Mamidala Jagadesh Kumar
Junctionless Field-Effect Transistors : Design, Modeling, and Simulation / / Shubham Sahay, Mamidala Jagadesh Kumar
Autore Sahay Shubham
Pubbl/distr/stampa Hoboken, New Jersey : , : John Wiley & Sons Inc., , [2019]
Descrizione fisica 1 online resource
Disciplina 621.3815/284
Collana IEEE Press series on microelectronic systems
Soggetto topico Metal semiconductor field-effect transistors
ISBN 1-119-52352-4
1-119-52354-0
1-119-52351-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Preface xi -- 1 Introduction to Field-Effect Transistors 1 -- 1.1 Transistor Action 2 -- 1.2 Metal-Oxide-Semiconductor Field-Effect Transistors 4 -- 1.3 MOSFET Circuits: The Need for Complementary MOS 9 -- 1.4 The Need for CMOS Scaling 11 -- 1.5 Moore’s Law 13 -- 1.6 Koomey’s Law 13 -- 1.7 Challenges in Scaling the MOSFET 13 -- 1.8 Conclusion 23 -- References 23 -- 2 Emerging FET Architectures 27 -- 2.1 Tunnel FETs 28 -- 2.2 Impact Ionization MOSFET 34 -- 2.3 Bipolar I-MOS 39 -- 2.4 Negative Capacitance FETs 41 -- 2.5 Two-Dimensional FETs 46 -- 2.6 Nanowire FETs 49 -- 2.7 Nanotube FETs 51 -- 2.8 Conclusion 57 -- References 58 -- 3 Fundamentals of Junctionless Field-Effect Transistors 67 -- 3.1 Device Structure 69 -- 3.2 Operation 70 -- 3.3 Design Parameters 80 -- 3.4 Parameters that Affect the Performance 82 -- 3.5 Beyond Silicon JLFETS: Other Materials 100 -- 3.6 Challenges 103 -- 3.7 Conclusion 110 -- References 111 -- 4 Device Architectures to Mitigate Challenges in Junctionless Field-Effect Transistors 125 -- 4.1 Junctionless Accumulation-Mode Field-Effect Transistors 126 -- 4.2 Realizing Efficient Volume Depletion 129 -- 4.3 SOI JLFET with a High-𝜅 Box 131 -- 4.4 Bulk Planar JLFET 137 -- 4.5 JLFET with a Nonuniform Doping 140 -- 4.6 JLFET with a Step Doping Profile 144 -- 4.7 Multigate JLFET 149 -- 4.8 JLFET with a High-𝜅 Spacer 153 -- 4.9 JLFET with a Dual Material Gate 157 -- 4.10 Conclusion 162 -- References 162 -- 5 Gate-Induced Drain Leakage in Junctionless Field-Effect Transistors 173 -- 5.1 Hole Accumulation 174 -- 5.2 Parasitic BJT Action 176 -- 5.3 Impact of BTBT-Induced Parasitic BJT Action on Scaling 177 -- 5.4 Impact of Silicon Film Thickness on GIDL 179 -- 5.5 Impact of Doping on GIDL 187 -- 5.6 Impact of Spacer Design on GIDL 189 -- 5.7 Nature of GIDL in Different NWFET Configurations 190 -- 5.8 Device Architectures to Mitigate GIDL 199 -- 5.9 Conclusion 248 -- References 249 -- 6 Impact Ionization in Junctionless Field-Effect Transistors 255.
6.1 Impact Ionization 256 -- 6.2 Floating Body Effects in Silicon-on-Insulator MOSFETs 256 -- 6.3 Nature of Impact Ionization in JLFETs 260 -- 6.4 Zero Gate Oxide Thickness Coefficient 263 -- 6.5 Single Transistor Latch-Up in JLFETs 266 -- 6.6 Impact of Body Bias on Impact Ionization in JLFETs 267 -- 6.7 Subband Gap Impact Ionization in DGJLFETS with Asymmetric Operation 268 -- 6.8 Impact of Gate Misalignment on Impact Ionization in DGJLFETs 270 -- 6.9 Spacer Design Guideline from Impact Ionization Perspective 272 -- 6.10 Hysteresis and Snapback in JLFETs 273 -- 6.11 Impact of Heavy-Ion Irradiation on JLFETs 275 -- 6.12 Conclusions 276 -- References 276 -- 7 Junctionless Devices Without Any Chemical Doping 281 -- 7.1 Charge Plasma Doping 282 -- 7.2 Charge Plasma Based p-n Diode 283 -- 7.3 Junctionless I-MOS FET 288 -- 7.4 Junctionless Tunnel FETs 290 -- 7.5 JLTFET on a Highly Doped Silicon Film 294 -- 7.6 Bipolar Enhanced JLTFET 294 -- 7.7 Junctionless FETS Without Any Chemical Doping 297 -- 7.8 Challenges for CPJLFETs 302 -- 7.9 Electrostatic Doping Based FETs 312 -- 7.10 Conclusions 319 -- References 319 -- 8 Modeling Junctionless Field-Effect Transistors 327 -- 8.1 Introduction to FET Modeling 328 -- 8.2 Surface Potential Modeling of JLFETs 330 -- 8.3 Charge-Based Modeling Approach 351 -- 8.4 Drain Current Modeling Approach 355 -- 8.5 Modeling Short-Channel JLFETs 365 -- 8.6 Modeling Quantum Confinement 372 -- 8.7 Conclusion 379 -- References 379 -- 9 Simulation of JLFETS Using Sentaurus TCAD 385 -- 9.1 Introduction to TCAD 386 -- 9.2 Tool Flow 387 -- 9.3 Sample Input Deck for Long-Channel JLFETS 391 -- 9.4 Model Calibration 407 -- 9.5 Model Calibration for Short-Channel JLFETs 409 -- 9.6 Model Calibration for NWFETS 422 -- References 436 -- 10 Conclusion and Perspectives 439 -- 10.1 JLFETS As a Label-Free Biosensor 441 -- 10.2 JLFETS As Capacitorless DRAM 443 -- 10.3 Nanowire Junctionless NAND Flash Memory 444 -- 10.4 Junctionless Polysilicon TFTS with a Hybrid Channel 447.
10.5 JLFETS for 3D Integrated Circuits 449 -- 10.6 Summary 450 -- References 451 -- Index 457.
Record Nr. UNINA-9910554835903321
Sahay Shubham  
Hoboken, New Jersey : , : John Wiley & Sons Inc., , [2019]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Junctionless Field-Effect Transistors : Design, Modeling, and Simulation / / Shubham Sahay, Mamidala Jagadesh Kumar
Junctionless Field-Effect Transistors : Design, Modeling, and Simulation / / Shubham Sahay, Mamidala Jagadesh Kumar
Autore Sahay Shubham
Pubbl/distr/stampa Hoboken, New Jersey : , : John Wiley & Sons Inc., , [2019]
Descrizione fisica 1 online resource
Disciplina 621.3815/284
Collana IEEE Press series on microelectronic systems
Soggetto topico Metal semiconductor field-effect transistors
ISBN 1-119-52352-4
1-119-52354-0
1-119-52351-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Preface xi -- 1 Introduction to Field-Effect Transistors 1 -- 1.1 Transistor Action 2 -- 1.2 Metal-Oxide-Semiconductor Field-Effect Transistors 4 -- 1.3 MOSFET Circuits: The Need for Complementary MOS 9 -- 1.4 The Need for CMOS Scaling 11 -- 1.5 Moore’s Law 13 -- 1.6 Koomey’s Law 13 -- 1.7 Challenges in Scaling the MOSFET 13 -- 1.8 Conclusion 23 -- References 23 -- 2 Emerging FET Architectures 27 -- 2.1 Tunnel FETs 28 -- 2.2 Impact Ionization MOSFET 34 -- 2.3 Bipolar I-MOS 39 -- 2.4 Negative Capacitance FETs 41 -- 2.5 Two-Dimensional FETs 46 -- 2.6 Nanowire FETs 49 -- 2.7 Nanotube FETs 51 -- 2.8 Conclusion 57 -- References 58 -- 3 Fundamentals of Junctionless Field-Effect Transistors 67 -- 3.1 Device Structure 69 -- 3.2 Operation 70 -- 3.3 Design Parameters 80 -- 3.4 Parameters that Affect the Performance 82 -- 3.5 Beyond Silicon JLFETS: Other Materials 100 -- 3.6 Challenges 103 -- 3.7 Conclusion 110 -- References 111 -- 4 Device Architectures to Mitigate Challenges in Junctionless Field-Effect Transistors 125 -- 4.1 Junctionless Accumulation-Mode Field-Effect Transistors 126 -- 4.2 Realizing Efficient Volume Depletion 129 -- 4.3 SOI JLFET with a High-𝜅 Box 131 -- 4.4 Bulk Planar JLFET 137 -- 4.5 JLFET with a Nonuniform Doping 140 -- 4.6 JLFET with a Step Doping Profile 144 -- 4.7 Multigate JLFET 149 -- 4.8 JLFET with a High-𝜅 Spacer 153 -- 4.9 JLFET with a Dual Material Gate 157 -- 4.10 Conclusion 162 -- References 162 -- 5 Gate-Induced Drain Leakage in Junctionless Field-Effect Transistors 173 -- 5.1 Hole Accumulation 174 -- 5.2 Parasitic BJT Action 176 -- 5.3 Impact of BTBT-Induced Parasitic BJT Action on Scaling 177 -- 5.4 Impact of Silicon Film Thickness on GIDL 179 -- 5.5 Impact of Doping on GIDL 187 -- 5.6 Impact of Spacer Design on GIDL 189 -- 5.7 Nature of GIDL in Different NWFET Configurations 190 -- 5.8 Device Architectures to Mitigate GIDL 199 -- 5.9 Conclusion 248 -- References 249 -- 6 Impact Ionization in Junctionless Field-Effect Transistors 255.
6.1 Impact Ionization 256 -- 6.2 Floating Body Effects in Silicon-on-Insulator MOSFETs 256 -- 6.3 Nature of Impact Ionization in JLFETs 260 -- 6.4 Zero Gate Oxide Thickness Coefficient 263 -- 6.5 Single Transistor Latch-Up in JLFETs 266 -- 6.6 Impact of Body Bias on Impact Ionization in JLFETs 267 -- 6.7 Subband Gap Impact Ionization in DGJLFETS with Asymmetric Operation 268 -- 6.8 Impact of Gate Misalignment on Impact Ionization in DGJLFETs 270 -- 6.9 Spacer Design Guideline from Impact Ionization Perspective 272 -- 6.10 Hysteresis and Snapback in JLFETs 273 -- 6.11 Impact of Heavy-Ion Irradiation on JLFETs 275 -- 6.12 Conclusions 276 -- References 276 -- 7 Junctionless Devices Without Any Chemical Doping 281 -- 7.1 Charge Plasma Doping 282 -- 7.2 Charge Plasma Based p-n Diode 283 -- 7.3 Junctionless I-MOS FET 288 -- 7.4 Junctionless Tunnel FETs 290 -- 7.5 JLTFET on a Highly Doped Silicon Film 294 -- 7.6 Bipolar Enhanced JLTFET 294 -- 7.7 Junctionless FETS Without Any Chemical Doping 297 -- 7.8 Challenges for CPJLFETs 302 -- 7.9 Electrostatic Doping Based FETs 312 -- 7.10 Conclusions 319 -- References 319 -- 8 Modeling Junctionless Field-Effect Transistors 327 -- 8.1 Introduction to FET Modeling 328 -- 8.2 Surface Potential Modeling of JLFETs 330 -- 8.3 Charge-Based Modeling Approach 351 -- 8.4 Drain Current Modeling Approach 355 -- 8.5 Modeling Short-Channel JLFETs 365 -- 8.6 Modeling Quantum Confinement 372 -- 8.7 Conclusion 379 -- References 379 -- 9 Simulation of JLFETS Using Sentaurus TCAD 385 -- 9.1 Introduction to TCAD 386 -- 9.2 Tool Flow 387 -- 9.3 Sample Input Deck for Long-Channel JLFETS 391 -- 9.4 Model Calibration 407 -- 9.5 Model Calibration for Short-Channel JLFETs 409 -- 9.6 Model Calibration for NWFETS 422 -- References 436 -- 10 Conclusion and Perspectives 439 -- 10.1 JLFETS As a Label-Free Biosensor 441 -- 10.2 JLFETS As Capacitorless DRAM 443 -- 10.3 Nanowire Junctionless NAND Flash Memory 444 -- 10.4 Junctionless Polysilicon TFTS with a Hybrid Channel 447.
10.5 JLFETS for 3D Integrated Circuits 449 -- 10.6 Summary 450 -- References 451 -- Index 457.
Record Nr. UNINA-9910830003503321
Sahay Shubham  
Hoboken, New Jersey : , : John Wiley & Sons Inc., , [2019]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
MOS devices for low-voltage and low-energy applications / / Yasuhisa Omura, Abhijit Mallik, and Naoto Matsuo
MOS devices for low-voltage and low-energy applications / / Yasuhisa Omura, Abhijit Mallik, and Naoto Matsuo
Autore Omura Y (Yasuhisa)
Pubbl/distr/stampa Singapore ; ; Hoboken, NJ : , : John Wiley & Sons, , 2017
Descrizione fisica 1 online resource (758 pages) : illustrations, tables, graphs
Disciplina 621.3815/284
Soggetto topico Metal oxide semiconductors
Metal oxide semiconductor field-effect transistors
Low voltage integrated circuits
Low voltage systems - Industrial applications
ISBN 1-5231-1527-0
1-119-10738-5
1-119-10736-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Preface XV -- Acknowledgments Xvi -- Part I Introduction To Low Voltage And Low Energy Devices 1 -- 1 Why Are Low Voltage And Low Energy Devices Desired? 3 -- References 4 -- 2 History Of Low Voltage And Low Power Devices 5 -- 2.1 Scaling Scheme And Low Voltage Requests 5 -- 2.2 Silicon On Insulator Devices And Real History 8 -- References 10 -- 3 Performance Prospects Of Subthreshold Logic Circuits 12 -- 3.1 Introduction 12 -- 3.2 Subthreshold Logic And Its Issues 12 -- 3.3 Is Subthreshold Logic The Best Solution? 13 -- References 13 -- Part Ii Summary Of Physics Of Modern Semiconductor Devices 15 -- 4 Overview 17 -- References 18 -- 5 Bulk Mosfet 19 -- 5.1 Theoretical Basis Of Bulk Mosfet Operation 19 -- 5.2 Subthreshold Characteristics: "Boff State" 19 -- 5.2.1 Fundamental Theory 19 -- 5.2.2 Influence Of Btbt Current 23 -- 5.2.3 Points To Be Remarked 24 -- 5.3 Post Threshold Characteristics: "Bon State" 24 -- 5.3.1 Fundamental Theory 24 -- 5.3.2 Self Heating Effects 26 -- 5.3.3 Parasitic Bipolar Effects 27 -- 5.4 Comprehensive Summary Of Short Channel Effects 27 -- References 28 -- 6 Soi Mosfet 29 -- 6.1 Partially Depleted Silicon On Insulator Metal Oxide Semiconductor Field Effect Transistors 29 -- 6.2 Fully Depleted (Fd) Soi Mosfet 30 -- 6.2.1 Subthreshold Characteristics 30 -- 6.2.2 Post Threshold Characteristics 36 -- 6.2.3 Comprehensive Summary Of Short Channel Effects 41 -- 6.3 Accumulation Mode (Am) Soi Mosfet 41 -- 6.3.1 Aspects Of Device Structure 41 -- 6.3.2 Subthreshold Characteristics 42 -- 6.3.3 Drain Current Component (I) Body Current (Id,Body) 43 -- 6.3.4 Drain Current Component (Ii) Surface Accumulation -- Layer Current (Id,Acc) 45 -- 6.3.5 Optional Discussions On The Accumulation Mode Soi Mosfet 45 -- 6.4 Finfet And Triple Gate Fet 46 -- 6.4.1 Introduction 46 -- 6.4.2 Device Structures And Simulations 46 -- 6.4.3 Results And Discussion 47 -- 6.4.4 Summary 49 -- 6.5 Gate All Around Mosfet 50 -- References 51 -- 7 Tunnel Field Effect Transistors (Tfets) 53.
7.1 Overview 53 -- 7.2 Model of Double‐Gate Lateral Tunnel FET and Device Performance Perspective 53 -- 7.2.1 Introduction 53 -- 7.2.2 Device Modeling 54 -- 7.2.3 Numerical Calculation Results and Discussion 61 -- 7.2.4 Summary 65 -- 7.3 Model of Vertical Tunnel FET and Aspects of its Characteristics 65 -- 7.3.1 Introduction 65 -- 7.3.2 Device Structure and Model Concept 65 -- 7.3.3 Comparing Model Results with TCAD Results 69 -- 7.3.4 Consideration of the Impact of Tunnel Dimensionality on Drivability 72 -- 7.3.5 Summary 75 -- 7.4 Appendix Integration of Eqs. (7.14) / (7.16) 76 -- References 78 -- Part III POTENTIAL OF CONVENTIONAL BULK MOSFETs 81 -- 8 Performance Evaluation of Analog Circuits with Deep Submicrometer MOSFETs in the Subthreshold Regime of Operation 83 -- 8.1 Introduction 83 -- 8.2 Subthreshold Operation and Device Simulation 84 -- 8.3 Model Description 85 -- 8.4 Results 86 -- 8.5 Summary 90 -- References 90 -- 9 Impact of Halo Doping on the Subthreshold Performance of Deep‐Submicrometer CMOS Devices and Circuits for Ultralow Power Analog/Mixed‐Signal Applications 91 -- 9.1 Introduction 91 -- 9.2 Device Structures and Simulation 92 -- 9.3 Subthreshold Operation 93 -- 9.4 Device Optimization for Subthreshold Analog Operation 95 -- 9.5 Subthreshold Analog Circuit Performance 98 -- 9.6 CMOS Amplifiers with Large Geometry Devices 105 -- 9.7 Summary 106 -- References 107 -- 10 Study of the Subthreshold Performance and the Effect of Channel Engineering on Deep Submicron Single‐Stage CMOS Amplifiers 108 -- 10.1 Introduction 108 -- 10.2 Circuit Description 108 -- 10.3 Device Structure and Simulation 110 -- 10.4 Results and Discussion 110 -- 10.5 PTAT as a Temperature Sensor 116 -- 10.6 Summary 116 -- References 116 -- 11 Subthreshold Performance of Dual‐Material Gate CMOS Devices and Circuits for Ultralow Power Analog/Mixed‐Signal Applications 117 -- 11.1 Introduction 117 -- 11.2 Device Structure and Simulation 118 -- 11.3 Results and Discussion 120 -- 11.4 Summary 126.
References 127 -- 12 Performance Prospect of Low‐Power Bulk MOSFETs 128 -- Reference 129 -- Part IV POTENTIAL OF FULLY‐DEPLETED SOI MOSFETs 131 -- 13 Demand for High‐Performance SOI Devices 133 -- 14 Demonstration of 100 nm Gate SOI CMOS with a Thin Buried Oxide Layer and its Impact on Device Technology 134 -- 14.1 Introduction 134 -- 14.2 Device Design Concept for 100 nm Gate SOI CMOS 134 -- 14.3 Device Fabrication 136 -- 14.4 Performance of 100‐nm‐ and 85‐nm Gate Devices 137 -- 14.4.1 Threshold and Subthreshold Characteristics 137 -- 14.4.2 Drain Current (ID)‐Drain Voltage (VD) and ID‐Gate Voltage (VG) Characteristics of 100‐nm‐Gate MOSFET/SIMOX 138 -- 14.4.3 ID / VD and ID / VG Characteristics of 85‐nm‐Gate MOSFET/SIMOX 142 -- 14.4.4 Switching Performance 142 -- 14.5 Discussion 142 -- 14.5.1 Threshold Voltage Balance in Ultrathin CMOS/SOI Devices 142 -- 14.6 Summary 144 -- References 145 -- 15 Discussion on Design Feasibility and Prospect of High‐Performance Sub‐50 nm Channel Single‐Gate SOI MOSFET Based on the ITRS Roadmap 147 -- 15.1 Introduction 147 -- 15.2 Device Structure and Simulations 148 -- 15.3 Proposed Model for Minimum Channel Length 149 -- 15.3.1 Minimum Channel Length Model Constructed using Extract A 149 -- 15.3.2 Minimum Channel Length Model Constructed using Extract B 150 -- 15.4 Performance Prospects of Scaled SOI MOSFETs 152 -- 15.4.1 Dynamic Operation Characteristics of Scaled SG SOI MOSFETs 152 -- 15.4.2 Tradeoff and Optimization of Standby Power Consumption and Dynamic Operation 157 -- 15.5 Summary 162 -- References 162 -- 16 Performance Prospects of Fully Depleted SOI MOSFET‐Based Diodes Applied to Schenkel Circuits for RF‐ID Chips 164 -- 16.1 Introduction 164 -- 16.2 Remaining Issues with Conventional Schenkel Circuits and an Advanced Proposal 165 -- 16.3 Simulation‐Based Consideration of RF Performance of SOI‐QD 172 -- 16.4 Summary 176 -- 16.5 Appendix: A Simulation Model for Minority Carrier Lifetime 177 -- 16.6 Appendix: Design Guideline for SOI‐QDs 177.
References 178 -- 17 The Potential and the Drawbacks of Underlap Single‐Gate Ultrathin SOI MOSFET 180 -- 17.1 Introduction 180 -- 17.2 Simulations 181 -- 17.3 Results and Discussion 183 -- 17.3.1 DC Characteristics and Switching Performance: Device A 183 -- 17.3.2 RF Analog Characteristics: Device A 184 -- 17.3.3 Impact of High‐κ Gate Dielectric on Performance of USU SOI MOSFET Devices: Devices B and C 185 -- 17.3.4 Impact of Simulation Model on Simulation Results 189 -- 17.4 Summary 192 -- References 192 -- 18 Practical Source/Drain Diffusion and Body Doping Layouts for High‐Performance and Low‐Energy Triple‐Gate SOI MOSFETs 194 -- 18.1 Introduction 194 -- 18.2 Device Structures and Simulation Model 195 -- 18.3 Results and Discussion 196 -- 18.3.1 Impact of S/D‐Underlying Layer on ION, IOFF, and Subthreshold Swing 196 -- 18.3.2 Tradeoff of Short‐Channel Effects and Drivability 196 -- 18.4 Summary 201 -- References 201 -- 19 Gate Field Engineering and Source/Drain Diffusion Engineering for High‐Performance Si Wire Gate‐All‐Around MOSFET and Low‐Power Strategy in a Sub‐30 nm‐Channel Regime 203 -- 19.1 Introduction 203 -- 19.2 Device Structures Assumed and Physical Parameters 204 -- 19.3 Simulation Results and Discussion 206 -- 19.3.1 Performance of Sub‐30 nm‐Channel Devices and Aspects of Device Characteristics 206 -- 19.3.2 Impact of Cross‐Section of Si Wire on Short‐Channel Effects and Drivability 212 -- 19.3.3 Minimizing Standby Power Consumption of GAA SOI MOSFET 216 -- 19.3.4 Prospective Switching Speed Performance of GAA SOI MOSFET 217 -- 19.3.5 Parasitic Resistance Issues of GAA Wire MOSFETs 218 -- 19.3.6 Proposal for Possible GAA Wire MOSFET Structure 220 -- 19.4 Summary 221 -- 19.5 Appendix: Brief Description of Physical Models in Simulations 221 -- References 225 -- 20 Impact of Local High‐κ Insulator on Drivability and Standby Power of Gate‐All‐Around SOI MOSFET 228 -- 20.1 Introduction 228 -- 20.2 Device Structure and Simulations 229 -- 20.3 Results and Discussion 230.
20.3.1 Device Characteristics of GAA Devices with Graded‐Profile Junctions 230 -- 20.3.2 Device Characteristics of GAA Devices with Abrupt Junctions 235 -- 20.3.3 Behaviors of Drivability and Off‐Current 237 -- 20.3.4 Dynamic Performance of Devices with Graded‐Profile Junctions 239 -- 20.4 Summary 239 -- References 240 -- Part V POTENTIAL OF PARTIALLY DEPLETED SOI MOSFETs 241 -- 21 Proposal for Cross‐Current Tetrode (XCT) SOI MOSFETs: A 60 dB Single‐Stage CMOS Amplifier Using High‐Gain Cross‐Current Tetrode MOSFET/SIMOX 243 -- 21.1 Introduction 243 -- 21.2 Device Fabrication 244 -- 21.3 Device Characteristics 245 -- 21.4 Performance of CMOS Amplifier 247 -- 21.5 Summary 249 -- References 249 -- 22 Device Model of the XCT‐SOI MOSFET and Scaling Scheme 250 -- 22.1 Introduction 250 -- 22.2 Device Structure and Assumptions for Modeling 251 -- 22.2.1 Device Structure and Features of XCT Device 251 -- 22.2.2 Basic Assumptions for Device Modeling 253 -- 22.2.3 Derivation of Model Equations 254 -- 22.3 Results and Discussion 258 -- 22.3.1 Measured Characteristics of XCT Devices 258 -- 22.4 Design Guidelines 261 -- 22.4.1 Drivability Control 261 -- 22.4.2 Scaling Issues 262 -- 22.4.3 Potentiality of Low‐Energy Operation of XCT CMOS Devices 265 -- 22.5 Summary 267 -- 22.6 Appendix: Calculation of MOSFET Channel Current 267 -- 22.7 Appendix: Basic Condition for Drivability Control 271 -- References 271 -- 23 Low‐Power Multivoltage Reference Circuit Using XCT‐SOI MOSFET 274 -- 23.1 Introduction 274 -- 23.2 Device Structure and Assumptions for Simulations 274 -- 23.2.1 Device Structure and Features 274 -- 23.2.2 Assumptions for Simulations 277 -- 23.3 Proposal for Voltage Reference Circuits and Simulation Results 278 -- 23.3.1 Two‐Reference Voltage Circuit 278 -- 23.3.2 Three‐Reference Voltage Circuit 283 -- 23.4 Summary 283 -- References 284 -- 24 Low‐Energy Operation Mechanisms for XCT‐SOI CMOS Devices: Prospects for a Sub‐20 nm Regime 285 -- 24.1 Introduction 285 -- 24.2 Device Structure and Assumptions for Modeling 286.
24.3 Circuit Simulation Results of SOI CMOS and XCT‐SOI CMOS 288 -- 24.4 Further Scaling Potential of XCT‐SOI MOSFET 291 -- 24.5 Performance Expected from the Scaled XCT‐SOI MOSFET 292 -- 24.6 Summary 296 -- References 296 -- Part VI QUANTUM EFFECTS AND APPLICATIONS / 1 297 -- 25 Overview 299 -- References 299 -- 26 Si Resonant Tunneling MOS Transistor 301 -- 26.1 Introduction 301 -- 26.2 Configuration of SRTMOST 302 -- 26.2.1 Structure and Electrostatic Potential 302 -- 26.2.2 Operation Principle and Subthreshold Characteristics 304 -- 26.3 Device Performance of SRTMOST 307 -- 26.3.1 Transistor Characteristics of SRTMOST 307 -- 26.3.2 Logic Circuit Using SRTMOST 310 -- 26.4 Summary 312 -- References 312 -- 27 Tunneling Dielectric Thin‐Film Transistor 314 -- 27.1 Introduction 314 -- 27.2 Fundamental Device Structure 315 -- 27.3 Experiment 315 -- 27.3.1 Experimental Method 315 -- 27.3.2 Calculation Method 317 -- 27.4 Results and Discussion 320 -- 27.4.1 Evaluation of SiNx Film 320 -- 27.4.2 Characteristics of the TDTFT 320 -- 27.4.3 TFT Performance at Low Temperatures 324 -- 27.4.4 TFT Performance at High Temperatures 324 -- 27.4.5 Suppression of the Hump Effect by the TDTFT 330 -- 27.5 Summary 336 -- References 336 -- 28 Proposal for a Tunnel‐Barrier Junction (TBJ) MOSFET 339 -- 28.1 Introduction 339 -- 28.2 Device Structure and Model 339 -- 28.3 Calculation Results 340 -- 28.4 Summary 343 -- References 343 -- 29 Performance Prediction of SOI Tunneling‐Barrier‐Junction MOSFET 344 -- 29.1 Introduction 344 -- 29.2 Simulation Model 345 -- 29.3 Simulation Results and Discussion 349 -- 29.3.1 Fundamental Properties of TBJ MOSFET 349 -- 29.3.2 Optimization of Device Parameters and Materials 349 -- 29.4 Summary 357 -- References 357 -- 30 Physics‐Based Model for TBJ‐MOSFETs and High‐Frequency Performance Prospects 358 -- 30.1 Introduction 358 -- 30.2 Device Structure and Device Model for Simulations 359 -- 30.3 Simulation Results and Discussion 360 -- 30.3.1 Current Drivability 361.
30.3.2 Threshold Voltage Issue 362 -- 30.3.3 Subthreshold Characteristics 363 -- 30.3.4 Radio‐Frequency Characteristics 363 -- 30.4 Summary 365 -- References 365 -- 31 Low‐Power High‐Temperature‐Operation‐Tolerant (HTOT) SOI MOSFET 367 -- 31.1 Introduction 367 -- 31.2 Device Structure and Simulations 368 -- 31.3 Results and Discussion 371 -- 31.3.1 Room‐Temperature Characteristics 371 -- 31.3.2 High‐Temperature Characteristics 373 -- 31.4 Summary 377 -- References 379 -- Part VII QUANTUM EFFECTS AND APPLICATIONS / 2 381 -- 32 Overview of Tunnel Field‐Effect Transistor 383 -- References 385 -- 33 Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field‐Effect Transistor 386 -- 33.1 Introduction 386 -- 33.2 Device Structure and Simulation 387 -- 33.3 Results and Discussion 387 -- 33.3.1 Effects of Variation in the Spacer Dielectric Constant 387 -- 33.3.2 Effects of Variation in the Spacer Width 391 -- 33.3.3 Effects of Variation in the Source Doping Concentration 392 -- 33.3.4 Effects of a Gate‐Source Overlap 394 -- 33.3.5 Effects of a Gate‐Channel Underlap 394 -- 33.4 Summary 397 -- References 397 -- 34 The Impact of a Fringing Field on the Device Performance of a P‐Channel Tunnel Field‐Effect Transistor with a High‐κ Gate Dielectric 399 -- 34.1 Introduction 399 -- 34.2 Device Structure and Simulation 399 -- 34.3 Results and Discussion 400 -- 34.3.1 Effects of Variation in the Gate Dielectric Constant 400 -- 34.3.2 Effects of Variation in the Spacer Dielectric Constant 408 -- 34.4 Summary 410 -- References 410 -- 35 Impact of a Spacer‐Drain Overlap on the Characteristics of a Silicon Tunnel Field‐Effect Transistor Based on Vertical Tunneling 412 -- 35.1 Introduction 412 -- 35.2 Device Structure and Process Steps 413 -- 35.3 Simulation Setup 414 -- 35.4 Results and Discussion 416 -- 35.4.1 Impact of Variation in the Spacer‐Drain Overlap 416 -- 35.4.2 Influence of Drain on the Device Characteristics 424 -- 35.4.3 Impact of Scaling 426.
35.5 Summary 429 -- References 430 -- 36 Gate‐on‐Germanium Source Tunnel Field‐Effect Transistor Enabling Sub‐0.5‐V Operation 431 -- 36.1 Introduction 431 -- 36.2 Proposed Device Structure 431 -- 36.3 Simulation Setup 432 -- 36.4 Results and Discussion 434 -- 36.4.1 Device Characteristics 434 -- 36.4.2 Effects of Different Structural Parameters 435 -- 36.4.3 Optimization of Different Structural Parameters 436 -- 36.5 Summary 445 -- References 445 -- Part VIII PROSPECTS OF LOW‐ENERGY DEVICE TECHNOLOLGY AND APPLICATIONS 447 -- 37 Performance Comparison of Modern Devices 449 -- References 450 -- 38 Emerging Device Technology and the Future of MOSFET 452 -- 38.1 Studies to Realize High‐Performance MOSFETs based on Unconventional Materials 452 -- 38.2 Challenging Studies to Realize High‐Performance MOSFETs based on the Nonconventional Doctrine 453 -- References 454 -- 39 How Devices Are and Should Be Applied to Circuits 456 -- 39.1 Past Approach 456 -- 39.2 Latest Studies 456 -- References 457 -- 40 Prospects for Low‐Energy Device Technology and Applications 458 -- References 459 -- Bibliography 460 -- Index 463.
Record Nr. UNINA-9910157536603321
Omura Y (Yasuhisa)  
Singapore ; ; Hoboken, NJ : , : John Wiley & Sons, , 2017
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
MOS devices for low-voltage and low-energy applications / / Yasuhisa Omura, Abhijit Mallik, and Naoto Matsuo
MOS devices for low-voltage and low-energy applications / / Yasuhisa Omura, Abhijit Mallik, and Naoto Matsuo
Autore Omura Y (Yasuhisa)
Pubbl/distr/stampa Singapore ; ; Hoboken, NJ : , : John Wiley & Sons, , 2017
Descrizione fisica 1 online resource (758 pages) : illustrations, tables, graphs
Disciplina 621.3815/284
Soggetto topico Metal oxide semiconductors
Metal oxide semiconductor field-effect transistors
Low voltage integrated circuits
Low voltage systems - Industrial applications
ISBN 1-5231-1527-0
1-119-10738-5
1-119-10736-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Preface XV -- Acknowledgments Xvi -- Part I Introduction To Low Voltage And Low Energy Devices 1 -- 1 Why Are Low Voltage And Low Energy Devices Desired? 3 -- References 4 -- 2 History Of Low Voltage And Low Power Devices 5 -- 2.1 Scaling Scheme And Low Voltage Requests 5 -- 2.2 Silicon On Insulator Devices And Real History 8 -- References 10 -- 3 Performance Prospects Of Subthreshold Logic Circuits 12 -- 3.1 Introduction 12 -- 3.2 Subthreshold Logic And Its Issues 12 -- 3.3 Is Subthreshold Logic The Best Solution? 13 -- References 13 -- Part Ii Summary Of Physics Of Modern Semiconductor Devices 15 -- 4 Overview 17 -- References 18 -- 5 Bulk Mosfet 19 -- 5.1 Theoretical Basis Of Bulk Mosfet Operation 19 -- 5.2 Subthreshold Characteristics: "Boff State" 19 -- 5.2.1 Fundamental Theory 19 -- 5.2.2 Influence Of Btbt Current 23 -- 5.2.3 Points To Be Remarked 24 -- 5.3 Post Threshold Characteristics: "Bon State" 24 -- 5.3.1 Fundamental Theory 24 -- 5.3.2 Self Heating Effects 26 -- 5.3.3 Parasitic Bipolar Effects 27 -- 5.4 Comprehensive Summary Of Short Channel Effects 27 -- References 28 -- 6 Soi Mosfet 29 -- 6.1 Partially Depleted Silicon On Insulator Metal Oxide Semiconductor Field Effect Transistors 29 -- 6.2 Fully Depleted (Fd) Soi Mosfet 30 -- 6.2.1 Subthreshold Characteristics 30 -- 6.2.2 Post Threshold Characteristics 36 -- 6.2.3 Comprehensive Summary Of Short Channel Effects 41 -- 6.3 Accumulation Mode (Am) Soi Mosfet 41 -- 6.3.1 Aspects Of Device Structure 41 -- 6.3.2 Subthreshold Characteristics 42 -- 6.3.3 Drain Current Component (I) Body Current (Id,Body) 43 -- 6.3.4 Drain Current Component (Ii) Surface Accumulation -- Layer Current (Id,Acc) 45 -- 6.3.5 Optional Discussions On The Accumulation Mode Soi Mosfet 45 -- 6.4 Finfet And Triple Gate Fet 46 -- 6.4.1 Introduction 46 -- 6.4.2 Device Structures And Simulations 46 -- 6.4.3 Results And Discussion 47 -- 6.4.4 Summary 49 -- 6.5 Gate All Around Mosfet 50 -- References 51 -- 7 Tunnel Field Effect Transistors (Tfets) 53.
7.1 Overview 53 -- 7.2 Model of Double‐Gate Lateral Tunnel FET and Device Performance Perspective 53 -- 7.2.1 Introduction 53 -- 7.2.2 Device Modeling 54 -- 7.2.3 Numerical Calculation Results and Discussion 61 -- 7.2.4 Summary 65 -- 7.3 Model of Vertical Tunnel FET and Aspects of its Characteristics 65 -- 7.3.1 Introduction 65 -- 7.3.2 Device Structure and Model Concept 65 -- 7.3.3 Comparing Model Results with TCAD Results 69 -- 7.3.4 Consideration of the Impact of Tunnel Dimensionality on Drivability 72 -- 7.3.5 Summary 75 -- 7.4 Appendix Integration of Eqs. (7.14) / (7.16) 76 -- References 78 -- Part III POTENTIAL OF CONVENTIONAL BULK MOSFETs 81 -- 8 Performance Evaluation of Analog Circuits with Deep Submicrometer MOSFETs in the Subthreshold Regime of Operation 83 -- 8.1 Introduction 83 -- 8.2 Subthreshold Operation and Device Simulation 84 -- 8.3 Model Description 85 -- 8.4 Results 86 -- 8.5 Summary 90 -- References 90 -- 9 Impact of Halo Doping on the Subthreshold Performance of Deep‐Submicrometer CMOS Devices and Circuits for Ultralow Power Analog/Mixed‐Signal Applications 91 -- 9.1 Introduction 91 -- 9.2 Device Structures and Simulation 92 -- 9.3 Subthreshold Operation 93 -- 9.4 Device Optimization for Subthreshold Analog Operation 95 -- 9.5 Subthreshold Analog Circuit Performance 98 -- 9.6 CMOS Amplifiers with Large Geometry Devices 105 -- 9.7 Summary 106 -- References 107 -- 10 Study of the Subthreshold Performance and the Effect of Channel Engineering on Deep Submicron Single‐Stage CMOS Amplifiers 108 -- 10.1 Introduction 108 -- 10.2 Circuit Description 108 -- 10.3 Device Structure and Simulation 110 -- 10.4 Results and Discussion 110 -- 10.5 PTAT as a Temperature Sensor 116 -- 10.6 Summary 116 -- References 116 -- 11 Subthreshold Performance of Dual‐Material Gate CMOS Devices and Circuits for Ultralow Power Analog/Mixed‐Signal Applications 117 -- 11.1 Introduction 117 -- 11.2 Device Structure and Simulation 118 -- 11.3 Results and Discussion 120 -- 11.4 Summary 126.
References 127 -- 12 Performance Prospect of Low‐Power Bulk MOSFETs 128 -- Reference 129 -- Part IV POTENTIAL OF FULLY‐DEPLETED SOI MOSFETs 131 -- 13 Demand for High‐Performance SOI Devices 133 -- 14 Demonstration of 100 nm Gate SOI CMOS with a Thin Buried Oxide Layer and its Impact on Device Technology 134 -- 14.1 Introduction 134 -- 14.2 Device Design Concept for 100 nm Gate SOI CMOS 134 -- 14.3 Device Fabrication 136 -- 14.4 Performance of 100‐nm‐ and 85‐nm Gate Devices 137 -- 14.4.1 Threshold and Subthreshold Characteristics 137 -- 14.4.2 Drain Current (ID)‐Drain Voltage (VD) and ID‐Gate Voltage (VG) Characteristics of 100‐nm‐Gate MOSFET/SIMOX 138 -- 14.4.3 ID / VD and ID / VG Characteristics of 85‐nm‐Gate MOSFET/SIMOX 142 -- 14.4.4 Switching Performance 142 -- 14.5 Discussion 142 -- 14.5.1 Threshold Voltage Balance in Ultrathin CMOS/SOI Devices 142 -- 14.6 Summary 144 -- References 145 -- 15 Discussion on Design Feasibility and Prospect of High‐Performance Sub‐50 nm Channel Single‐Gate SOI MOSFET Based on the ITRS Roadmap 147 -- 15.1 Introduction 147 -- 15.2 Device Structure and Simulations 148 -- 15.3 Proposed Model for Minimum Channel Length 149 -- 15.3.1 Minimum Channel Length Model Constructed using Extract A 149 -- 15.3.2 Minimum Channel Length Model Constructed using Extract B 150 -- 15.4 Performance Prospects of Scaled SOI MOSFETs 152 -- 15.4.1 Dynamic Operation Characteristics of Scaled SG SOI MOSFETs 152 -- 15.4.2 Tradeoff and Optimization of Standby Power Consumption and Dynamic Operation 157 -- 15.5 Summary 162 -- References 162 -- 16 Performance Prospects of Fully Depleted SOI MOSFET‐Based Diodes Applied to Schenkel Circuits for RF‐ID Chips 164 -- 16.1 Introduction 164 -- 16.2 Remaining Issues with Conventional Schenkel Circuits and an Advanced Proposal 165 -- 16.3 Simulation‐Based Consideration of RF Performance of SOI‐QD 172 -- 16.4 Summary 176 -- 16.5 Appendix: A Simulation Model for Minority Carrier Lifetime 177 -- 16.6 Appendix: Design Guideline for SOI‐QDs 177.
References 178 -- 17 The Potential and the Drawbacks of Underlap Single‐Gate Ultrathin SOI MOSFET 180 -- 17.1 Introduction 180 -- 17.2 Simulations 181 -- 17.3 Results and Discussion 183 -- 17.3.1 DC Characteristics and Switching Performance: Device A 183 -- 17.3.2 RF Analog Characteristics: Device A 184 -- 17.3.3 Impact of High‐κ Gate Dielectric on Performance of USU SOI MOSFET Devices: Devices B and C 185 -- 17.3.4 Impact of Simulation Model on Simulation Results 189 -- 17.4 Summary 192 -- References 192 -- 18 Practical Source/Drain Diffusion and Body Doping Layouts for High‐Performance and Low‐Energy Triple‐Gate SOI MOSFETs 194 -- 18.1 Introduction 194 -- 18.2 Device Structures and Simulation Model 195 -- 18.3 Results and Discussion 196 -- 18.3.1 Impact of S/D‐Underlying Layer on ION, IOFF, and Subthreshold Swing 196 -- 18.3.2 Tradeoff of Short‐Channel Effects and Drivability 196 -- 18.4 Summary 201 -- References 201 -- 19 Gate Field Engineering and Source/Drain Diffusion Engineering for High‐Performance Si Wire Gate‐All‐Around MOSFET and Low‐Power Strategy in a Sub‐30 nm‐Channel Regime 203 -- 19.1 Introduction 203 -- 19.2 Device Structures Assumed and Physical Parameters 204 -- 19.3 Simulation Results and Discussion 206 -- 19.3.1 Performance of Sub‐30 nm‐Channel Devices and Aspects of Device Characteristics 206 -- 19.3.2 Impact of Cross‐Section of Si Wire on Short‐Channel Effects and Drivability 212 -- 19.3.3 Minimizing Standby Power Consumption of GAA SOI MOSFET 216 -- 19.3.4 Prospective Switching Speed Performance of GAA SOI MOSFET 217 -- 19.3.5 Parasitic Resistance Issues of GAA Wire MOSFETs 218 -- 19.3.6 Proposal for Possible GAA Wire MOSFET Structure 220 -- 19.4 Summary 221 -- 19.5 Appendix: Brief Description of Physical Models in Simulations 221 -- References 225 -- 20 Impact of Local High‐κ Insulator on Drivability and Standby Power of Gate‐All‐Around SOI MOSFET 228 -- 20.1 Introduction 228 -- 20.2 Device Structure and Simulations 229 -- 20.3 Results and Discussion 230.
20.3.1 Device Characteristics of GAA Devices with Graded‐Profile Junctions 230 -- 20.3.2 Device Characteristics of GAA Devices with Abrupt Junctions 235 -- 20.3.3 Behaviors of Drivability and Off‐Current 237 -- 20.3.4 Dynamic Performance of Devices with Graded‐Profile Junctions 239 -- 20.4 Summary 239 -- References 240 -- Part V POTENTIAL OF PARTIALLY DEPLETED SOI MOSFETs 241 -- 21 Proposal for Cross‐Current Tetrode (XCT) SOI MOSFETs: A 60 dB Single‐Stage CMOS Amplifier Using High‐Gain Cross‐Current Tetrode MOSFET/SIMOX 243 -- 21.1 Introduction 243 -- 21.2 Device Fabrication 244 -- 21.3 Device Characteristics 245 -- 21.4 Performance of CMOS Amplifier 247 -- 21.5 Summary 249 -- References 249 -- 22 Device Model of the XCT‐SOI MOSFET and Scaling Scheme 250 -- 22.1 Introduction 250 -- 22.2 Device Structure and Assumptions for Modeling 251 -- 22.2.1 Device Structure and Features of XCT Device 251 -- 22.2.2 Basic Assumptions for Device Modeling 253 -- 22.2.3 Derivation of Model Equations 254 -- 22.3 Results and Discussion 258 -- 22.3.1 Measured Characteristics of XCT Devices 258 -- 22.4 Design Guidelines 261 -- 22.4.1 Drivability Control 261 -- 22.4.2 Scaling Issues 262 -- 22.4.3 Potentiality of Low‐Energy Operation of XCT CMOS Devices 265 -- 22.5 Summary 267 -- 22.6 Appendix: Calculation of MOSFET Channel Current 267 -- 22.7 Appendix: Basic Condition for Drivability Control 271 -- References 271 -- 23 Low‐Power Multivoltage Reference Circuit Using XCT‐SOI MOSFET 274 -- 23.1 Introduction 274 -- 23.2 Device Structure and Assumptions for Simulations 274 -- 23.2.1 Device Structure and Features 274 -- 23.2.2 Assumptions for Simulations 277 -- 23.3 Proposal for Voltage Reference Circuits and Simulation Results 278 -- 23.3.1 Two‐Reference Voltage Circuit 278 -- 23.3.2 Three‐Reference Voltage Circuit 283 -- 23.4 Summary 283 -- References 284 -- 24 Low‐Energy Operation Mechanisms for XCT‐SOI CMOS Devices: Prospects for a Sub‐20 nm Regime 285 -- 24.1 Introduction 285 -- 24.2 Device Structure and Assumptions for Modeling 286.
24.3 Circuit Simulation Results of SOI CMOS and XCT‐SOI CMOS 288 -- 24.4 Further Scaling Potential of XCT‐SOI MOSFET 291 -- 24.5 Performance Expected from the Scaled XCT‐SOI MOSFET 292 -- 24.6 Summary 296 -- References 296 -- Part VI QUANTUM EFFECTS AND APPLICATIONS / 1 297 -- 25 Overview 299 -- References 299 -- 26 Si Resonant Tunneling MOS Transistor 301 -- 26.1 Introduction 301 -- 26.2 Configuration of SRTMOST 302 -- 26.2.1 Structure and Electrostatic Potential 302 -- 26.2.2 Operation Principle and Subthreshold Characteristics 304 -- 26.3 Device Performance of SRTMOST 307 -- 26.3.1 Transistor Characteristics of SRTMOST 307 -- 26.3.2 Logic Circuit Using SRTMOST 310 -- 26.4 Summary 312 -- References 312 -- 27 Tunneling Dielectric Thin‐Film Transistor 314 -- 27.1 Introduction 314 -- 27.2 Fundamental Device Structure 315 -- 27.3 Experiment 315 -- 27.3.1 Experimental Method 315 -- 27.3.2 Calculation Method 317 -- 27.4 Results and Discussion 320 -- 27.4.1 Evaluation of SiNx Film 320 -- 27.4.2 Characteristics of the TDTFT 320 -- 27.4.3 TFT Performance at Low Temperatures 324 -- 27.4.4 TFT Performance at High Temperatures 324 -- 27.4.5 Suppression of the Hump Effect by the TDTFT 330 -- 27.5 Summary 336 -- References 336 -- 28 Proposal for a Tunnel‐Barrier Junction (TBJ) MOSFET 339 -- 28.1 Introduction 339 -- 28.2 Device Structure and Model 339 -- 28.3 Calculation Results 340 -- 28.4 Summary 343 -- References 343 -- 29 Performance Prediction of SOI Tunneling‐Barrier‐Junction MOSFET 344 -- 29.1 Introduction 344 -- 29.2 Simulation Model 345 -- 29.3 Simulation Results and Discussion 349 -- 29.3.1 Fundamental Properties of TBJ MOSFET 349 -- 29.3.2 Optimization of Device Parameters and Materials 349 -- 29.4 Summary 357 -- References 357 -- 30 Physics‐Based Model for TBJ‐MOSFETs and High‐Frequency Performance Prospects 358 -- 30.1 Introduction 358 -- 30.2 Device Structure and Device Model for Simulations 359 -- 30.3 Simulation Results and Discussion 360 -- 30.3.1 Current Drivability 361.
30.3.2 Threshold Voltage Issue 362 -- 30.3.3 Subthreshold Characteristics 363 -- 30.3.4 Radio‐Frequency Characteristics 363 -- 30.4 Summary 365 -- References 365 -- 31 Low‐Power High‐Temperature‐Operation‐Tolerant (HTOT) SOI MOSFET 367 -- 31.1 Introduction 367 -- 31.2 Device Structure and Simulations 368 -- 31.3 Results and Discussion 371 -- 31.3.1 Room‐Temperature Characteristics 371 -- 31.3.2 High‐Temperature Characteristics 373 -- 31.4 Summary 377 -- References 379 -- Part VII QUANTUM EFFECTS AND APPLICATIONS / 2 381 -- 32 Overview of Tunnel Field‐Effect Transistor 383 -- References 385 -- 33 Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field‐Effect Transistor 386 -- 33.1 Introduction 386 -- 33.2 Device Structure and Simulation 387 -- 33.3 Results and Discussion 387 -- 33.3.1 Effects of Variation in the Spacer Dielectric Constant 387 -- 33.3.2 Effects of Variation in the Spacer Width 391 -- 33.3.3 Effects of Variation in the Source Doping Concentration 392 -- 33.3.4 Effects of a Gate‐Source Overlap 394 -- 33.3.5 Effects of a Gate‐Channel Underlap 394 -- 33.4 Summary 397 -- References 397 -- 34 The Impact of a Fringing Field on the Device Performance of a P‐Channel Tunnel Field‐Effect Transistor with a High‐κ Gate Dielectric 399 -- 34.1 Introduction 399 -- 34.2 Device Structure and Simulation 399 -- 34.3 Results and Discussion 400 -- 34.3.1 Effects of Variation in the Gate Dielectric Constant 400 -- 34.3.2 Effects of Variation in the Spacer Dielectric Constant 408 -- 34.4 Summary 410 -- References 410 -- 35 Impact of a Spacer‐Drain Overlap on the Characteristics of a Silicon Tunnel Field‐Effect Transistor Based on Vertical Tunneling 412 -- 35.1 Introduction 412 -- 35.2 Device Structure and Process Steps 413 -- 35.3 Simulation Setup 414 -- 35.4 Results and Discussion 416 -- 35.4.1 Impact of Variation in the Spacer‐Drain Overlap 416 -- 35.4.2 Influence of Drain on the Device Characteristics 424 -- 35.4.3 Impact of Scaling 426.
35.5 Summary 429 -- References 430 -- 36 Gate‐on‐Germanium Source Tunnel Field‐Effect Transistor Enabling Sub‐0.5‐V Operation 431 -- 36.1 Introduction 431 -- 36.2 Proposed Device Structure 431 -- 36.3 Simulation Setup 432 -- 36.4 Results and Discussion 434 -- 36.4.1 Device Characteristics 434 -- 36.4.2 Effects of Different Structural Parameters 435 -- 36.4.3 Optimization of Different Structural Parameters 436 -- 36.5 Summary 445 -- References 445 -- Part VIII PROSPECTS OF LOW‐ENERGY DEVICE TECHNOLOLGY AND APPLICATIONS 447 -- 37 Performance Comparison of Modern Devices 449 -- References 450 -- 38 Emerging Device Technology and the Future of MOSFET 452 -- 38.1 Studies to Realize High‐Performance MOSFETs based on Unconventional Materials 452 -- 38.2 Challenging Studies to Realize High‐Performance MOSFETs based on the Nonconventional Doctrine 453 -- References 454 -- 39 How Devices Are and Should Be Applied to Circuits 456 -- 39.1 Past Approach 456 -- 39.2 Latest Studies 456 -- References 457 -- 40 Prospects for Low‐Energy Device Technology and Applications 458 -- References 459 -- Bibliography 460 -- Index 463.
Record Nr. UNINA-9910830903103321
Omura Y (Yasuhisa)  
Singapore ; ; Hoboken, NJ : , : John Wiley & Sons, , 2017
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