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Analyzing the Logic of Sun Tzu in “The Art of War”, Using Mind Maps [[electronic resource] /] / by Peter van Emde Boas, Ghica van Emde Boas, Kaibo Xie, Bonan Zhao
| Analyzing the Logic of Sun Tzu in “The Art of War”, Using Mind Maps [[electronic resource] /] / by Peter van Emde Boas, Ghica van Emde Boas, Kaibo Xie, Bonan Zhao |
| Autore | Emde Boas P. van |
| Edizione | [1st ed. 2022.] |
| Pubbl/distr/stampa | Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2022 |
| Descrizione fisica | 1 online resource (416 pages) |
| Disciplina | 371.320973 |
| Collana | Logic in Asia: Studia Logica Library |
| Soggetto topico |
Logic
Historical linguistics Historical Linguistics History of China Lògica Processament de dades |
| Soggetto genere / forma | Llibres electrònics |
| ISBN | 981-19-6250-2 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Sun Tzu and the Art of War -- Diagramming Ancient Text -- The Making of a Mind Map -- Logic -- Patterns -- Conditional Sentences -- The Linguistic Perspective -- Game Theory and Strategic Thinking -- The Mind Mapping Perspective -- Start Planning -- Waging War -- Planning Attack -- Tactical Dispositions -- Energy -- Weak Points and Strong -- Contending -- Nine Variations -- The Army on the March -- Terrain -- The Nine Situations -- The Attack by Fire -- The Use of Spies -- List of All Patterns -- Translations of The Art of War. |
| Record Nr. | UNISA-996490345403316 |
Emde Boas P. van
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| Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2022 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Analyzing the Logic of Sun Tzu in “The Art of War”, Using Mind Maps / / by Peter van Emde Boas, Ghica van Emde Boas, Kaibo Xie, Bonan Zhao
| Analyzing the Logic of Sun Tzu in “The Art of War”, Using Mind Maps / / by Peter van Emde Boas, Ghica van Emde Boas, Kaibo Xie, Bonan Zhao |
| Autore | Emde Boas P. van |
| Edizione | [1st ed. 2022.] |
| Pubbl/distr/stampa | Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2022 |
| Descrizione fisica | 1 online resource (416 pages) |
| Disciplina | 371.320973 |
| Collana | Logic in Asia: Studia Logica Library |
| Soggetto topico |
Logic
Historical linguistics Historical Linguistics History of China Lògica Processament de dades |
| Soggetto genere / forma | Llibres electrònics |
| ISBN | 981-19-6250-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Sun Tzu and the Art of War -- Diagramming Ancient Text -- The Making of a Mind Map -- Logic -- Patterns -- Conditional Sentences -- The Linguistic Perspective -- Game Theory and Strategic Thinking -- The Mind Mapping Perspective -- Start Planning -- Waging War -- Planning Attack -- Tactical Dispositions -- Energy -- Weak Points and Strong -- Contending -- Nine Variations -- The Army on the March -- Terrain -- The Nine Situations -- The Attack by Fire -- The Use of Spies -- List of All Patterns -- Translations of The Art of War. |
| Record Nr. | UNINA-9910616367203321 |
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Emde Boas P. van
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| Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2022 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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The capacity of local governments in Europe : autonomy, responsibilities and reforms / / Sabine Kuhlmann, Benoît Paul Dumas, Moritz Heuberger
| The capacity of local governments in Europe : autonomy, responsibilities and reforms / / Sabine Kuhlmann, Benoît Paul Dumas, Moritz Heuberger |
| Autore | Kuhlmann Sabine |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , [2022] |
| Descrizione fisica | 1 online resource (129 pages) |
| Disciplina | 371.320973 |
| Collana | Governance and Public Management |
| Soggetto topico | Local government - Europe |
| ISBN | 3-031-07962-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Intro -- Contents -- List of Figures -- List of Tables -- Chapter 1: Introduction -- Chapter 2: Comparison of the Role of Local Governments in Europe: Autonomy, Self-Government, Local Democracy -- 2.1 Comparison of European Administrative Models -- 2.2 Conceptual Framework: Dimensions for Comparing Local Governments' Capacities -- 2.3 Local Autonomy -- 2.4 Functional Responsibilities -- 2.5 Intergovernmental Relations -- 2.6 Territorial Profile -- 2.7 Political Profile -- 2.8 Conclusion -- Bibliography -- Chapter 3: Local Government Finances -- 3.1 European Models of Local Government Finance: Funding Sources and Volume of Expenditures -- 3.2 Role of European Structural Funds -- 3.3 Conclusion -- Bibliography -- Chapter 4: Reform Trends -- 4.1 Reform Discourses in Recent Decades -- 4.2 Recentralisation and Decentralisation -- 4.3 Territorial Reform -- 4.4 New Public Management and Privatisation -- 4.5 Post-New Public Management: Remunicipalisation -- 4.6 Conclusion: Diffusion and Convergence of Reform Models -- Bibliography -- Chapter 5: Conclusions -- Bibliography -- Annex -- Bibliography. |
| Record Nr. | UNINA-9910616386703321 |
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Kuhlmann Sabine
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| Cham, Switzerland : , : Springer, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Digital logic design using Verilog : coding and RTL synthesis / / Vaibbhav Taraate
| Digital logic design using Verilog : coding and RTL synthesis / / Vaibbhav Taraate |
| Autore | Taraate Vaibbhav |
| Edizione | [2nd ed.] |
| Pubbl/distr/stampa | Singapore : , : Springer, , [2022] |
| Descrizione fisica | 1 online resource (607 pages) |
| Disciplina | 371.320973 |
| Soggetto topico |
Logic design - Data processing
Verilog (Computer hardware description language) |
| ISBN |
981-16-3199-9
981-16-3198-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Preface -- Acknowledgements -- Contents -- About the Author -- 1 Introduction -- 1.1 Evolution of Logic Design -- 1.2 System and Logic Design Abstractions -- 1.2.1 Architecture Design -- 1.2.2 Micro-architecture Design -- 1.2.3 RTL Design and Synthesis -- 1.2.4 Switch Level Design -- 1.3 Integrated Circuit Design and Methodologies -- 1.3.1 RTL Design -- 1.3.2 Functional Verification -- 1.3.3 Synthesis -- 1.3.4 Physical Design -- 1.4 Verilog as Hardware Description Language -- 1.5 Verilog Design Description -- 1.5.1 Structural Design -- 1.5.2 Behavior Design -- 1.5.3 Synthesizable Design -- 1.6 Few Important Verilog Terminologies -- 1.7 Exercises -- 1.8 Summary -- 2 Concept of Concurrency and Verilog Operators -- 2.1 Use of Continuous Assignment to Model Design -- 2.2 Use of always Procedural Block to Implement Combinational Design -- 2.3 Concept of Concurrency -- 2.4 Verilog Arithmetic Operators -- 2.5 Verilog Logical Operators -- 2.6 Verilog Equality and Inequality Operators -- 2.7 Verilog Sign Operators -- 2.8 Verilog Bitwise Operators -- 2.9 Verilog Relational Operators -- 2.10 Verilog Concatenation and Replication Operators -- 2.11 Verilog Reduction Operators -- 2.12 Verilog Shift Operators -- 2.13 Exercises -- 2.14 Summary -- 3 Verilog Constructs and Combinational Design-I -- 3.1 The Role of Constructs -- 3.2 Logic Gates and Synthesizable RTL -- 3.2.1 NOT or Invert Logic -- 3.2.2 OR Logic -- 3.2.3 NOR Logic -- 3.2.4 AND Logic -- 3.2.5 NAND Logic -- 3.2.6 Two Input XOR Logic -- 3.2.7 Two Input XNOR Logic -- 3.3 Tristate Logic -- 3.4 Arithmetic Circuits -- 3.4.1 Adder -- 3.4.1.1 Half Adder -- 3.4.1.2 Full Adder -- 3.4.2 Subtractor -- 3.4.2.1 Half Subtractor -- 3.4.2.2 Full Subtractor -- 3.5 Exercises -- 3.6 Summary -- 4 Verilog Constructs and Combinational Design-II -- 4.1 Procedural Block always @*.
4.2 Multi-bit Adders and Subtractors -- 4.2.1 Four-Bit Full Adder -- 4.2.2 4-Bit Full Subtractor -- 4.2.3 4-Bit Adder and Subtractor -- 4.3 Optimization of Resources -- 4.3.1 Optimization Using Only Adders -- 4.3.2 Optimization by Tweaking the Logic to Have Better Data and Control Path -- 4.4 Procedural Block initial -- 4.5 Simulation Concepts: Basic Testbench -- 4.6 Comparators and Parity Detectors -- 4.6.1 Binary Comparators -- 4.6.2 Parity Detector -- 4.7 Code Converters -- 4.7.1 Binary to Gray Code Converter -- 4.7.2 Gray to Binary Code Converter -- 4.8 Let Us Think About the Design from Specifications -- 4.9 Exercises -- 4.10 Summary -- 5 Multiplexers as Universal Logic -- 5.1 Multiplexers -- 5.2 Multiplexer as Universal logic -- 5.2.1 2:1 MUX -- 5.3 The if...else Versus case Construct -- 5.4 The 4:1 MUX Using if...else -- 5.5 The 4:1 MUX Using case Construct -- 5.6 The 4:1 Mux Using 2:1 MUX -- 5.7 Let Us Design Combinational Logic Using Multiplexers -- 5.8 Optimization Strategies Using RTL Tweaks -- 5.9 Exercises -- 5.10 Summary -- 6 Decoders and Encoders -- 6.1 Decoders -- 6.1.1 1 Line to 2 Decoder Using case construct -- 6.1.2 1 Line to 2 Decoder Having Enable Using case -- 6.1.3 2 Line to 4 Decoder with Enable Using case -- 6.1.4 2 Line to 4 Decoder with Active Low Enable Using case -- 6.1.5 2 to 4 Decoder Using Continuous Assignments -- 6.1.6 Decoder Using Shift Operator -- 6.1.7 Testbench of 2:4 Decoder -- 6.1.8 4 Line to 16 Decoder Using 2:4 Decoder -- 6.2 Testbench for 4:16 Decoder -- 6.3 Encoders -- 6.3.1 Priority Encoders -- 6.4 Testbench of 4:2 Priority encoder -- 6.5 Exercises -- 6.6 Summary -- 7 Event Queue and Design Guidelines -- 7.1 Verilog Stratified Event Queue -- 7.2 Verilog Blocking Assignments -- 7.3 Incomplete Sensitivity List -- 7.4 Continuous Versus Procedural Assignments -- 7.5 Combinational Loops in Design. 7.6 Unintentional Latches in the Design -- 7.7 Use of Blocking Assignments -- 7.8 Use of if...else Versus case constructs -- 7.9 Nested Multiplexer or Priority Logic -- 7.10 Parallel Logic or Decoding Logic -- 7.11 Priority Encoding Structure -- 7.12 Missing default Condition in case construct -- 7.13 Nested if...else with Missing else Condition -- 7.14 Logical Equality Versus Case Equality -- 7.14.1 Logical Equality and Logical Inequality Operators -- 7.14.2 Case Equality and Case Inequality Operators -- 7.15 Multiple Driver Assignments -- 7.16 Exercises -- 7.17 Summary -- 8 Basics of Sequential Design Using Verilog -- 8.1 Sequential Logic -- 8.1.1 Positive-Level Sensitive D Latch -- 8.1.2 Negative-Level Sensitive D Latch -- 8.2 Flip-Flop -- 8.2.1 Positive Edge-Triggered D Flip-Flop -- 8.2.2 Negative Edge-Triggered D Flip-Flop -- 8.2.3 Synchronous and Asynchronous Reset -- 8.2.3.1 D Flip-Flop Having Asynchronous Reset -- 8.2.4 D Flip-Flop Having Synchronous Reset -- 8.2.5 Flip-Flop Having Synchronous Load Enable and Asynchronous Reset -- 8.2.6 Flip-Flop with Synchronous Load and Synchronous Reset -- 8.3 Exercises -- 8.4 Summary -- 9 Synchronous Counter Design Using Synthesizable Constructs -- 9.1 Synchronous Counters -- 9.1.1 Three-Bit Up Counter -- 9.1.2 Three-Bit Down Counter -- 9.1.3 Three-Bit Up-Down Counter -- 9.2 Gray Counters -- 9.2.1 Gray and Binary Counter -- 9.2.2 Ring Counters -- 9.2.3 Johnson Counters -- 9.3 BCD Up-Down Counter -- 9.4 Exercises -- 9.5 Summary -- 10 RTL Design of Registers and Memories -- 10.1 Parallel Input and Parallel Output (PIPO) Register -- 10.2 Shift Register -- 10.3 Right and Left Shift Operation -- 10.4 Timing and Performance Evaluation -- 10.5 Asynchronous Counter Design -- 10.5.1 Ripple Counters -- 10.6 RTL Design of Memories -- 10.7 Parameterized Read-Write Memory -- 10.8 Exercises -- 10.9 Summary. 11 Sequential Circuit Design Guidelines -- 11.1 What Happens If Blocking Assignments Are Used to Code Sequential Logic? -- 11.1.1 Blocking Assignments and Multiple always Blocks -- 11.1.2 Multiple Blocking Assignments Used in the Single always Block -- 11.1.3 Example Blocking Assignment -- 11.2 Non-blocking Assignments -- 11.2.1 Example Non-blocking Assignments -- 11.2.2 Example Non-blocking Assignment -- 11.2.3 Example Using Non-blocking Assignments -- 11.3 Latch Versus Flip-Flop -- 11.3.1 D Flip-Flop -- 11.3.2 Latch -- 11.4 Use of Synchronous Versus Asynchronous Reset -- 11.4.1 D Flip-Flop Having Asynchronous Reset -- 11.4.2 Synchronous Reset D Flip-Flop -- 11.5 Use of if...else Versus case constructs -- 11.6 Internally Generated Clocks -- 11.7 Guidelines for Modeling Synchronous Designs -- 11.8 Multiple Clocks in the Same module -- 11.9 Multi-phase Clocks in the Design -- 11.10 Guidelines for Modeling Asynchronous Designs -- 11.11 Exercises -- 11.12 Summary -- 12 RTL Design Strategies for Complex Designs -- 12.1 ALU Design -- 12.1.1 Logic Unit Design -- 12.1.1.1 Logic Unit to Infer Parallel Logic -- 12.1.1.2 Logic Unit Having Registered Inputs and Outputs -- 12.1.2 Arithmetic Unit -- 12.1.3 Arithmetic and Logic Unit -- 12.2 Functions and Tasks -- 12.2.1 Counting Number of 1's from the Given String -- 12.2.2 RTL Design Using function to Count Number of 1'S -- 12.3 Synthesis Result of RTL Using function -- 12.4 Synthesis Result of RTL Using task -- 12.5 Exercises -- 12.6 Summary -- 13 RTL Tweaks and Performance Improvement Techniques -- 13.1 Arithmetic Resource Sharing -- 13.1.1 RTL Design Using Resource Sharing to Have Area Optimization -- 13.2 Gated Clocks and Dynamic Power Reduction -- 13.3 Use of Pipelining in Design -- 13.3.1 Design Without Pipelining -- 13.3.2 Speed Improvement Using Register Balancing or Pipelining. 13.4 Counter Design and Duty Cycle Control -- 13.5 MOD-3 Counter RTL Design to Have 50% Duty Cycle -- 13.6 Exercise -- 13.7 Summary -- 14 Finite State Machines Using Verilog -- 14.1 Moore Versus Mealy Machines -- 14.1.1 Level to Pulse Converter -- 14.2 FSM Encoding Styles -- 14.2.1 Binary Encoding -- 14.2.1.1 Two-Bit Binary Counter FSM -- 14.2.2 Gray Encoding -- 14.2.2.1 Two-Bit Gray Counter FSM -- 14.3 One-Hot Encoding -- 14.4 Sequence Detectors Using FSMs -- 14.4.1 Mealy Sequence Detector Using Two always Procedural Blocks -- 14.4.2 Mealy Machine: Sequence Detector to Detect 101 Overlapping Sequence -- 14.5 Improving the Design Performance for FSMs -- 14.6 Exercises -- 14.7 Summary -- 15 Non-synthesizable Verilog Constructs and Testbenches -- 15.1 Intra-delay and Inter-delay Assignments -- 15.1.1 Simulation for Blocking Assignments -- 15.1.2 Simulation of Non-blocking Assignments -- 15.2 The always and initial Procedural Block -- 15.2.1 Blocking Assignments with Inter-assignment Delays -- 15.2.2 Blocking Assignments with Intra-assignment Delays -- 15.2.3 Non-blocking Assignments with Inter-assignment Delays -- 15.2.4 Non-blocking Assignments with Intra-assignment Delays -- 15.3 Role of Testbenches -- 15.4 Multiple Assignments Within the begin-end -- 15.5 Multiple Assignments Within the fork-join -- 15.6 Display Tasks -- 15.7 Exercises -- 15.8 Summary -- 16 FPGA Architecture and Design Flow -- 16.1 Introduction to PLD -- 16.2 FPGA as Programmable ASIC -- 16.2.1 SRAM Based FPGA -- 16.2.2 Flash Based FPGA -- 16.2.3 Antifuse FPGAS -- 16.2.4 Important FPGA Blocks -- 16.3 FPGA Design Flow -- 16.3.1 Design Entry -- 16.3.2 Design Simulation and Synthesis -- 16.3.3 Design Implementation -- 16.3.4 Device Programming -- 16.4 Logic Realization Using FPGA -- 16.4.1 Configurable Logic Block -- 16.4.2 Input Output Block (IOB) -- 16.4.3 Block RAM. 16.4.4 Digital Clock Manager (DCM) Block. |
| Record Nr. | UNINA-9910743250303321 |
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Taraate Vaibbhav
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| Singapore : , : Springer, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Epistolae Duorum Amantium : Parodien - Auf ein Berühmtes Liebespaar? / / Rüdiger Schnell
| Epistolae Duorum Amantium : Parodien - Auf ein Berühmtes Liebespaar? / / Rüdiger Schnell |
| Autore | Schnell Rüdiger |
| Edizione | [First edition.] |
| Pubbl/distr/stampa | Leiden, Netherlands : , : Brill, , [2022] |
| Descrizione fisica | 1 online resource (640 pages) |
| Disciplina | 371.320973 |
| Collana | Mittellateinische Studien und Texte Series |
| Soggetto topico |
Love-letters - History
Parody in literature Philosophers |
| ISBN |
9789004498167
9789004471900 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | ger |
| Record Nr. | UNINA-9910795329803321 |
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Schnell Rüdiger
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| Leiden, Netherlands : , : Brill, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Epistolae Duorum Amantium : Parodien - Auf ein Berühmtes Liebespaar? / / Rüdiger Schnell
| Epistolae Duorum Amantium : Parodien - Auf ein Berühmtes Liebespaar? / / Rüdiger Schnell |
| Autore | Schnell Rüdiger |
| Edizione | [First edition.] |
| Pubbl/distr/stampa | Leiden, Netherlands : , : Brill, , [2022] |
| Descrizione fisica | 1 online resource (640 pages) |
| Disciplina | 371.320973 |
| Collana | Mittellateinische Studien und Texte Series |
| Soggetto topico |
Love-letters - History
Parody in literature Philosophers |
| ISBN |
9789004498167
9789004471900 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | ger |
| Record Nr. | UNINA-9910820870803321 |
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Schnell Rüdiger
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| Leiden, Netherlands : , : Brill, , [2022] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Inductive Logic Programming : 31st International Conference, ILP 2022, Windsor Great Park, UK, September 28–30, 2022, Proceedings / / edited by Stephen H. Muggleton, Alireza Tamaddoni-Nezhad
| Inductive Logic Programming : 31st International Conference, ILP 2022, Windsor Great Park, UK, September 28–30, 2022, Proceedings / / edited by Stephen H. Muggleton, Alireza Tamaddoni-Nezhad |
| Edizione | [1st ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (167 pages) |
| Disciplina | 371.320973 |
| Collana | Lecture Notes in Artificial Intelligence |
| Soggetto topico |
Artificial intelligence
Computer engineering Computer networks Compilers (Computer programs) Computer science Machine theory Artificial Intelligence Computer Engineering and Networks Compilers and Interpreters Computer Science Logic and Foundations of Programming Formal Languages and Automata Theory |
| ISBN | 3-031-55630-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910845098803321 |
| Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Introduction to Logic Circuits & Logic Design with VHDL / / by Brock J. LaMeres
| Introduction to Logic Circuits & Logic Design with VHDL / / by Brock J. LaMeres |
| Autore | LaMeres Brock J. |
| Edizione | [3rd ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (544 pages) |
| Disciplina | 371.320973 |
| Soggetto topico |
Electronic circuits
Microprocessors Computer architecture Logic design Electronic Circuits and Systems Processor Architectures Logic Design |
| ISBN | 3-031-42547-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Analog Vs. Digital -- Number Systems -- Digital Circuitry & Interfacing -- Combinational Logic Design -- VHDL (Part 1) -- MSI Logic -- Sequential Logic Design -- VHDL (Part 2) -- Behavioral Modeling Of Sequential Logic -- Memory -- Programmable Logic -- Arithmetic Circuits -- Computer System Design -- Floating-Point Systems. |
| Record Nr. | UNINA-9910760250003321 |
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LaMeres Brock J.
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Lecture Notes in Analog Electronics : Low Voltage Electronic Components / / by Vančo Litovski
| Lecture Notes in Analog Electronics : Low Voltage Electronic Components / / by Vančo Litovski |
| Autore | Litovski Vanco |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (429 pages) |
| Disciplina | 371.320973 |
| Collana | Lecture Notes in Electrical Engineering |
| Soggetto topico |
Power electronics
Solid state physics Optoelectronic devices Semiconductors Power Electronics Electronic Devices Optoelectronic Devices |
| ISBN | 981-19-9868-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Electric current in semiconductors -- The p-n junction and the diode -- Bipolar transistor – BJT -- Junction field effect transistor – JFET -- Insulated gate field effect transistors - IGFET -- MESFET -- Optoelectronic components -- Magnetoelectronic components -- Basics of semiconductor technology. |
| Record Nr. | UNINA-9910729895303321 |
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Litovski Vanco
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| Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Perspectives on Deduction: Contemporary Studies in the Philosophy, History and Formal Theories of Deduction / / edited by Antonio Piccolomini d'Aragona
| Perspectives on Deduction: Contemporary Studies in the Philosophy, History and Formal Theories of Deduction / / edited by Antonio Piccolomini d'Aragona |
| Edizione | [1st ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (421 pages) : illustrations |
| Disciplina | 371.320973 |
| Collana | Synthese Library, Studies in Epistemology, Logic, Methodology, and Philosophy of Science |
| Soggetto topico |
Logic
Mathematical logic Knowledge, Theory of Mathematics - Philosophy Mathematical Logic and Foundations Epistemology Philosophy of Mathematics |
| ISBN | 3-031-51406-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | 1. Introduction: deduction at the crossroads (Antonio Piccolomini d'Aragona) -- 2. The interdependence between the concepts of valid inference and proof revisited (Dag Prawitz) -- 3. The completeness theorem? So what! (Goran Sundholm) -- 4. Godel's absolute proofs and Girard's Ludics. Mutual insights (Gabriella Crocco and Myriam Quatrini) -- 5. Dummett, analytic and synthetic deductions (Cesare Cozzo) -- 6. From proof-objects to grounds (Enrico Moriconi) -- 7. On an ecumenical natural deduction with stoup - Part I: the propositional case (Luiz Carlos Pereira and Elaine Pimentel) -- 8. Martin-Lof on the validity of inference (Ansten Klev) -- 9. Molecularity in the theory of meaning and the topic neutrality of logic (Nils Kurbis and Bernhard Weiss) -- 10. Assertion, assumption and deduction (Peter Pagin) -- 11. Deduction and ampliativity: a critical appraisal (Emiliano Ippoliti) -- 12. A new conjecture about identity of proofs (Paolo Pistone) -- 13. Godel's introduction to deduction (Milos Adzic) -- 14. Karl Popper on deduction (Thomas Piecha) -- 15. An epistemological view on the Peano School Axiomatics (Paola Cantu) -- 16. Inferential quantification and the w-rule (Constantin Brincus) -- 17. Chains of inferences in proof by induction: a cognitive analysis (Samuele Antonini and Bernardo Nannini) -- 18. From strategies to derivations and back. An easy completeness proof for first-order intuitionistic dialogical logic (Davide Catta) -- Index. |
| Record Nr. | UNINA-9910847083103321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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