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2014 International Conference on the Internet of Things (IOT 2014) : : Cambridge, Massachusetts, USA 6-8 October 2014
| 2014 International Conference on the Internet of Things (IOT 2014) : : Cambridge, Massachusetts, USA 6-8 October 2014 |
| Pubbl/distr/stampa | IEEE |
| Disciplina | 006.2/2 |
| Soggetto topico |
Ubiquitous computing
Embedded Internet devices Wireless communication systems Ambient intelligence Interactive computer systems Sensor networks Radio frequency identification systems Internet |
| ISBN | 1-4799-5154-4 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
2014 International Conference on the Internet of Things
Internet of Things |
| Record Nr. | UNISA-996280404003316 |
| IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
2014 International Conference on the Internet of Things (IOT 2014) : : Cambridge, Massachusetts, USA 6-8 October 2014
| 2014 International Conference on the Internet of Things (IOT 2014) : : Cambridge, Massachusetts, USA 6-8 October 2014 |
| Pubbl/distr/stampa | IEEE |
| Disciplina | 006.2/2 |
| Soggetto topico |
Ubiquitous computing
Embedded Internet devices Wireless communication systems Ambient intelligence Interactive computer systems Sensor networks Radio frequency identification systems Internet |
| ISBN | 1-4799-5154-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
2014 International Conference on the Internet of Things
Internet of Things |
| Record Nr. | UNINA-9910132685003321 |
| IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Arduino Software Internals : A Complete Guide to How Your Arduino Language and Hardware Work Together
| Arduino Software Internals : A Complete Guide to How Your Arduino Language and Hardware Work Together |
| Autore | Dunbar Norman |
| Edizione | [2nd ed.] |
| Pubbl/distr/stampa | Berkeley, CA : , : Apress L. P., , 2024 |
| Descrizione fisica | 1 online resource (393 pages) |
| Disciplina | 006.2/2 |
| Collana | Maker Innovations Series |
| Soggetto topico | Arduino (Programmable controller) |
| ISBN | 9798868801716 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Intro -- Contents -- About the Author -- About the Technical Reviewer -- Acknowledgments -- Preface -- Preface to the Second Edition -- 1 Introduction -- 1.1 Arduino Installation Paths -- 1.2 Coding Style -- 1.2.1 Number Formats -- 1.3 The Arduino Language -- 1.4 Coming Up -- 2 Arduino Compilation -- 2.1 Settings.json -- 2.1.1 Finding Other Hidden Settings -- 2.1.2 Setting Tab Stops -- 2.2 Globally Defined Properties -- 2.3 Boards.txt -- 2.3.1 Arduino Uno Example -- 2.3.1.1 Board Identifier -- 2.3.1.2 Identification Settings -- 2.3.1.3 Upload Settings -- 2.3.1.4 Bootloader Settings -- 2.3.1.5 Build Settings -- 2.3.1.6 Configuring an ICSP -- 2.4 Boards.local.txt -- 2.5 Platform.txt -- 2.5.1 Build Recipes -- 2.5.2 Pre- and Post-Build Hooks -- 2.6 Programmers.txt -- 2.7 Compiling a Sketch -- 2.7.1 Arduino Sketch (*.ino) Preprocessing -- 2.7.2 Arduino Sketch (*.ino) Build -- 2.7.3 After the Build -- 2.8 The Arduino main() Function -- 2.9 Header File Arduino.h -- 2.9.1 Header File avr/pgmspace.h -- 2.9.2 Header File avr/io.h -- 2.9.2.1 Header File avr/iom328p.h -- 2.9.2.2 Header File avr/portpins.h -- 2.9.2.3 Header File < -- avr/common.h> -- -- 2.9.2.4 Header File < -- avr/version.h> -- -- 2.9.2.5 Header File < -- avr/fuse.h> -- -- 2.9.2.6 Header File < -- avr/lock.h> -- -- 2.9.3 Header File avr\interrupt.h -- 2.9.4 Header File binary.h -- 2.9.5 Header File WCharacter.h -- 2.9.6 Header File WString.h -- 2.9.7 Header File HardwareSerial.h -- 2.9.8 Header File USBAPI.h -- 2.9.9 Header File pins_arduino.h -- 2.10 The init() Function -- 2.10.1 Enabling the Global Interrupt Flag -- 2.10.2 Enabling Timer 0 -- 2.10.3 Timer 0 Overflow Interrupt -- 2.10.4 Configuring Timer 1 and Timer 2 -- 2.10.5 Initializing the Analog-to-Digital Converter -- 2.10.6 Disabling the USART -- 3 Arduino Language Reference -- 3.1 What Are We Looking At?.
3.2 Digital Input/Output -- 3.2.1 Function pinMode() -- 3.2.2 Function digitalRead() -- 3.2.3 Function digitalWrite() -- 3.3 Analog Input/Output -- 3.3.1 Function analogReference() -- 3.3.2 Function analogRead() -- 3.3.3 Function analogWrite() -- 3.4 Advanced Input/Output -- 3.4.1 Function tone() -- 3.4.2 Function noTone() -- 3.4.3 Function pulseIn() -- 3.4.4 Function pulseInLong() -- 3.4.5 Function shiftIn() -- 3.4.6 Function shiftOut() -- 3.5 Time -- 3.5.1 Function delay() -- 3.5.2 Function delayMicroseconds() -- 3.5.3 Function micros() -- 3.5.4 Function millis() -- 3.6 Interrupts -- 3.6.1 Function interrupts() -- 3.6.2 Function noInterrupts() -- 3.6.3 Function attachInterrupt() -- 3.6.4 Function detachInterrupt() -- 3.7 Bits and Bobs -- 3.7.1 Macro bit() -- 3.7.2 Macro bitClear() -- 3.7.3 Macro bitRead() -- 3.7.4 Macro bitSet() -- 3.7.5 Macro bitWrite() -- 3.7.6 Macro bitToggle() -- 3.7.7 Macro highByte() -- 3.7.8 Macro lowByte() -- 3.7.9 Macro sbi() -- 3.7.10 Macro cbi() -- 4 Arduino Classes -- 4.1 The Print Class -- 4.1.1 Class Members -- 4.1.2 Using the Print Class -- 4.2 The Printable Class -- 4.2.1 An Example Printable Class -- 4.3 The Stream Class -- 4.3.1 Class Members -- 4.4 The HardwareSerial Class -- 4.4.1 Interrupt Handlers -- 4.4.1.1 USART Receive Complete Interrupt -- 4.4.1.2 USART Data Register Empty Interrupt -- 4.4.2 Class Functions and Macros -- 4.4.2.1 Macro SERIAL_TX_BUFFER_SIZE -- 4.4.2.2 Macro SERIAL_RX_BUFFER_SIZE -- 4.4.2.3 Typedef tx_buffer_index_t and rx_buffer_index_t -- 4.4.2.4 Serial Communications Parameters -- 4.4.2.5 Macro HAVE_HWSERIAL0 -- 4.4.2.6 Constructor HardwareSerial() -- 4.4.2.7 Function begin(unsigned long baud) -- 4.4.2.8 Function begin(unsigned long, uint8_t) -- 4.4.2.9 Function end() -- 4.4.2.10 Operator bool() -- 4.4.2.11 Function available(void) -- 4.4.2.12 Function peek(void). 4.4.2.13 Function read(void) -- 4.4.2.14 Function availableForWrite(void) -- 4.4.2.15 Function flush(void) -- 4.4.2.16 Function write(uint8_t) -- 4.4.2.17 Function _rx_complete_irq(void) -- 4.4.2.18 Function _tx_udr_empty_irq(void) -- 4.5 The String Class -- 5 Converting to the AVR Language -- 5.1 Introduction -- 5.2 Numbering Systems -- 5.2.1 Decimal Numbering -- 5.2.2 Binary Numbering -- 5.2.3 Hexadecimal Numbering -- 5.3 Binary Logical Operations -- 5.3.1 NOT -- 5.3.2 AND -- 5.3.3 OR -- 5.3.4 XOR -- 5.4 Replacing the Arduino Language -- 5.4.1 The ATmega328P Pins and Ports -- 5.4.2 Replacing pinMode() -- 5.4.3 Replacing digitalWrite() -- 5.4.4 Enabling Internal Pull-Up Resistors -- 5.4.4.1 Bit Twiddling -- 5.4.5 Replacing digitalRead() -- 5.4.6 Toggling Output Pins -- 5.4.7 Installing digitalToggle() -- 6 Alternatives to the Arduino IDE -- 6.1 What Are the Alternatives? -- 6.2 PlatformIO -- 6.2.1 System Requirements -- 6.2.2 Installing PlatformIO IDE -- 6.2.2.1 The Toolbar -- 6.2.2.2 PIO Home Tab -- 6.2.2.3 Creating a New Project -- 6.2.2.4 Import Arduino Project -- 6.2.2.5 Opening Existing Projects -- 6.2.2.6 Project Examples -- 6.2.2.7 Editing the Project -- 6.2.2.8 Compiling a Project -- 6.2.2.9 Upload a Project -- 6.2.3 Testing PlatformIO Core -- 6.2.3.1 Set Up a New Project -- 6.2.3.2 Initialize the Project -- 6.2.4 PlatformIO for Arduino-Style Projects -- 6.2.4.1 Compiling Arduino Projects -- 6.2.4.2 Uploading Arduino Projects -- 6.2.5 PlatformIO for AVR-Style Projects -- 6.2.5.1 Compiling AVR Projects -- 6.2.5.2 Uploading AVR Projects -- 6.2.6 Burning Bootloaders -- 6.2.7 Using Your Own IDE -- 6.2.8 Adding Additional Boards -- 6.2.9 PlatformIO Home -- 6.2.9.1 Creating Projects -- 6.2.9.2 Importing Arduino Sketches -- 6.2.9.3 Opening Projects -- 6.3 Arduino Command Line -- 6.3.1 Obtaining the Arduino CLI -- 6.3.2 Installing the Arduino CLI. 6.3.3 Configuring the CLI -- 6.3.4 Creating Sketches -- 6.3.5 Unknown Boards -- 6.3.6 Installing Platforms or Cores -- 6.3.7 Compiling Sketches -- 6.3.8 Uploading Sketches -- 6.3.8.1 Permissions Errors? -- 6.3.9 Uploading Sketches with an ICSP -- 6.3.10 Burning Bootloaders -- 6.3.11 Serial Usage -- 6.3.12 Profiles -- 6.3.13 A Simple Makefile -- 6.3.13.1 Verbosity -- 6.3.13.2 Compile -- 6.3.13.3 Upload -- 6.3.13.4 Program -- 6.3.13.5 Bootloader -- 6.3.13.6 Monitor -- 6.3.13.7 Details -- 6.3.13.8 Settings -- 6.3.13.9 Help -- 6.3.14 Library Manager -- 6.3.14.1 Downloadable Libraries -- 6.3.14.2 Zip File Libraries -- 6.3.14.3 Git Repository Libraries -- 6.3.14.4 Listing Libraries -- 6.3.14.5 Library Examples -- 6.3.15 Board Manager -- 7 ATmega328P Configuration and Management -- 7.1 ATmega328P Fuses -- 7.1.1 Low Fuse Bits -- 7.1.1.1 SUT Fuse Bits -- 7.1.1.2 CKSEL Fuse Bits -- 7.1.2 Low Fuse Factory Default -- 7.1.3 Arduino Low Fuse Settings -- 7.1.4 High Fuse Bits -- 7.1.5 High Fuse Factory Default -- 7.1.6 Arduino High Fuse Settings -- 7.1.7 Extended Fuse Bits -- 7.1.8 Extended Fuse Factory Default -- 7.1.9 Arduino Extended Fuse Settings -- 7.2 Brown Out Detection -- 7.3 The Watchdog Timer -- 7.3.1 Watchdog Timer Modes of Operation -- 7.3.2 Amended Sketch setup() Function -- 7.3.3 Watchdog Timer Reset -- 7.3.4 The Watchdog Timer Control Register -- 7.3.5 Enabling the Watchdog Timer -- 7.3.6 Setting the Watchdog Timer Timeout -- 7.3.7 Disabling the Watchdog Timer -- 7.4 Putting the AVR to Sleep -- 7.4.1 Sleep Modes -- 7.4.1.1 Features of All Sleep Modes -- 7.4.1.2 Idle Sleep Mode -- 7.4.1.3 ADC Noise Reduction Sleep Mode -- 7.4.1.4 Power Down Sleep Mode -- 7.4.1.5 Power Save Sleep Mode -- 7.4.1.6 Standby Sleep Mode -- 7.4.1.7 Extended Standby Sleep Mode -- 7.4.2 Sleep and the Analog Comparator -- 7.5 Power Reduction -- 7.5.1 Power Consumption. 7.5.1.1 Calculating Power Requirements -- 7.5.2 Power Reduction Register -- 7.5.3 Saving Arduino Power -- 7.5.4 The Power Functions -- 7.6 Bootloaders -- 7.6.1 Flash Memory -- 7.6.2 Lock Bits -- 7.6.2.1 Device Lock Bits -- 7.6.2.2 Bootloader Lock Bits -- 7.6.3 Installing the Uno (Optiboot) Bootloader -- 7.6.4 Optiboot Bootloader Operation -- 8 ATmega328P Hardware-Timers and Counters -- 8.1 Timers -- 8.1.1 Timer 0 (Eight Bits) -- 8.1.2 Timer 1 (16 Bits) -- 8.1.3 Timer 2 (Eight Bits) -- 8.1.4 Timer Clock Sources -- 8.1.5 Timer Non-PWM Operating Modes -- 8.1.5.1 Timers Disabled -- 8.1.5.2 Normal Mode -- 8.1.5.3 Clear Timer on Compare Match Mode -- 8.1.6 Timer PWM Modes -- 8.1.6.1 Duty Cycle -- 8.1.6.2 PWM Frequencies -- 8.1.6.3 Fast PWM Mode -- 8.1.6.4 Phase Correct PWM Mode -- 8.1.6.5 Phase and Frequency Correct PWM Mode -- 8.1.7 Too Much to Remember? Try AVRAssist -- 8.2 Counting -- 8.2.1 Setting External Counting -- 8.2.2 Counter Example -- 8.3 Input Capture Unit -- 9 ATmega328P Hardware-AC, ADC, and USART -- 9.1 Analog Comparator (AC) -- 9.1.1 Reference Voltage -- 9.1.2 Sampled Voltage -- 9.1.3 Digital Input -- 9.1.4 Enable the Analog Comparator -- 9.1.5 Select Reference Voltage Source -- 9.1.5.1 External Reference -- 9.1.5.2 Internal Bandgap Reference -- 9.1.6 Select Sampled Voltage Source Pin -- 9.1.6.1 Sample Voltage on Pin AIN1 -- 9.1.6.2 Sample Voltage on Pins A0-A7 -- 9.1.6.3 Sampled Voltage Summary -- 9.1.7 Comparator Outputs -- 9.1.8 Comparator Example -- 9.2 Analog-to-Digital Converter (ADC) -- 9.2.1 ADC Setup and Initiation -- 9.2.1.1 Powering the ADC -- 9.2.1.2 Selecting the Prescaler -- 9.2.1.3 Selecting the Reference Voltage Source -- 9.2.1.4 Left or Right Alignment? -- 9.2.1.5 Selecting an Input Source -- 9.2.1.6 Disable Digital Input -- 9.2.1.7 ADC Interrupt -- 9.2.1.8 Single Shot or Auto Trigger?. 9.2.1.9 Enabling the ADC and Initiating Conversions. |
| Record Nr. | UNINA-9910869163503321 |
Dunbar Norman
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| Berkeley, CA : , : Apress L. P., , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded SoPC design with NIOS II processor and Verilog examples [[electronic resource] /] / Pong P. Chu
| Embedded SoPC design with NIOS II processor and Verilog examples [[electronic resource] /] / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2012 |
| Descrizione fisica | 1 online resource (783 p.) |
| Disciplina | 006.2/2 |
| Soggetto topico |
Embedded computer systems
Field programmable gate arrays Verilog (Computer hardware description language) |
| ISBN |
1-280-59239-7
9786613622228 1-118-30957-X 1-118-30972-3 1-118-30946-4 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | pt. I. Basic digital circuits development -- pt. II. Basic NIOS II software development -- pt. III. Custom I/O peripheral development -- pt. IV. Hardware accelerator case studies. |
| Record Nr. | UNINA-9910139089603321 |
|
Chu Pong P. <1959->
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||
| Hoboken, N.J., : Wiley, c2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded SoPC design with NIOS II processor and Verilog examples [[electronic resource] /] / Pong P. Chu
| Embedded SoPC design with NIOS II processor and Verilog examples [[electronic resource] /] / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2012 |
| Descrizione fisica | 1 online resource (783 p.) |
| Disciplina | 006.2/2 |
| Soggetto topico |
Embedded computer systems
Field programmable gate arrays Verilog (Computer hardware description language) |
| ISBN |
1-280-59239-7
9786613622228 1-118-30957-X 1-118-30972-3 1-118-30946-4 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | pt. I. Basic digital circuits development -- pt. II. Basic NIOS II software development -- pt. III. Custom I/O peripheral development -- pt. IV. Hardware accelerator case studies. |
| Record Nr. | UNINA-9910822030103321 |
|
Chu Pong P. <1959->
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| Hoboken, N.J., : Wiley, c2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded systems [[electronic resource] ] : hardware, design, and implementation / / edited by Krzysztof Iniewski
| Embedded systems [[electronic resource] ] : hardware, design, and implementation / / edited by Krzysztof Iniewski |
| Pubbl/distr/stampa | Hoboken, N.J., : John Wiley & Sons, Inc., 2013 |
| Descrizione fisica | 1 online resource (387 p.) |
| Disciplina | 006.2/2 |
| Altri autori (Persone) | IniewskiKrzysztof |
| Soggetto topico | Embedded computer systems |
| ISBN |
1-118-46865-1
1-283-73564-4 1-118-46861-9 |
| Classificazione | TEC008070 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Title page; Copyright page; Contents; Preface; Contributors; 1: Low Power Multicore Processors for Embedded Systems; 1.1 Multicore Chip with Highly Efficient Cores; 1.2 SuperHTM RISC Engine Family (SH) Processor Cores; 1.2.1 History of SH Processor Cores; 1.2.2 Highly Efficient ISA; 1.2.3 Asymmetric In-Order Dual-Issue Superscalar Architecture; 1.3 SH-X: A Highly Efficient CPU Core; 1.3.1 Microarchitecture Selections; 1.3.2 Improved Superpipeline Structure; 1.3.3 Branch Prediction and Out-of-Order Branch Issue; 1.3.4 Low Power Technologies; 1.3.5 Performance and Efficiency Evaluations
1.4 SH-X FPU: A Highly Efficient FPU1.4.1 FPU Architecture of SH Processors; 1.4.2 Implementation of SH-X FPU; 1.4.3 Performance Evaluations with 3D Graphics Benchmark; 1.5 SH-X2: Frequency and Efficiency Enhanced Core; 1.5.1 Frequency Enhancement; 1.5.2 Low Power Technologies; 1.6 SH-X3: Multicore Architecture Extension; 1.6.1 SH-X3 Core Specifications; 1.6.2 Symmetric and Asymmetric Multiprocessor Support; 1.6.3 Core Snoop Sequence Optimization; 1.6.4 Dynamic Power Management; 1.6.5 RP-1 Prototype Chip; 1.6.6 RP-2 Prototype Chip; 1.7 SH-X4: ISA and Address Space Extension 1.7.1 SH-X4 Core Specifications1.7.2 Efficient ISA Extension; 1.7.3 Address Space Extension; 1.7.4 Data Transfer Unit; 1.7.5 RP-X Prototype Chip; References; 2: Special-Purpose Hardware for Computational Biology; 2.1 Molecular Dynamics Simulations on Graphics Processing Units; 2.1.1 Molecular Mechanics Force Fields; 2.1.2 Graphics Processing Units for MD Simulations; 2.2 Special-Purpose Hardware and Network Topologies for MD Simulations; 2.2.1 High-Throughput Interaction Subsystem; 2.2.2 Hardware Description of the Flexible Subsystem; 2.2.3 Performance and Conclusions 2.3 Quantum MC Applications on Field-Programmable Gate Arrays2.3.1 Energy Computation and WF Kernels; 2.3.2 Hardware Architecture; 2.3.3 PE and WF Computation Kernels; 2.4 Conclusions and Future Directions; References; 3: Embedded GPU Design; 3.1 Introduction; 3.2 System Architecture; 3.3 Graphics Modules Design; 3.3.1 RISC Processor; 3.3.2 Geometry Processor; 3.3.3 Rendering Engine; 3.4 System Power Management; 3.4.1 Multiple Power-Domain Management; 3.4.2 Power Management Unit; 3.5 Implementation Results; 3.5.1 Chip Implementation; 3.5.2 Comparisons; 3.6 Conclusion; References 4: Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors4.1 Introduction; 4.2 The DVP Interface; 4.3 The iBRIDGE-BB Architecture; 4.3.1 Configuring the iBRIDGE-BB; 4.3.2 Operation of the iBRIDGE-BB; 4.3.3 Description of Internal Blocks; 4.4 Hardware Implementation; 4.4.1 Verification in Field-Programmable Gate Array; 4.4.2 Application in Image Compression; 4.4.3 Application-Specific Integrated Circuit (ASIC) Synthesis and Performance Analysis; 4.5 Conclusion; Acknowledgments; References; 5: Embedded Computing Systems on FPGAs; 5.1 FPGA Architecture 5.2 FPGA Configuration Technology |
| Record Nr. | UNINA-9910141415403321 |
| Hoboken, N.J., : John Wiley & Sons, Inc., 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded systems [[electronic resource] ] : hardware, design, and implementation / / edited by Krzysztof Iniewski
| Embedded systems [[electronic resource] ] : hardware, design, and implementation / / edited by Krzysztof Iniewski |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Hoboken, N.J., : John Wiley & Sons, Inc., 2013 |
| Descrizione fisica | 1 online resource (387 p.) |
| Disciplina | 006.2/2 |
| Altri autori (Persone) | IniewskiKrzysztof |
| Soggetto topico | Embedded computer systems |
| ISBN |
1-118-46865-1
1-283-73564-4 1-118-46861-9 |
| Classificazione | TEC008070 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Title page; Copyright page; Contents; Preface; Contributors; 1: Low Power Multicore Processors for Embedded Systems; 1.1 Multicore Chip with Highly Efficient Cores; 1.2 SuperHTM RISC Engine Family (SH) Processor Cores; 1.2.1 History of SH Processor Cores; 1.2.2 Highly Efficient ISA; 1.2.3 Asymmetric In-Order Dual-Issue Superscalar Architecture; 1.3 SH-X: A Highly Efficient CPU Core; 1.3.1 Microarchitecture Selections; 1.3.2 Improved Superpipeline Structure; 1.3.3 Branch Prediction and Out-of-Order Branch Issue; 1.3.4 Low Power Technologies; 1.3.5 Performance and Efficiency Evaluations
1.4 SH-X FPU: A Highly Efficient FPU1.4.1 FPU Architecture of SH Processors; 1.4.2 Implementation of SH-X FPU; 1.4.3 Performance Evaluations with 3D Graphics Benchmark; 1.5 SH-X2: Frequency and Efficiency Enhanced Core; 1.5.1 Frequency Enhancement; 1.5.2 Low Power Technologies; 1.6 SH-X3: Multicore Architecture Extension; 1.6.1 SH-X3 Core Specifications; 1.6.2 Symmetric and Asymmetric Multiprocessor Support; 1.6.3 Core Snoop Sequence Optimization; 1.6.4 Dynamic Power Management; 1.6.5 RP-1 Prototype Chip; 1.6.6 RP-2 Prototype Chip; 1.7 SH-X4: ISA and Address Space Extension 1.7.1 SH-X4 Core Specifications1.7.2 Efficient ISA Extension; 1.7.3 Address Space Extension; 1.7.4 Data Transfer Unit; 1.7.5 RP-X Prototype Chip; References; 2: Special-Purpose Hardware for Computational Biology; 2.1 Molecular Dynamics Simulations on Graphics Processing Units; 2.1.1 Molecular Mechanics Force Fields; 2.1.2 Graphics Processing Units for MD Simulations; 2.2 Special-Purpose Hardware and Network Topologies for MD Simulations; 2.2.1 High-Throughput Interaction Subsystem; 2.2.2 Hardware Description of the Flexible Subsystem; 2.2.3 Performance and Conclusions 2.3 Quantum MC Applications on Field-Programmable Gate Arrays2.3.1 Energy Computation and WF Kernels; 2.3.2 Hardware Architecture; 2.3.3 PE and WF Computation Kernels; 2.4 Conclusions and Future Directions; References; 3: Embedded GPU Design; 3.1 Introduction; 3.2 System Architecture; 3.3 Graphics Modules Design; 3.3.1 RISC Processor; 3.3.2 Geometry Processor; 3.3.3 Rendering Engine; 3.4 System Power Management; 3.4.1 Multiple Power-Domain Management; 3.4.2 Power Management Unit; 3.5 Implementation Results; 3.5.1 Chip Implementation; 3.5.2 Comparisons; 3.6 Conclusion; References 4: Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors4.1 Introduction; 4.2 The DVP Interface; 4.3 The iBRIDGE-BB Architecture; 4.3.1 Configuring the iBRIDGE-BB; 4.3.2 Operation of the iBRIDGE-BB; 4.3.3 Description of Internal Blocks; 4.4 Hardware Implementation; 4.4.1 Verification in Field-Programmable Gate Array; 4.4.2 Application in Image Compression; 4.4.3 Application-Specific Integrated Circuit (ASIC) Synthesis and Performance Analysis; 4.5 Conclusion; Acknowledgments; References; 5: Embedded Computing Systems on FPGAs; 5.1 FPGA Architecture 5.2 FPGA Configuration Technology |
| Record Nr. | UNINA-9910819603603321 |
| Hoboken, N.J., : John Wiley & Sons, Inc., 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Embedded systems development : from functional models to implementations / / Alberto Sangiovanni-Vincentelli, Haibo Zeng, Marco Di Natale, Peter Marwedel, editors
| Embedded systems development : from functional models to implementations / / Alberto Sangiovanni-Vincentelli, Haibo Zeng, Marco Di Natale, Peter Marwedel, editors |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | New York : , : Springer, , 2014 |
| Descrizione fisica | 1 online resource (viii, 223 pages) : illustrations (some color) |
| Disciplina | 006.2/2 |
| Collana | Embedded Systems |
| Soggetto topico |
Embedded computer systems - Design and construction
Systemes enfouis (informatique) - Conception et construction - Actes de congres |
| ISBN | 1-4614-3879-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction: Modeling, Analysis and Synthesis of Embedded Software and Systems -- Part I Model-Based Design and Synthesis -- Modeling, Analysis, and Implementation of Streaming Applications for Hardware Targets -- Dataflow-based, Cross-Platform Design Flow for DSP Applications -- Part II Model-Driven, Integration and Verification of Heterogeneous Models -- On Integrating EAST-ADL and UPPAAL for Embedded System Architecture Verification -- Schedulability Analysis at Early Design Stages with MARTE -- Part III Component-Based Design and Real-Time Components -- Early Time-Budgeting for Component-Based Embedded Control Systems -- Contract-Based Reasoning for Component systems with Rich Interactions -- Extracting End-to-end Timing Models from Component-Based Distributed Embedded Systems -- Part IV Timing Analysis and Time-Based Synthesis -- Distributed Priority Assignment in Real-Time Systems -- Exploration of Distributed Automotive Systems using Compositional Timing Analysis -- Design and Evaluation of Future Ethernet AVB-based ECU Networks. |
| Record Nr. | UNINA-9910299758703321 |
| New York : , : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Introduction to embedded systems : a cyber-physical systems approach / / Edward Ashford Lee and Sanjit Arunkumar Seshia
| Introduction to embedded systems : a cyber-physical systems approach / / Edward Ashford Lee and Sanjit Arunkumar Seshia |
| Autore | Lee Edward A. <1957-> |
| Pubbl/distr/stampa | The MIT Press Open |
| Disciplina | 006.2/2 |
| Soggetto topico | Embedded computer systems |
| ISBN | 0-262-53381-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996437054003316 |
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Lee Edward A. <1957->
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| The MIT Press Open | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Introduction to embedded systems : a cyber-physical systems approach / / Edward Ashford Lee and Sanjit Arunkumar Seshia
| Introduction to embedded systems : a cyber-physical systems approach / / Edward Ashford Lee and Sanjit Arunkumar Seshia |
| Autore | Lee Edward A. <1957-> |
| Pubbl/distr/stampa | The MIT Press Open |
| Disciplina | 006.2/2 |
| Soggetto topico | Embedded computer systems |
| ISBN | 0-262-53381-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910765887703321 |
|
Lee Edward A. <1957->
|
||
| The MIT Press Open | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
