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2014 International Conference on the Internet of Things (IOT 2014) : : Cambridge, Massachusetts, USA 6-8 October 2014
| 2014 International Conference on the Internet of Things (IOT 2014) : : Cambridge, Massachusetts, USA 6-8 October 2014 |
| Pubbl/distr/stampa | IEEE |
| Disciplina | 006.2/2 |
| Soggetto topico |
Ubiquitous computing
Embedded Internet devices Wireless communication systems Ambient intelligence Interactive computer systems Sensor networks Radio frequency identification systems Internet |
| ISBN | 1-4799-5154-4 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
2014 International Conference on the Internet of Things
Internet of Things |
| Record Nr. | UNISA-996280404003316 |
| IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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2014 International Conference on the Internet of Things (IOT 2014) : : Cambridge, Massachusetts, USA 6-8 October 2014
| 2014 International Conference on the Internet of Things (IOT 2014) : : Cambridge, Massachusetts, USA 6-8 October 2014 |
| Pubbl/distr/stampa | IEEE |
| Disciplina | 006.2/2 |
| Soggetto topico |
Ubiquitous computing
Embedded Internet devices Wireless communication systems Ambient intelligence Interactive computer systems Sensor networks Radio frequency identification systems Internet |
| ISBN | 1-4799-5154-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
2014 International Conference on the Internet of Things
Internet of Things |
| Record Nr. | UNINA-9910132685003321 |
| IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Arduino Software Internals : A Complete Guide to How Your Arduino Language and Hardware Work Together / / by Norman Dunbar
| Arduino Software Internals : A Complete Guide to How Your Arduino Language and Hardware Work Together / / by Norman Dunbar |
| Autore | Dunbar Norman |
| Edizione | [2nd ed. 2024.] |
| Pubbl/distr/stampa | Berkeley, CA : , : Apress : , : Imprint : Apress, , 2024 |
| Descrizione fisica | 1 online resource (393 pages) |
| Disciplina | 006.2/2 |
| Collana | Maker Innovations Series |
| Soggetto topico |
Makerspaces
Compilers (Computer programs) Operating systems (Computers) Maker Compilers and Interpreters Operating Systems |
| ISBN | 9798868801716 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1. Introduction -- Chapter 2. Arduino Compilation -- Chapter 3. Arduino Language Reference.-Chapter 4. Arduino Classes -- Chapter 5. Converting to the AVR Language -- Chapter 6. Alternatives to the Arduino IDE -- Chapter 7. ATmega328P Configuration and Management.-Chapter 8. ATmega328P Hardware - Timers and Counters -- Chapter 9. ATmega328P Hardware - ADC and USART -- Appendix A: Arduino Paths -- Appendix B: ATmega328P Pinout -- Appendix C: ATmega328P Power Restrictions -- Appendix D: Predefined Settings -- Appendix E: ADC Temperature Conversion -- Appendix F: Assembly Language - Briefly -- Appendix G: Smallest Blink Sketch? -- Appendix H: NormDuino -- Appendix I: No ICSP? No Problem! -- Appendix J: Breadboard 8MHz Board Setup -- Appendix K: AVRAssist. |
| Record Nr. | UNINA-9910869163503321 |
Dunbar Norman
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| Berkeley, CA : , : Apress : , : Imprint : Apress, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded SoPC design with NIOS II processor and Verilog examples [[electronic resource] /] / Pong P. Chu
| Embedded SoPC design with NIOS II processor and Verilog examples [[electronic resource] /] / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2012 |
| Descrizione fisica | 1 online resource (783 p.) |
| Disciplina | 006.2/2 |
| Soggetto topico |
Embedded computer systems
Field programmable gate arrays Verilog (Computer hardware description language) |
| ISBN |
1-280-59239-7
9786613622228 1-118-30957-X 1-118-30972-3 1-118-30946-4 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | pt. I. Basic digital circuits development -- pt. II. Basic NIOS II software development -- pt. III. Custom I/O peripheral development -- pt. IV. Hardware accelerator case studies. |
| Record Nr. | UNINA-9910139089603321 |
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Chu Pong P. <1959->
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| Hoboken, N.J., : Wiley, c2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded SoPC design with NIOS II processor and Verilog examples / / Pong P. Chu
| Embedded SoPC design with NIOS II processor and Verilog examples / / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2012 |
| Descrizione fisica | 1 online resource (783 p.) |
| Disciplina | 006.2/2 |
| Soggetto topico |
Embedded computer systems
Field programmable gate arrays Verilog (Computer hardware description language) |
| ISBN |
1-280-59239-7
9786613622228 1-118-30957-X 1-118-30972-3 1-118-30946-4 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | pt. I. Basic digital circuits development -- pt. II. Basic NIOS II software development -- pt. III. Custom I/O peripheral development -- pt. IV. Hardware accelerator case studies. |
| Altri titoli varianti | Embedded system on a programmable chip design with Nios II processor and Verilog examples |
| Record Nr. | UNINA-9910822030103321 |
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Chu Pong P. <1959->
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| Hoboken, N.J., : Wiley, c2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded systems [[electronic resource] ] : hardware, design, and implementation / / edited by Krzysztof Iniewski
| Embedded systems [[electronic resource] ] : hardware, design, and implementation / / edited by Krzysztof Iniewski |
| Pubbl/distr/stampa | Hoboken, N.J., : John Wiley & Sons, Inc., 2013 |
| Descrizione fisica | 1 online resource (387 p.) |
| Disciplina | 006.2/2 |
| Altri autori (Persone) | IniewskiKrzysztof |
| Soggetto topico | Embedded computer systems |
| ISBN |
1-118-46865-1
1-283-73564-4 1-118-46861-9 |
| Classificazione | TEC008070 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Title page; Copyright page; Contents; Preface; Contributors; 1: Low Power Multicore Processors for Embedded Systems; 1.1 Multicore Chip with Highly Efficient Cores; 1.2 SuperHTM RISC Engine Family (SH) Processor Cores; 1.2.1 History of SH Processor Cores; 1.2.2 Highly Efficient ISA; 1.2.3 Asymmetric In-Order Dual-Issue Superscalar Architecture; 1.3 SH-X: A Highly Efficient CPU Core; 1.3.1 Microarchitecture Selections; 1.3.2 Improved Superpipeline Structure; 1.3.3 Branch Prediction and Out-of-Order Branch Issue; 1.3.4 Low Power Technologies; 1.3.5 Performance and Efficiency Evaluations
1.4 SH-X FPU: A Highly Efficient FPU1.4.1 FPU Architecture of SH Processors; 1.4.2 Implementation of SH-X FPU; 1.4.3 Performance Evaluations with 3D Graphics Benchmark; 1.5 SH-X2: Frequency and Efficiency Enhanced Core; 1.5.1 Frequency Enhancement; 1.5.2 Low Power Technologies; 1.6 SH-X3: Multicore Architecture Extension; 1.6.1 SH-X3 Core Specifications; 1.6.2 Symmetric and Asymmetric Multiprocessor Support; 1.6.3 Core Snoop Sequence Optimization; 1.6.4 Dynamic Power Management; 1.6.5 RP-1 Prototype Chip; 1.6.6 RP-2 Prototype Chip; 1.7 SH-X4: ISA and Address Space Extension 1.7.1 SH-X4 Core Specifications1.7.2 Efficient ISA Extension; 1.7.3 Address Space Extension; 1.7.4 Data Transfer Unit; 1.7.5 RP-X Prototype Chip; References; 2: Special-Purpose Hardware for Computational Biology; 2.1 Molecular Dynamics Simulations on Graphics Processing Units; 2.1.1 Molecular Mechanics Force Fields; 2.1.2 Graphics Processing Units for MD Simulations; 2.2 Special-Purpose Hardware and Network Topologies for MD Simulations; 2.2.1 High-Throughput Interaction Subsystem; 2.2.2 Hardware Description of the Flexible Subsystem; 2.2.3 Performance and Conclusions 2.3 Quantum MC Applications on Field-Programmable Gate Arrays2.3.1 Energy Computation and WF Kernels; 2.3.2 Hardware Architecture; 2.3.3 PE and WF Computation Kernels; 2.4 Conclusions and Future Directions; References; 3: Embedded GPU Design; 3.1 Introduction; 3.2 System Architecture; 3.3 Graphics Modules Design; 3.3.1 RISC Processor; 3.3.2 Geometry Processor; 3.3.3 Rendering Engine; 3.4 System Power Management; 3.4.1 Multiple Power-Domain Management; 3.4.2 Power Management Unit; 3.5 Implementation Results; 3.5.1 Chip Implementation; 3.5.2 Comparisons; 3.6 Conclusion; References 4: Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors4.1 Introduction; 4.2 The DVP Interface; 4.3 The iBRIDGE-BB Architecture; 4.3.1 Configuring the iBRIDGE-BB; 4.3.2 Operation of the iBRIDGE-BB; 4.3.3 Description of Internal Blocks; 4.4 Hardware Implementation; 4.4.1 Verification in Field-Programmable Gate Array; 4.4.2 Application in Image Compression; 4.4.3 Application-Specific Integrated Circuit (ASIC) Synthesis and Performance Analysis; 4.5 Conclusion; Acknowledgments; References; 5: Embedded Computing Systems on FPGAs; 5.1 FPGA Architecture 5.2 FPGA Configuration Technology |
| Record Nr. | UNINA-9910141415403321 |
| Hoboken, N.J., : John Wiley & Sons, Inc., 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded systems : hardware, design, and implementation / / edited by Krzysztof Iniewski
| Embedded systems : hardware, design, and implementation / / edited by Krzysztof Iniewski |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Hoboken, N.J., : John Wiley & Sons, Inc., 2013 |
| Descrizione fisica | 1 online resource (387 p.) |
| Disciplina | 006.2/2 |
| Altri autori (Persone) | IniewskiKrzysztof |
| Soggetto topico | Embedded computer systems |
| ISBN |
1-118-46865-1
1-283-73564-4 1-118-46861-9 |
| Classificazione | TEC008070 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Title page; Copyright page; Contents; Preface; Contributors; 1: Low Power Multicore Processors for Embedded Systems; 1.1 Multicore Chip with Highly Efficient Cores; 1.2 SuperHTM RISC Engine Family (SH) Processor Cores; 1.2.1 History of SH Processor Cores; 1.2.2 Highly Efficient ISA; 1.2.3 Asymmetric In-Order Dual-Issue Superscalar Architecture; 1.3 SH-X: A Highly Efficient CPU Core; 1.3.1 Microarchitecture Selections; 1.3.2 Improved Superpipeline Structure; 1.3.3 Branch Prediction and Out-of-Order Branch Issue; 1.3.4 Low Power Technologies; 1.3.5 Performance and Efficiency Evaluations
1.4 SH-X FPU: A Highly Efficient FPU1.4.1 FPU Architecture of SH Processors; 1.4.2 Implementation of SH-X FPU; 1.4.3 Performance Evaluations with 3D Graphics Benchmark; 1.5 SH-X2: Frequency and Efficiency Enhanced Core; 1.5.1 Frequency Enhancement; 1.5.2 Low Power Technologies; 1.6 SH-X3: Multicore Architecture Extension; 1.6.1 SH-X3 Core Specifications; 1.6.2 Symmetric and Asymmetric Multiprocessor Support; 1.6.3 Core Snoop Sequence Optimization; 1.6.4 Dynamic Power Management; 1.6.5 RP-1 Prototype Chip; 1.6.6 RP-2 Prototype Chip; 1.7 SH-X4: ISA and Address Space Extension 1.7.1 SH-X4 Core Specifications1.7.2 Efficient ISA Extension; 1.7.3 Address Space Extension; 1.7.4 Data Transfer Unit; 1.7.5 RP-X Prototype Chip; References; 2: Special-Purpose Hardware for Computational Biology; 2.1 Molecular Dynamics Simulations on Graphics Processing Units; 2.1.1 Molecular Mechanics Force Fields; 2.1.2 Graphics Processing Units for MD Simulations; 2.2 Special-Purpose Hardware and Network Topologies for MD Simulations; 2.2.1 High-Throughput Interaction Subsystem; 2.2.2 Hardware Description of the Flexible Subsystem; 2.2.3 Performance and Conclusions 2.3 Quantum MC Applications on Field-Programmable Gate Arrays2.3.1 Energy Computation and WF Kernels; 2.3.2 Hardware Architecture; 2.3.3 PE and WF Computation Kernels; 2.4 Conclusions and Future Directions; References; 3: Embedded GPU Design; 3.1 Introduction; 3.2 System Architecture; 3.3 Graphics Modules Design; 3.3.1 RISC Processor; 3.3.2 Geometry Processor; 3.3.3 Rendering Engine; 3.4 System Power Management; 3.4.1 Multiple Power-Domain Management; 3.4.2 Power Management Unit; 3.5 Implementation Results; 3.5.1 Chip Implementation; 3.5.2 Comparisons; 3.6 Conclusion; References 4: Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors4.1 Introduction; 4.2 The DVP Interface; 4.3 The iBRIDGE-BB Architecture; 4.3.1 Configuring the iBRIDGE-BB; 4.3.2 Operation of the iBRIDGE-BB; 4.3.3 Description of Internal Blocks; 4.4 Hardware Implementation; 4.4.1 Verification in Field-Programmable Gate Array; 4.4.2 Application in Image Compression; 4.4.3 Application-Specific Integrated Circuit (ASIC) Synthesis and Performance Analysis; 4.5 Conclusion; Acknowledgments; References; 5: Embedded Computing Systems on FPGAs; 5.1 FPGA Architecture 5.2 FPGA Configuration Technology |
| Record Nr. | UNINA-9910819603603321 |
| Hoboken, N.J., : John Wiley & Sons, Inc., 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Introduction to embedded systems : a cyber-physical systems approach / / Edward Ashford Lee and Sanjit Arunkumar Seshia
| Introduction to embedded systems : a cyber-physical systems approach / / Edward Ashford Lee and Sanjit Arunkumar Seshia |
| Autore | Lee Edward A. <1957-> |
| Pubbl/distr/stampa | The MIT Press Open |
| Disciplina | 006.2/2 |
| Soggetto topico | Embedded computer systems |
| ISBN | 0-262-53381-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996437054003316 |
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Lee Edward A. <1957->
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| The MIT Press Open | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Introduction to embedded systems : a cyber-physical systems approach / / Edward Ashford Lee and Sanjit Arunkumar Seshia
| Introduction to embedded systems : a cyber-physical systems approach / / Edward Ashford Lee and Sanjit Arunkumar Seshia |
| Autore | Lee Edward A. <1957-> |
| Pubbl/distr/stampa | The MIT Press Open |
| Disciplina | 006.2/2 |
| Soggetto topico | Embedded computer systems |
| ISBN | 0-262-53381-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910765887703321 |
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Lee Edward A. <1957->
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| The MIT Press Open | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Model-based design of adaptive embedded systems / / Twan Basten ... [et al.], editors
| Model-based design of adaptive embedded systems / / Twan Basten ... [et al.], editors |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | New York, NY, : Springer, c2013 |
| Descrizione fisica | 1 online resource (xiii, 306 pages) : illustrations (some color) |
| Disciplina | 006.2/2 |
| Altri autori (Persone) | BastenTwan |
| Collana | Embedded systems |
| Soggetto topico |
Embedded computer systems - Design and construction
Adaptive control systems |
| ISBN |
1-299-40753-6
1-4614-4821-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Adaptivity in Professional Printing Systems -- Aspects of Adaptive Systems Engineering: A Professional Printing Case -- Piezo Printhead Control: Jetting Any Drop at Any Time -- Adaptive Strategies for Productive Toner Printers -- Reasoning with Uncertainty about System Behaviour: Making Printing Systems Adaptive -- Supporting the Architecting Process of Adaptable Systems -- Model-Driven Design-Space Exploration for Software-Intensive Embedded Systems -- Engineering Embedded Software: Managing Complexity and Evolution -- Reflections on the Octopus Project. |
| Record Nr. | UNINA-9910438039803321 |
| New York, NY, : Springer, c2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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