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2014 International Conference on the Internet of Things (IOT 2014) : : Cambridge, Massachusetts, USA 6-8 October 2014
| 2014 International Conference on the Internet of Things (IOT 2014) : : Cambridge, Massachusetts, USA 6-8 October 2014 |
| Pubbl/distr/stampa | IEEE |
| Disciplina | 006.2/2 |
| Soggetto topico |
Ubiquitous computing
Embedded Internet devices Wireless communication systems Ambient intelligence Interactive computer systems Sensor networks Radio frequency identification systems Internet |
| ISBN | 1-4799-5154-4 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
2014 International Conference on the Internet of Things
Internet of Things |
| Record Nr. | UNISA-996280404003316 |
| IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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2014 International Conference on the Internet of Things (IOT 2014) : : Cambridge, Massachusetts, USA 6-8 October 2014
| 2014 International Conference on the Internet of Things (IOT 2014) : : Cambridge, Massachusetts, USA 6-8 October 2014 |
| Pubbl/distr/stampa | IEEE |
| Disciplina | 006.2/2 |
| Soggetto topico |
Ubiquitous computing
Embedded Internet devices Wireless communication systems Ambient intelligence Interactive computer systems Sensor networks Radio frequency identification systems Internet |
| ISBN |
9781479951543
1479951544 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
2014 International Conference on the Internet of Things
Internet of Things |
| Record Nr. | UNINA-9910132685003321 |
| IEEE | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Arduino Software Internals : A Complete Guide to How Your Arduino Language and Hardware Work Together / / by Norman Dunbar
| Arduino Software Internals : A Complete Guide to How Your Arduino Language and Hardware Work Together / / by Norman Dunbar |
| Autore | Dunbar Norman |
| Edizione | [2nd ed. 2024.] |
| Pubbl/distr/stampa | Berkeley, CA : , : Apress : , : Imprint : Apress, , 2024 |
| Descrizione fisica | 1 online resource (393 pages) |
| Disciplina | 006.2/2 |
| Collana | Maker Innovations Series |
| Soggetto topico |
Makerspaces
Compilers (Computer programs) Operating systems (Computers) Maker Compilers and Interpreters Operating Systems |
| ISBN | 9798868801716 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1. Introduction -- Chapter 2. Arduino Compilation -- Chapter 3. Arduino Language Reference.-Chapter 4. Arduino Classes -- Chapter 5. Converting to the AVR Language -- Chapter 6. Alternatives to the Arduino IDE -- Chapter 7. ATmega328P Configuration and Management.-Chapter 8. ATmega328P Hardware - Timers and Counters -- Chapter 9. ATmega328P Hardware - ADC and USART -- Appendix A: Arduino Paths -- Appendix B: ATmega328P Pinout -- Appendix C: ATmega328P Power Restrictions -- Appendix D: Predefined Settings -- Appendix E: ADC Temperature Conversion -- Appendix F: Assembly Language - Briefly -- Appendix G: Smallest Blink Sketch? -- Appendix H: NormDuino -- Appendix I: No ICSP? No Problem! -- Appendix J: Breadboard 8MHz Board Setup -- Appendix K: AVRAssist. |
| Record Nr. | UNINA-9910869163503321 |
Dunbar Norman
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| Berkeley, CA : , : Apress : , : Imprint : Apress, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded SoPC design with NIOS II processor and Verilog examples [[electronic resource] /] / Pong P. Chu
| Embedded SoPC design with NIOS II processor and Verilog examples [[electronic resource] /] / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2012 |
| Descrizione fisica | 1 online resource (783 p.) |
| Disciplina | 006.2/2 |
| Soggetto topico |
Embedded computer systems
Field programmable gate arrays Verilog (Computer hardware description language) |
| ISBN |
1-280-59239-7
9786613622228 1-118-30957-X 1-118-30972-3 1-118-30946-4 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | pt. I. Basic digital circuits development -- pt. II. Basic NIOS II software development -- pt. III. Custom I/O peripheral development -- pt. IV. Hardware accelerator case studies. |
| Record Nr. | UNINA-9910139089603321 |
|
Chu Pong P. <1959->
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| Hoboken, N.J., : Wiley, c2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded SoPC design with NIOS II processor and Verilog examples / / Pong P. Chu
| Embedded SoPC design with NIOS II processor and Verilog examples / / Pong P. Chu |
| Autore | Chu Pong P. <1959-> |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, c2012 |
| Descrizione fisica | 1 online resource (783 p.) |
| Disciplina | 006.2/2 |
| Soggetto topico |
Embedded computer systems
Field programmable gate arrays Verilog (Computer hardware description language) |
| ISBN |
9786613622228
9781280592393 1280592397 9781118309575 111830957X 9781118309728 1118309723 9781118309469 1118309464 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | pt. I. Basic digital circuits development -- pt. II. Basic NIOS II software development -- pt. III. Custom I/O peripheral development -- pt. IV. Hardware accelerator case studies. |
| Altri titoli varianti | Embedded system on a programmable chip design with Nios II processor and Verilog examples |
| Record Nr. | UNINA-9910822030103321 |
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Chu Pong P. <1959->
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| Hoboken, N.J., : Wiley, c2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded systems [[electronic resource] ] : hardware, design, and implementation / / edited by Krzysztof Iniewski
| Embedded systems [[electronic resource] ] : hardware, design, and implementation / / edited by Krzysztof Iniewski |
| Pubbl/distr/stampa | Hoboken, N.J., : John Wiley & Sons, Inc., 2013 |
| Descrizione fisica | 1 online resource (387 p.) |
| Disciplina | 006.2/2 |
| Altri autori (Persone) | IniewskiKrzysztof |
| Soggetto topico | Embedded computer systems |
| ISBN |
1-118-46865-1
1-283-73564-4 1-118-46861-9 |
| Classificazione | TEC008070 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Title page; Copyright page; Contents; Preface; Contributors; 1: Low Power Multicore Processors for Embedded Systems; 1.1 Multicore Chip with Highly Efficient Cores; 1.2 SuperHTM RISC Engine Family (SH) Processor Cores; 1.2.1 History of SH Processor Cores; 1.2.2 Highly Efficient ISA; 1.2.3 Asymmetric In-Order Dual-Issue Superscalar Architecture; 1.3 SH-X: A Highly Efficient CPU Core; 1.3.1 Microarchitecture Selections; 1.3.2 Improved Superpipeline Structure; 1.3.3 Branch Prediction and Out-of-Order Branch Issue; 1.3.4 Low Power Technologies; 1.3.5 Performance and Efficiency Evaluations
1.4 SH-X FPU: A Highly Efficient FPU1.4.1 FPU Architecture of SH Processors; 1.4.2 Implementation of SH-X FPU; 1.4.3 Performance Evaluations with 3D Graphics Benchmark; 1.5 SH-X2: Frequency and Efficiency Enhanced Core; 1.5.1 Frequency Enhancement; 1.5.2 Low Power Technologies; 1.6 SH-X3: Multicore Architecture Extension; 1.6.1 SH-X3 Core Specifications; 1.6.2 Symmetric and Asymmetric Multiprocessor Support; 1.6.3 Core Snoop Sequence Optimization; 1.6.4 Dynamic Power Management; 1.6.5 RP-1 Prototype Chip; 1.6.6 RP-2 Prototype Chip; 1.7 SH-X4: ISA and Address Space Extension 1.7.1 SH-X4 Core Specifications1.7.2 Efficient ISA Extension; 1.7.3 Address Space Extension; 1.7.4 Data Transfer Unit; 1.7.5 RP-X Prototype Chip; References; 2: Special-Purpose Hardware for Computational Biology; 2.1 Molecular Dynamics Simulations on Graphics Processing Units; 2.1.1 Molecular Mechanics Force Fields; 2.1.2 Graphics Processing Units for MD Simulations; 2.2 Special-Purpose Hardware and Network Topologies for MD Simulations; 2.2.1 High-Throughput Interaction Subsystem; 2.2.2 Hardware Description of the Flexible Subsystem; 2.2.3 Performance and Conclusions 2.3 Quantum MC Applications on Field-Programmable Gate Arrays2.3.1 Energy Computation and WF Kernels; 2.3.2 Hardware Architecture; 2.3.3 PE and WF Computation Kernels; 2.4 Conclusions and Future Directions; References; 3: Embedded GPU Design; 3.1 Introduction; 3.2 System Architecture; 3.3 Graphics Modules Design; 3.3.1 RISC Processor; 3.3.2 Geometry Processor; 3.3.3 Rendering Engine; 3.4 System Power Management; 3.4.1 Multiple Power-Domain Management; 3.4.2 Power Management Unit; 3.5 Implementation Results; 3.5.1 Chip Implementation; 3.5.2 Comparisons; 3.6 Conclusion; References 4: Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors4.1 Introduction; 4.2 The DVP Interface; 4.3 The iBRIDGE-BB Architecture; 4.3.1 Configuring the iBRIDGE-BB; 4.3.2 Operation of the iBRIDGE-BB; 4.3.3 Description of Internal Blocks; 4.4 Hardware Implementation; 4.4.1 Verification in Field-Programmable Gate Array; 4.4.2 Application in Image Compression; 4.4.3 Application-Specific Integrated Circuit (ASIC) Synthesis and Performance Analysis; 4.5 Conclusion; Acknowledgments; References; 5: Embedded Computing Systems on FPGAs; 5.1 FPGA Architecture 5.2 FPGA Configuration Technology |
| Record Nr. | UNINA-9910141415403321 |
| Hoboken, N.J., : John Wiley & Sons, Inc., 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded systems : hardware, design, and implementation / / edited by Krzysztof Iniewski
| Embedded systems : hardware, design, and implementation / / edited by Krzysztof Iniewski |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Hoboken, N.J., : John Wiley & Sons, Inc., 2013 |
| Descrizione fisica | 1 online resource (387 p.) |
| Disciplina | 006.2/2 |
| Altri autori (Persone) | IniewskiKrzysztof |
| Soggetto topico | Embedded computer systems |
| ISBN |
9781118468654
1118468651 9781283735643 1283735644 9781118468616 1118468619 |
| Classificazione | TEC008070 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Title page; Copyright page; Contents; Preface; Contributors; 1: Low Power Multicore Processors for Embedded Systems; 1.1 Multicore Chip with Highly Efficient Cores; 1.2 SuperHTM RISC Engine Family (SH) Processor Cores; 1.2.1 History of SH Processor Cores; 1.2.2 Highly Efficient ISA; 1.2.3 Asymmetric In-Order Dual-Issue Superscalar Architecture; 1.3 SH-X: A Highly Efficient CPU Core; 1.3.1 Microarchitecture Selections; 1.3.2 Improved Superpipeline Structure; 1.3.3 Branch Prediction and Out-of-Order Branch Issue; 1.3.4 Low Power Technologies; 1.3.5 Performance and Efficiency Evaluations
1.4 SH-X FPU: A Highly Efficient FPU1.4.1 FPU Architecture of SH Processors; 1.4.2 Implementation of SH-X FPU; 1.4.3 Performance Evaluations with 3D Graphics Benchmark; 1.5 SH-X2: Frequency and Efficiency Enhanced Core; 1.5.1 Frequency Enhancement; 1.5.2 Low Power Technologies; 1.6 SH-X3: Multicore Architecture Extension; 1.6.1 SH-X3 Core Specifications; 1.6.2 Symmetric and Asymmetric Multiprocessor Support; 1.6.3 Core Snoop Sequence Optimization; 1.6.4 Dynamic Power Management; 1.6.5 RP-1 Prototype Chip; 1.6.6 RP-2 Prototype Chip; 1.7 SH-X4: ISA and Address Space Extension 1.7.1 SH-X4 Core Specifications1.7.2 Efficient ISA Extension; 1.7.3 Address Space Extension; 1.7.4 Data Transfer Unit; 1.7.5 RP-X Prototype Chip; References; 2: Special-Purpose Hardware for Computational Biology; 2.1 Molecular Dynamics Simulations on Graphics Processing Units; 2.1.1 Molecular Mechanics Force Fields; 2.1.2 Graphics Processing Units for MD Simulations; 2.2 Special-Purpose Hardware and Network Topologies for MD Simulations; 2.2.1 High-Throughput Interaction Subsystem; 2.2.2 Hardware Description of the Flexible Subsystem; 2.2.3 Performance and Conclusions 2.3 Quantum MC Applications on Field-Programmable Gate Arrays2.3.1 Energy Computation and WF Kernels; 2.3.2 Hardware Architecture; 2.3.3 PE and WF Computation Kernels; 2.4 Conclusions and Future Directions; References; 3: Embedded GPU Design; 3.1 Introduction; 3.2 System Architecture; 3.3 Graphics Modules Design; 3.3.1 RISC Processor; 3.3.2 Geometry Processor; 3.3.3 Rendering Engine; 3.4 System Power Management; 3.4.1 Multiple Power-Domain Management; 3.4.2 Power Management Unit; 3.5 Implementation Results; 3.5.1 Chip Implementation; 3.5.2 Comparisons; 3.6 Conclusion; References 4: Low-Cost VLSI Architecture for Random Block-Based Access of Pixels in Modern Image Sensors4.1 Introduction; 4.2 The DVP Interface; 4.3 The iBRIDGE-BB Architecture; 4.3.1 Configuring the iBRIDGE-BB; 4.3.2 Operation of the iBRIDGE-BB; 4.3.3 Description of Internal Blocks; 4.4 Hardware Implementation; 4.4.1 Verification in Field-Programmable Gate Array; 4.4.2 Application in Image Compression; 4.4.3 Application-Specific Integrated Circuit (ASIC) Synthesis and Performance Analysis; 4.5 Conclusion; Acknowledgments; References; 5: Embedded Computing Systems on FPGAs; 5.1 FPGA Architecture 5.2 FPGA Configuration Technology |
| Record Nr. | UNINA-9910819603603321 |
| Hoboken, N.J., : John Wiley & Sons, Inc., 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Embedded Systems with .NET nanoFramework : Practical, Hands-On C# for Microcontrollers: Building Resource-Constrained IoT Devices from Peripherals to CloudMaster / / by José Simões
| Embedded Systems with .NET nanoFramework : Practical, Hands-On C# for Microcontrollers: Building Resource-Constrained IoT Devices from Peripherals to CloudMaster / / by José Simões |
| Autore | Simoes Jose |
| Edizione | [1st ed. 2025.] |
| Pubbl/distr/stampa | Berkeley, CA : , : Apress : , : Imprint : Apress, , 2025 |
| Descrizione fisica | 1 online resource (280 pages) |
| Disciplina | 006.2/2 |
| Collana | Professional and Applied Computing Series |
| Soggetto topico |
Microsoft software
Microsoft .NET Framework Internet of things Software engineering Microsoft Internet of Things Software Engineering |
| ISBN | 979-88-6882-096-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1: Origins and Initial Concept -- Chapter 2: Architecture -- Chapter 3: The Build System -- Chapter 4: Being Part of the .NET Ecosystem -- Chapter 5: Interfacing with the Outside World -- Chapter 6: An IoT Embedded Device -- Chapter 7: Nano Devices Big-Time Connectivity -- Chapter 8: Testing for Embedded Success -- Chapter 9: Advanced Coding Topics -- Chapter 10: Beyond Connectivity - MCP in Embedded Devices. |
| Record Nr. | UNINA-9911049147703321 |
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Simoes Jose
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| Berkeley, CA : , : Apress : , : Imprint : Apress, , 2025 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Integrated Systems : Embedded, Signal Processing, and Communication
| Integrated Systems : Embedded, Signal Processing, and Communication |
| Autore | Gudipalli Abhishek |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Newark : , : John Wiley & Sons, Incorporated, , 2026 |
| Descrizione fisica | 1 online resource (612 pages) |
| Disciplina | 006.2/2 |
| Soggetto topico | Embedded computer systems |
| ISBN |
1-394-31176-1
1-394-31175-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover -- Series Page -- Title Page -- Copyright Page -- Contents -- Preface -- Chapter 1 Integration of Industrial Robots to Enhance Warehouse Efficiency in an Industry 4.0 Environment Using Digital Twin Technology -- Abbreviations -- 1.1 Introduction -- 1.2 Industry Internet of Things and Robot Applications in Warehouse -- 1.3 Programming Using CODESYS V3.5 SP19 -- 1.4 Creation of Warehouse in Factory IO -- 1.5 Sequential Function Chart Programming Using CODESYS V3.5 -- 1.6 Conclusions -- Bibliography -- Chapter 2 QR Code-Enabled Anytime Pill Dispenser -- 2.1 Introduction -- 2.2 Literature Review -- 2.3 Methodology -- 2.3.1 Hardware Requirements -- 2.3.2 Workflow -- 2.4 Results and Discussions -- 2.4.1 System Initialization -- 2.4.2 QR Code Scanning -- 2.5 Conclusion -- References -- Chapter 3 Analysis on Insulation Properties of Carbon Quantum Dots-SiO2 Oil Fillers in Mineral Oil -- 3.1 Introduction -- 3.2 Experimental Arrangement and Preparation Method -- 3.2.1 Preparation of Nanofluid -- 3.2.2 AC Breakdown Voltage Test -- 3.2.3 Tan Delta and Volume Resistivity Test -- 3.3 Results and Discussion -- 3.4 Conclusion -- Bibliography -- Chapter 4 Comparative Analysis of Partial Discharge Characteristics in Different Electrode Configurations of Biodegradable Nanofluid -- 4.1 Introduction -- 4.2 Sample and Procedure for Test -- 4.2.1 Mixture of Test Solution and Nanofluids -- 4.2.2 Test Arrangements and Procedures -- 4.3 Test Results and Analysis -- 4.3.1 Partial Discharge Magnitude and Its Inception -- 4.4 Conclusion -- References -- Chapter 5 Cost-Effective Real-Time Facial Recognition and Database Integration Using Firebase -- 5.1 Introduction -- 5.2 Literature Review -- 5.2.1 Overview of Facial Recognition Techniques -- 5.2.2 Existing Systems and Technologies -- 5.2.3 Applications of Facial Recognition in Various Fields.
5.2.3.1 Education Attendance Monitoring -- 5.2.3.2 Exam Proctoring -- 5.2.3.3 Financial Services and Banking Secure Transactions -- 5.2.3.4 Fraud Prevention -- 5.2.3.5 Healthcare Patient Identification -- 5.2.3.6 Emotion Detection -- 5.2.3.7 Safety and Monitoring -- 5.2.3.8 Access Control -- 5.2.3.9 Border Control -- 5.3 Methodology -- 5.4 Implementation -- 5.4.1 Real-Time Facial Recognition System -- 5.4.2 Face Encoding Generation Script -- 5.4.3 Database Initialization Script -- 5.5 Conclusion -- References -- Chapter 6 Remote Light Monitoring for Energy Efficiency -- 6.1 Introduction -- 6.2 Methodology -- 6.3 Design Approach -- 6.4 Results -- 6.4.1 Cost Analysis -- 6.5 Conclusion -- References -- Chapter 7 Buffer for Critical Path VLSI Circuits -- 7.1 Introduction -- 7.2 Conventional Buffer -- 7.3 Schematic Design of the Proposed Buffer -- 7.4 Results and Discussions -- 7.4.1 Scaling of Voltage and Load -- 7.4.1.1 Delay Due to Scaling of Voltage and Load -- 7.4.1.2 Power Dissipation for Scaling of Voltage and Load -- 7.4.2 Scaling the Technology Node -- 7.5 Conclusion -- References -- Chapter 8 Fuzzy Logic-Based Navigation Control for Khepera Robot -- 8.1 Introduction -- 8.1.1 Scope and Limitations -- 8.2 Research Methodology -- 8.2.1 Environment Modeling -- 8.2.2 Robot Modeling -- 8.2.3 Fuzzy Logic Controller Design -- 8.2.4 Simulation-Based -- 8.3 Results and Discussions -- 8.3.1 Fuzzy System Inputs and Outputs -- 8.3.2 Khepera's Trajectory -- 8.3.3 Khepera's Performances with Fuzzy and without Fuzzy Controller -- 8.4 Conclusions -- References -- Chapter 9 Detection and Recurrence of Breast Cancer Through Image Processing and Attention Awareness: A Comparative Analysis of Algorithms -- 9.1 Introduction -- 9.2 Literature Review -- 9.3 System Implementation -- 9.4 Results and Discussion -- 9.5 Conclusion -- References. Chapter 10 Transformative Innovations in Tomato Plant Disease Detection: A Comprehensive Examination of Advanced Sensing Technologies and Algorithmic Precision -- 10.1 Introduction -- 10.2 Problem Statement -- 10.3 Related Works -- 10.4 Materials and Methods -- 10.4.1 Architecture -- 10.4.2 Algorithm -- 10.4.3 Mathematics -- 10.4.3.1 Intersection Over Union -- 10.4.3.2 Average Precision -- 10.4.4 Implementation -- 10.4.5 Dataset -- 10.5 Experiments and Results -- 10.5.1 Test Bench -- 10.5.2 Test Case -- 10.5.3 Benchmarking -- 10.5.4 Results -- 10.6 Conclusion -- References -- Chapter 11 Triples, Helmet, Number Plate Design On Real-Time Information System -- Introduction -- Abbreviations -- Proposed System -- Models Implemented -- Advanced Picture Handling Includes a Few Major Advances -- Picture Compression -- Image Compression Types -- Compression Ratio -- Image Lossy Compression -- Lossless Image Input -- Experimental Results -- Limitations -- Future Works -- Conclusion -- References -- Chapter 12 Brain Tumor Segmentation Using U-Net, U-Net with Attention, and ResNeXt50 -- 12.1 Introduction -- 12.2 Dataset Description -- 12.2.1 MRI Images -- 12.2.2 Manual FLAIR Abnormality Segmentation Masks -- 12.2.3 Patient Information -- 12.2.4 Purpose -- 12.2.5 Availability -- 12.3 Methodology -- 12.3.1 Data Preprocessing -- 12.3.2 Data Augmentation and Transformations -- 12.3.3 Algorithm Selection -- 12.4 Segmentation Quality Metrics and Loss Functions -- 12.4.1 Segmentation Quality Metric -- 12.4.2 Segmentation Loss Function -- 12.5 Training Procedure -- 12.5.1 Model Training and Optimization -- 12.5.2 Test Performance Evaluation -- 12.6 Test Results and Visualization -- 12.7 Performance Evaluation of Segmentation Models -- 12.8 Discussion -- 12.8.1 Model Performance Comparison -- 12.8.2 Architectural Advantages. 12.8.3 Training Strategy and Data Augmentation -- 12.9 Future Scope -- 12.10 Conclusion -- Acknowledgment -- References -- Chapter 13 Skin Disease Classification for Healthcare Using a Federated Learning-Based Ensemble Learning -- 13.1 Introduction -- 13.2 Literature Review -- 13.3 Dataset and Methodology -- 13.4 Results and Discussion -- 13.5 Conclusion -- References -- Chapter 14 Fingerprint Recognition Using Image Processing and Neural Networks -- 14.1 Introduction -- 14.2 Related Works -- 14.3 Proposed Methodology -- 14.4 Results and Discussion -- 14.5 Methodology Comparison -- 14.6 Conclusion and Future Work -- Bibliography -- Chapter 15 Machine Learning Algorithms to Predict and Detect Malicious Network Traffic and Cyberattacks -- Introduction -- Literature Review -- Proposed Methodologies -- Algorithms Used -- Decision Tree Algorithm -- XGBoost Algorithm -- Performance Metrics -- Confusion Matrix -- Results and Output -- Conclusion -- References -- Chapter 16 Machine Learning-Based Term Retrieval Method for Text Extraction from Emojipedia -- 16.1 Introduction -- 16.2 Related Works -- 16.3 Proposed Methodology -- 16.3.1 Preprocessing -- 16.3.2 Feature Extraction -- 16.3.3 Automated Term-Based Retrieval Method -- 16.3.4 Stemming -- 16.3.5 Stop Words -- 16.3.6 Feature Extraction-Term Frequency-IDF -- 16.4 Result and Discussion -- 16.5 Conclusion -- Bibliography -- Chapter 17 Experimentations on Eulerian Video Magnification -- 17.1 Introduction -- 17.2 Related Works -- 17.3 Methodology -- 17.3.1 Video Acquisition -- 17.3.2 Spatial Decomposition -- 17.3.3 Time Domain Filtering -- 17.3.4 Amplification Filtering -- 17.3.5 Synthesized Images -- 17.4 Experiments -- 17.4.1 Video Acquisition -- 17.4.1.1 Methods -- 17.5 Results -- 17.5.1 Horizontal Vibration Video -- 17.5.2 Vertical Vibration Video -- 17.6 Discussion -- 17.6.1 Significance of Findings. 17.6.2 Challenges Encountered -- 17.6.3 Noise Amplification -- 17.6.4 Artifact Introduction -- 17.6.5 Computational Efficiency -- 17.6.6 Potential Applications -- 17.6.6.1 Medical Diagnostics -- 17.6.6.2 Structural Health Monitoring -- 17.6.6.3 Video Forensics -- 17.6.6.4 Materials Science -- 17.6.7 Future Research Directions -- 17.6.7.1 Advanced Noise Reduction Techniques -- 17.6.7.2 Artifact Minimization -- 17.6.7.3 Real-Time Processing -- 17.6.7.4 Application-Specific Customization -- 17.6.7.5 Extended Validation -- 17.7 Conclusion -- Data Availability -- References -- Chapter 18 Predictive Modeling for Early Detection of Mental Health Crisis Among Employees -- 18.1 Introduction -- 18.2 Related Works -- 18.3 Methodology and Model Development -- 18.3.1 Mental Health Prediction Models -- 18.3.2 Logistic Regression -- 18.3.3 K-Nearest Neighbors -- 18.3.4 Decision Tree Classifier -- 18.3.5 Random Forest -- 18.3.6 Bagging (Bootstrap Aggregating) -- 18.3.7 Boosting -- 18.3.8 Stacking -- 18.3.9 Data Collection and Preprocessing Methods -- 18.4 Evaluation Methodologies -- 18.4.1 Comparison with Baseline Methods -- 18.4.2 Model Performance -- 18.4.3 Challenges and Solutions -- 18.4.4 Limited Access to Large and High-Quality Datasets -- 18.4.5 Feature Selection -- 18.4.6 Class Imbalance -- 18.4.7 Model Overfitting -- 18.5 Conclusion -- References -- Chapter 19 Enhancement of Spatial Resolution with Deep CNN-Based Fusion of Panchromatic-Multispectral Images -- 19.1 Introduction -- 19.2 Literature Survey -- 19.3 Methodology -- 19.3.1 Input Layers -- 19.3.2 Multi-Filter Layer (Edge Filters) -- 19.3.3 Upsampling and Concatenation (C) -- 19.3.4 Convolutional Layers -- 19.3.5 Residual Skip Connection -- 19.3.6 Output Layer -- 19.4 Experimental Results and Analysis -- 19.4.1 Datasets -- 19.4.2 Quantitative Metrics -- 19.4.3 Metrics and Graphs -- 19.5 Conclusion. References. |
| Record Nr. | UNINA-9911046228903321 |
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Gudipalli Abhishek
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| Newark : , : John Wiley & Sons, Incorporated, , 2026 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Introduction to embedded systems : a cyber-physical systems approach / / Edward Ashford Lee and Sanjit Arunkumar Seshia
| Introduction to embedded systems : a cyber-physical systems approach / / Edward Ashford Lee and Sanjit Arunkumar Seshia |
| Autore | Lee Edward A. <1957-> |
| Pubbl/distr/stampa | The MIT Press Open |
| Disciplina | 006.2/2 |
| Soggetto topico | Embedded computer systems |
| ISBN | 0-262-53381-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996437054003316 |
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Lee Edward A. <1957->
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| The MIT Press Open | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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