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2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing / / Institute of Electrical and Electronics Engineers
| 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | [Place of publication not identified] : , : IEEE, , 2014 |
| Descrizione fisica | 1 online resource |
| Disciplina | 005.275 |
| Soggetto topico | Parallel programming (Computer science) |
| ISBN | 1-4799-2729-5 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
2014 22nd Euromicro International Conference on Parallel, Distributed and Network-Based Processing
Parallel, Distributed and Network-Based Processing Parallel, Distributed and Network-Based Processing (PDP), 2014 22nd Euromicro International Conference on |
| Record Nr. | UNINA-9910132528303321 |
| [Place of publication not identified] : , : IEEE, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing / / Institute of Electrical and Electronics Engineers
| 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | [Place of publication not identified] : , : IEEE, , 2014 |
| Descrizione fisica | 1 online resource |
| Disciplina | 005.275 |
| Soggetto topico | Parallel programming (Computer science) |
| ISBN | 1-4799-2729-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti |
2014 22nd Euromicro International Conference on Parallel, Distributed and Network-Based Processing
Parallel, Distributed and Network-Based Processing Parallel, Distributed and Network-Based Processing (PDP), 2014 22nd Euromicro International Conference on |
| Record Nr. | UNISA-996279769603316 |
| [Place of publication not identified] : , : IEEE, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Advanced Polytopic Projects [[electronic resource] /] / by Octavian Iordache
| Advanced Polytopic Projects [[electronic resource] /] / by Octavian Iordache |
| Autore | Iordache Octavian |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (214 pages) : illustrations |
| Disciplina | 005.275 |
| Collana | Lecture Notes in Intelligent Transportation and Infrastructure |
| Soggetto topico |
Computational intelligence
Manufactures Engineering design Control engineering Computational Intelligence Manufacturing, Machines, Tools, Processes Engineering Design Control and Systems Theory |
| ISBN | 3-030-01243-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Polytopic Projects -- Integration and Separation -- Structuring and Restructuring -- Forward and Backward -- Assimilation and Accommodation -- Testing and Designing -- Additive and Subtractive -- Prospection and Retrospection. |
| Record Nr. | UNINA-9910337620503321 |
Iordache Octavian
|
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Algorithmics for hard problems : introduction to combinatorial optimization, randomization, approximation, and heuristics / Juraj Hromkovĭc
| Algorithmics for hard problems : introduction to combinatorial optimization, randomization, approximation, and heuristics / Juraj Hromkovĭc |
| Autore | Hromkovič, Juraj |
| Edizione | [2. ed] |
| Pubbl/distr/stampa | Berlin ; New York : Springer-Verlag, 2003 |
| Descrizione fisica | xiii, 544 p. : ill. ; 24 cm |
| Disciplina | 005.275 |
| Collana | Texts in theoretical computer science |
| Soggetto topico | Programmazione parallela |
| ISBN | 3540441344 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISALENTO-991004064449707536 |
|
Hromkovič, Juraj
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| Berlin ; New York : Springer-Verlag, 2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Salento | ||
| ||
Algorithms and parallel computing [[electronic resource] /] / Fayez Gebali
| Algorithms and parallel computing [[electronic resource] /] / Fayez Gebali |
| Autore | Gebali Fayez |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, 2011 |
| Descrizione fisica | 1 online resource (365 p.) |
| Disciplina |
004.35
004/.35 005.275 |
| Collana | Wiley series on parallel and distributed computing |
| Soggetto topico |
Parallel processing (Electronic computers)
Computer algorithms |
| ISBN |
1-283-02557-4
9786613025579 0-470-93201-5 0-470-93202-3 |
| Classificazione | COM043000 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Algorithms and Parallel Computing; Contents; Preface; List of Acronyms; Chapter 1: Introduction; 1.1 INTRODUCTION; 1.2 TOWARD AUTOMATING PARALLEL PROGRAMMING; 1.3 ALGORITHMS; 1.4 PARALLEL COMPUTING DESIGN CONSIDERATIONS; 1.5 PARALLEL ALGORITHMS AND PARALLEL ARCHITECTURES; 1.6 RELATING PARALLEL ALGORITHM AND PARALLEL ARCHITECTURE; 1.7 IMPLEMENTATION OF ALGORITHMS: A TWO-SIDED PROBLEM; 1.8 MEASURING BENEFITS OF PARALLEL COMPUTING; 1.9 AMDAHL'S LAW FOR MULTIPROCESSOR SYSTEMS; 1.10 GUSTAFSON-BARSIS'S LAW; 1.11 APPLICATIONS OF PARALLEL COMPUTING; Chapter 2: Enhancing Uniprocessor Performance
2.1 INTRODUCTION2.2 INCREASING PROCESSOR CLOCK FREQUENCY; 2.3 PARALLELIZING ALU STRUCTURE; 2.4 USING MEMORY HIERARCHY; 2.5 PIPELINING; 2.6 VERY LONG INSTRUCTION WORD (VLIW) PROCESSORS; 2.7 INSTRUCTION-LEVEL PARALLELISM (ILP) AND SUPERSCALAR PROCESSORS; 2.8 MULTITHREADED PROCESSOR; Chapter 3: Parallel Computers; 3.1 INTRODUCTION; 3.2 PARALLEL COMPUTING; 3.3 SHARED-MEMORY MULTIPROCESSORS (UNIFORM MEMORY ACCESS [UMA]); 3.4 DISTRIBUTED-MEMORY MULTIPROCESSOR (NONUNIFORM MEMORY ACCESS [NUMA]); 3.5 SIMD PROCESSORS; 3.6 SYSTOLIC PROCESSORS; 3.7 CLUSTER COMPUTING; 3.8 GRID (CLOUD) COMPUTING 3.9 MULTICORE SYSTEMS3.10 SM; 3.11 COMMUNICATION BETWEEN PARALLEL PROCESSORS; 3.12 SUMMARY OF PARALLEL ARCHITECTURES; Chapter 4: Shared-Memory Multiprocessors; 4.1 INTRODUCTION; 4.2 CACHE COHERENCE AND MEMORY CONSISTENCY; 4.3 SYNCHRONIZATION AND MUTUAL EXCLUSION; Chapter 5: Interconnection Networks; 5.1 INTRODUCTION; 5.2 CLASSIFICATION OF INTERCONNECTION NETWORKS BY LOGICAL TOPOLOGIES; 5.3 INTERCONNECTION NETWORK SWITCH ARCHITECTURE; Chapter 6: Concurrency Platforms; 6.1 INTRODUCTION; 6.2 CONCURRENCY PLATFORMS; 6.3 CILK++; 6.4 OpenMP; 6.5 COMPUTE UNIFIED DEVICE ARCHITECTURE (CUDA) Chapter 7: Ad Hoc Techniques for Parallel Algorithms7.1 INTRODUCTION; 7.2 DEFINING ALGORITHM VARIABLES; 7.3 INDEPENDENT LOOP SCHEDULING; 7.4 DEPENDENT LOOPS; 7.5 LOOP SPREADING FOR SIMPLE DEPENDENT LOOPS; 7.6 LOOP UNROLLING; 7.7 PROBLEM PARTITIONING; 7.8 DIVIDE-AND-CONQUER (RECURSIVE PARTITIONING) STRATEGIES; 7.9 PIPELINING; Chapter 8: Nonserial-Parallel Algorithms; 8.1 INTRODUCTION; 8.2 COMPARING DAG AND DCG ALGORITHMS; 8.3 PARALLELIZING NSPA ALGORITHMS REPRESENTED BY A DAG; 8.4 FORMAL TECHNIQUE FOR ANALYZING NSPAs; 8.5 DETECTING CYCLES IN THE ALGORITHM 8.6 EXTRACTING SERIAL AND PARALLEL ALGORITHM PERFORMANCE PARAMETERS8.7 USEFUL THEOREMS; 8.8 PERFORMANCE OF SERIAL AND PARALLEL ALGORITHMS ON PARALLEL COMPUTERS; Chapter 9: z-Transform Analysis; 9.1 INTRODUCTION; 9.2 DEFINITION OF z-TRANSFORM; 9.3 THE 1-D FIR DIGITAL FILTER ALGORITHM; 9.4 SOFTWARE AND HARDWARE IMPLEMENTATIONS OF THE z-TRANSFORM; 9.5 DESIGN 1: USING HORNER'S RULE FOR BROADCAST INPUT AND PIPELINED OUTPUT; 9.6 DESIGN 2: PIPELINED INPUT AND BROADCAST OUTPUT; 9.7 DESIGN 3: PIPELINED INPUT AND OUTPUT; Chapter 10: Dependence Graph Analysis; 10.1 INTRODUCTION 10.2 THE 1-D FIR DIGITAL FILTER ALGORITHM |
| Record Nr. | UNINA-9910133581903321 |
|
Gebali Fayez
|
||
| Hoboken, N.J., : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Algorithms and parallel computing [[electronic resource] /] / Fayez Gebali
| Algorithms and parallel computing [[electronic resource] /] / Fayez Gebali |
| Autore | Gebali Fayez |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, 2011 |
| Descrizione fisica | 1 online resource (365 p.) |
| Disciplina |
004.35
004/.35 005.275 |
| Collana | Wiley series on parallel and distributed computing |
| Soggetto topico |
Parallel processing (Electronic computers)
Computer algorithms |
| ISBN |
1-283-02557-4
9786613025579 0-470-93201-5 0-470-93202-3 |
| Classificazione | COM043000 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Algorithms and Parallel Computing; Contents; Preface; List of Acronyms; Chapter 1: Introduction; 1.1 INTRODUCTION; 1.2 TOWARD AUTOMATING PARALLEL PROGRAMMING; 1.3 ALGORITHMS; 1.4 PARALLEL COMPUTING DESIGN CONSIDERATIONS; 1.5 PARALLEL ALGORITHMS AND PARALLEL ARCHITECTURES; 1.6 RELATING PARALLEL ALGORITHM AND PARALLEL ARCHITECTURE; 1.7 IMPLEMENTATION OF ALGORITHMS: A TWO-SIDED PROBLEM; 1.8 MEASURING BENEFITS OF PARALLEL COMPUTING; 1.9 AMDAHL'S LAW FOR MULTIPROCESSOR SYSTEMS; 1.10 GUSTAFSON-BARSIS'S LAW; 1.11 APPLICATIONS OF PARALLEL COMPUTING; Chapter 2: Enhancing Uniprocessor Performance
2.1 INTRODUCTION2.2 INCREASING PROCESSOR CLOCK FREQUENCY; 2.3 PARALLELIZING ALU STRUCTURE; 2.4 USING MEMORY HIERARCHY; 2.5 PIPELINING; 2.6 VERY LONG INSTRUCTION WORD (VLIW) PROCESSORS; 2.7 INSTRUCTION-LEVEL PARALLELISM (ILP) AND SUPERSCALAR PROCESSORS; 2.8 MULTITHREADED PROCESSOR; Chapter 3: Parallel Computers; 3.1 INTRODUCTION; 3.2 PARALLEL COMPUTING; 3.3 SHARED-MEMORY MULTIPROCESSORS (UNIFORM MEMORY ACCESS [UMA]); 3.4 DISTRIBUTED-MEMORY MULTIPROCESSOR (NONUNIFORM MEMORY ACCESS [NUMA]); 3.5 SIMD PROCESSORS; 3.6 SYSTOLIC PROCESSORS; 3.7 CLUSTER COMPUTING; 3.8 GRID (CLOUD) COMPUTING 3.9 MULTICORE SYSTEMS3.10 SM; 3.11 COMMUNICATION BETWEEN PARALLEL PROCESSORS; 3.12 SUMMARY OF PARALLEL ARCHITECTURES; Chapter 4: Shared-Memory Multiprocessors; 4.1 INTRODUCTION; 4.2 CACHE COHERENCE AND MEMORY CONSISTENCY; 4.3 SYNCHRONIZATION AND MUTUAL EXCLUSION; Chapter 5: Interconnection Networks; 5.1 INTRODUCTION; 5.2 CLASSIFICATION OF INTERCONNECTION NETWORKS BY LOGICAL TOPOLOGIES; 5.3 INTERCONNECTION NETWORK SWITCH ARCHITECTURE; Chapter 6: Concurrency Platforms; 6.1 INTRODUCTION; 6.2 CONCURRENCY PLATFORMS; 6.3 CILK++; 6.4 OpenMP; 6.5 COMPUTE UNIFIED DEVICE ARCHITECTURE (CUDA) Chapter 7: Ad Hoc Techniques for Parallel Algorithms7.1 INTRODUCTION; 7.2 DEFINING ALGORITHM VARIABLES; 7.3 INDEPENDENT LOOP SCHEDULING; 7.4 DEPENDENT LOOPS; 7.5 LOOP SPREADING FOR SIMPLE DEPENDENT LOOPS; 7.6 LOOP UNROLLING; 7.7 PROBLEM PARTITIONING; 7.8 DIVIDE-AND-CONQUER (RECURSIVE PARTITIONING) STRATEGIES; 7.9 PIPELINING; Chapter 8: Nonserial-Parallel Algorithms; 8.1 INTRODUCTION; 8.2 COMPARING DAG AND DCG ALGORITHMS; 8.3 PARALLELIZING NSPA ALGORITHMS REPRESENTED BY A DAG; 8.4 FORMAL TECHNIQUE FOR ANALYZING NSPAs; 8.5 DETECTING CYCLES IN THE ALGORITHM 8.6 EXTRACTING SERIAL AND PARALLEL ALGORITHM PERFORMANCE PARAMETERS8.7 USEFUL THEOREMS; 8.8 PERFORMANCE OF SERIAL AND PARALLEL ALGORITHMS ON PARALLEL COMPUTERS; Chapter 9: z-Transform Analysis; 9.1 INTRODUCTION; 9.2 DEFINITION OF z-TRANSFORM; 9.3 THE 1-D FIR DIGITAL FILTER ALGORITHM; 9.4 SOFTWARE AND HARDWARE IMPLEMENTATIONS OF THE z-TRANSFORM; 9.5 DESIGN 1: USING HORNER'S RULE FOR BROADCAST INPUT AND PIPELINED OUTPUT; 9.6 DESIGN 2: PIPELINED INPUT AND BROADCAST OUTPUT; 9.7 DESIGN 3: PIPELINED INPUT AND OUTPUT; Chapter 10: Dependence Graph Analysis; 10.1 INTRODUCTION 10.2 THE 1-D FIR DIGITAL FILTER ALGORITHM |
| Record Nr. | UNINA-9910830899403321 |
|
Gebali Fayez
|
||
| Hoboken, N.J., : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Algorithms and parallel computing [[electronic resource] /] / Fayez Gebali
| Algorithms and parallel computing [[electronic resource] /] / Fayez Gebali |
| Autore | Gebali Fayez |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Hoboken, N.J., : Wiley, 2011 |
| Descrizione fisica | 1 online resource (365 p.) |
| Disciplina |
004.35
004/.35 005.275 |
| Collana | Wiley series on parallel and distributed computing |
| Soggetto topico |
Parallel processing (Electronic computers)
Computer algorithms |
| ISBN |
1-283-02557-4
9786613025579 0-470-93201-5 0-470-93202-3 |
| Classificazione | COM043000 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Algorithms and Parallel Computing; Contents; Preface; List of Acronyms; Chapter 1: Introduction; 1.1 INTRODUCTION; 1.2 TOWARD AUTOMATING PARALLEL PROGRAMMING; 1.3 ALGORITHMS; 1.4 PARALLEL COMPUTING DESIGN CONSIDERATIONS; 1.5 PARALLEL ALGORITHMS AND PARALLEL ARCHITECTURES; 1.6 RELATING PARALLEL ALGORITHM AND PARALLEL ARCHITECTURE; 1.7 IMPLEMENTATION OF ALGORITHMS: A TWO-SIDED PROBLEM; 1.8 MEASURING BENEFITS OF PARALLEL COMPUTING; 1.9 AMDAHL'S LAW FOR MULTIPROCESSOR SYSTEMS; 1.10 GUSTAFSON-BARSIS'S LAW; 1.11 APPLICATIONS OF PARALLEL COMPUTING; Chapter 2: Enhancing Uniprocessor Performance
2.1 INTRODUCTION2.2 INCREASING PROCESSOR CLOCK FREQUENCY; 2.3 PARALLELIZING ALU STRUCTURE; 2.4 USING MEMORY HIERARCHY; 2.5 PIPELINING; 2.6 VERY LONG INSTRUCTION WORD (VLIW) PROCESSORS; 2.7 INSTRUCTION-LEVEL PARALLELISM (ILP) AND SUPERSCALAR PROCESSORS; 2.8 MULTITHREADED PROCESSOR; Chapter 3: Parallel Computers; 3.1 INTRODUCTION; 3.2 PARALLEL COMPUTING; 3.3 SHARED-MEMORY MULTIPROCESSORS (UNIFORM MEMORY ACCESS [UMA]); 3.4 DISTRIBUTED-MEMORY MULTIPROCESSOR (NONUNIFORM MEMORY ACCESS [NUMA]); 3.5 SIMD PROCESSORS; 3.6 SYSTOLIC PROCESSORS; 3.7 CLUSTER COMPUTING; 3.8 GRID (CLOUD) COMPUTING 3.9 MULTICORE SYSTEMS3.10 SM; 3.11 COMMUNICATION BETWEEN PARALLEL PROCESSORS; 3.12 SUMMARY OF PARALLEL ARCHITECTURES; Chapter 4: Shared-Memory Multiprocessors; 4.1 INTRODUCTION; 4.2 CACHE COHERENCE AND MEMORY CONSISTENCY; 4.3 SYNCHRONIZATION AND MUTUAL EXCLUSION; Chapter 5: Interconnection Networks; 5.1 INTRODUCTION; 5.2 CLASSIFICATION OF INTERCONNECTION NETWORKS BY LOGICAL TOPOLOGIES; 5.3 INTERCONNECTION NETWORK SWITCH ARCHITECTURE; Chapter 6: Concurrency Platforms; 6.1 INTRODUCTION; 6.2 CONCURRENCY PLATFORMS; 6.3 CILK++; 6.4 OpenMP; 6.5 COMPUTE UNIFIED DEVICE ARCHITECTURE (CUDA) Chapter 7: Ad Hoc Techniques for Parallel Algorithms7.1 INTRODUCTION; 7.2 DEFINING ALGORITHM VARIABLES; 7.3 INDEPENDENT LOOP SCHEDULING; 7.4 DEPENDENT LOOPS; 7.5 LOOP SPREADING FOR SIMPLE DEPENDENT LOOPS; 7.6 LOOP UNROLLING; 7.7 PROBLEM PARTITIONING; 7.8 DIVIDE-AND-CONQUER (RECURSIVE PARTITIONING) STRATEGIES; 7.9 PIPELINING; Chapter 8: Nonserial-Parallel Algorithms; 8.1 INTRODUCTION; 8.2 COMPARING DAG AND DCG ALGORITHMS; 8.3 PARALLELIZING NSPA ALGORITHMS REPRESENTED BY A DAG; 8.4 FORMAL TECHNIQUE FOR ANALYZING NSPAs; 8.5 DETECTING CYCLES IN THE ALGORITHM 8.6 EXTRACTING SERIAL AND PARALLEL ALGORITHM PERFORMANCE PARAMETERS8.7 USEFUL THEOREMS; 8.8 PERFORMANCE OF SERIAL AND PARALLEL ALGORITHMS ON PARALLEL COMPUTERS; Chapter 9: z-Transform Analysis; 9.1 INTRODUCTION; 9.2 DEFINITION OF z-TRANSFORM; 9.3 THE 1-D FIR DIGITAL FILTER ALGORITHM; 9.4 SOFTWARE AND HARDWARE IMPLEMENTATIONS OF THE z-TRANSFORM; 9.5 DESIGN 1: USING HORNER'S RULE FOR BROADCAST INPUT AND PIPELINED OUTPUT; 9.6 DESIGN 2: PIPELINED INPUT AND BROADCAST OUTPUT; 9.7 DESIGN 3: PIPELINED INPUT AND OUTPUT; Chapter 10: Dependence Graph Analysis; 10.1 INTRODUCTION 10.2 THE 1-D FIR DIGITAL FILTER ALGORITHM |
| Record Nr. | UNINA-9910841043903321 |
|
Gebali Fayez
|
||
| Hoboken, N.J., : Wiley, 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Beyond Loop Level Parallelism in OpenMP: Accelerators, Tasking and More [[electronic resource] /] / edited by Mitsuhisa Sato, Toshihiro Hanawa, Matthias S. Müller, Barbara Chapman, Bronis R. de Supinski
| Beyond Loop Level Parallelism in OpenMP: Accelerators, Tasking and More [[electronic resource] /] / edited by Mitsuhisa Sato, Toshihiro Hanawa, Matthias S. Müller, Barbara Chapman, Bronis R. de Supinski |
| Edizione | [1st ed. 2010.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2010 |
| Descrizione fisica | 1 online resource (187 p. 121 illus.) |
| Disciplina | 005.275 |
| Collana | Programming and Software Engineering |
| Soggetto topico |
Computer communication systems
Architecture, Computer Microprocessors Algorithms Software engineering Computers Computer Communication Networks Computer System Implementation Processor Architectures Algorithm Analysis and Problem Complexity Software Engineering Computation by Abstract Devices |
| ISBN |
1-280-38670-3
9786613564627 3-642-13217-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Sixth International Workshop on OpenMP IWOMP 2010 -- Enabling Low-Overhead Hybrid MPI/OpenMP Parallelism with MPC -- A ROSE-Based OpenMP 3.0 Research Compiler Supporting Multiple Runtime Libraries -- Binding Nested OpenMP Programs on Hierarchical Memory Architectures -- A Proposal for User-Defined Reductions in OpenMP -- An Extension to Improve OpenMP Tasking Control -- Towards an Error Model for OpenMP -- How OpenMP Applications Get More Benefit from Many-Core Era -- Topology-Aware OpenMP Process Scheduling -- How to Reconcile Event-Based Performance Analysis with Tasking in OpenMP -- Fuzzy Application Parallelization Using OpenMP -- Hybrid Parallel Programming on SMP Clusters Using XPFortran and OpenMP -- A Case for Including Transactions in OpenMP -- OMPCUDA : OpenMP Execution Framework for CUDA Based on Omni OpenMP Compiler. |
| Record Nr. | UNINA-9910482966803321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Beyond Loop Level Parallelism in OpenMP: Accelerators, Tasking and More [[electronic resource] /] / edited by Mitsuhisa Sato, Toshihiro Hanawa, Matthias S. Müller, Barbara Chapman, Bronis R. de Supinski
| Beyond Loop Level Parallelism in OpenMP: Accelerators, Tasking and More [[electronic resource] /] / edited by Mitsuhisa Sato, Toshihiro Hanawa, Matthias S. Müller, Barbara Chapman, Bronis R. de Supinski |
| Edizione | [1st ed. 2010.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2010 |
| Descrizione fisica | 1 online resource (187 p. 121 illus.) |
| Disciplina | 005.275 |
| Collana | Programming and Software Engineering |
| Soggetto topico |
Computer communication systems
Architecture, Computer Microprocessors Algorithms Software engineering Computers Computer Communication Networks Computer System Implementation Processor Architectures Algorithm Analysis and Problem Complexity Software Engineering Computation by Abstract Devices |
| ISBN |
1-280-38670-3
9786613564627 3-642-13217-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Sixth International Workshop on OpenMP IWOMP 2010 -- Enabling Low-Overhead Hybrid MPI/OpenMP Parallelism with MPC -- A ROSE-Based OpenMP 3.0 Research Compiler Supporting Multiple Runtime Libraries -- Binding Nested OpenMP Programs on Hierarchical Memory Architectures -- A Proposal for User-Defined Reductions in OpenMP -- An Extension to Improve OpenMP Tasking Control -- Towards an Error Model for OpenMP -- How OpenMP Applications Get More Benefit from Many-Core Era -- Topology-Aware OpenMP Process Scheduling -- How to Reconcile Event-Based Performance Analysis with Tasking in OpenMP -- Fuzzy Application Parallelization Using OpenMP -- Hybrid Parallel Programming on SMP Clusters Using XPFortran and OpenMP -- A Case for Including Transactions in OpenMP -- OMPCUDA : OpenMP Execution Framework for CUDA Based on Omni OpenMP Compiler. |
| Record Nr. | UNISA-996465838303316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Concurrent and distributed computing in Java [Risorsa elettronica] / Vijay K. Garg
| Concurrent and distributed computing in Java [Risorsa elettronica] / Vijay K. Garg |
| Autore | Garg, Vijay Kumar |
| Pubbl/distr/stampa | [Piscataway, N. J.] : IEEE |
| Disciplina | 005.275 |
| Soggetto non controllato |
Programmazione parallela
Java |
| ISBN | 9780471721277 |
| Formato | Risorse elettroniche  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-990009791750403321 |
|
Garg, Vijay Kumar
|
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| [Piscataway, N. J.] : IEEE | ||
| Risorse elettroniche | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
