Pubbl/distr/stampa	New York, New York : , : IEEE, , 2020
Descrizione fisica	1 online resource (37 pages)
Disciplina	005.14
Soggetto topico	Computer security Computer software - Verification
ISBN	1-5044-6313-7
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Altri titoli varianti	1711.2-2019 - IEEE Standard for Secure SCADA Communications Protocol
Record Nr.	UNINA-9910389519903321

Pubbl/distr/stampa	[Place of publication not identified], : IEEE, 2002
Descrizione fisica	1 online resource (ix, 188 pages) : illustrations
Disciplina	005.14
Soggetto topico	Computer software - Verification Electronic digital computers - Evaluation
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Record Nr.	UNINA-9910872451903321

Pubbl/distr/stampa	[Place of publication not identified], : I E E E, 2004
Descrizione fisica	1 online resource
Disciplina	005.14
Soggetto topico	Computer software - Verification Electronic circuits - Testing
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	HLDVT'04 - Ninth Annual IEEE International Workshop on High Level Design Validation and Test -- Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) -- Copyright -- Chairs' welcome message -- Committees -- Table of contents -- TTTC: test technology technical council -- Session 1: formal techniques -- Enhancing sequential depth computation with a branch-and-bound algorithm -- Reference model based RTL verification: an integrated approach -- Dynamic guiding of bounded property checking -- Towards an efficient assertion based verification of SystemC designs.
Record Nr.	UNINA-9910872487603321

Pubbl/distr/stampa	[Place of publication not identified], : I E E E, 2005
Descrizione fisica	1 online resource (viii, 250 pages) : illustrations
Disciplina	005.14
Soggetto topico	Computer software - Verification
ISBN	1-5090-9725-2
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Simulation-based functional test generation for embedded processors,"C. -- Scalable defect mapping and configuration of memory-based nanofabrics,"Chen -- Improvement of fault injection techniques based on VHDL code modification,"J. -- MVP: a mutation-based validation paradigm,"J. -- Establishing latch correspondence for embedded circuits of PowerPC microprocessors,"H. -- Sequential equivalence checking based on k-th invariants and circuit SAT solving,"Feng -- VERISEC: verifying equivalence of sequential circuits using SAT,"M. -- Automated clock inference for stream function-based system level specifications,"J. -- Cosimulation of ITRON-based embedded software with SystemC,"S. -- A software test program generator for verifying system-on-chips,"A. -- Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model,"Che-Hua -- DVGen: a test generator for the transmeta Efficeon VLIW processor,"K. -- Reuse in system-level stimuli-generation,"Y. -- Harnessing machine learning to improve the success rate of stimuli generation,"S. -- A new simulation-based property checking algorithm based on partitioned alternative search space traversal,"Qingwei -- Validating families of latency insensitive protocols,"S. -- GASIM: a fast Galois field based simulator for functional model,"D. -- Overlap reduction in symbolic system traversal,"P. -- Formal verification of high-level conformance with symbolic simulation,"R. -- A method for generation of GSTE assertion graphs,"E. -- Automatic abstraction refinement for Petri nets verification,"Zhenyu -- An optimum algorithm for compacting error traces for efficient functional debugging,"Chia-Chih -- Increasing the deducibility in CNF instances for efficient SAT-based bounded model checking,"V. -- B-cubing theory: new possibilities for efficient SAT-solving,"D. -- Multilevel design validation in a secure embedded system,"D. -- Security evaluation against electromagnetic analysis at design time,"Huiyun -- Formal meaning of coverage metrics in simulation-based hardware design verification,"I. -- Advanced analysis techniques for cross-product coverage,"H. -- A proof of correctness for the construction of property monitors,".
Record Nr.	UNISA-996199541903316

Pubbl/distr/stampa	[Place of publication not identified], : I E E E, 2005
Descrizione fisica	1 online resource (viii, 250 pages) : illustrations
Disciplina	005.14
Soggetto topico	Computer software - Verification
ISBN	9781509097258 1509097252
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Simulation-based functional test generation for embedded processors,"C. -- Scalable defect mapping and configuration of memory-based nanofabrics,"Chen -- Improvement of fault injection techniques based on VHDL code modification,"J. -- MVP: a mutation-based validation paradigm,"J. -- Establishing latch correspondence for embedded circuits of PowerPC microprocessors,"H. -- Sequential equivalence checking based on k-th invariants and circuit SAT solving,"Feng -- VERISEC: verifying equivalence of sequential circuits using SAT,"M. -- Automated clock inference for stream function-based system level specifications,"J. -- Cosimulation of ITRON-based embedded software with SystemC,"S. -- A software test program generator for verifying system-on-chips,"A. -- Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model,"Che-Hua -- DVGen: a test generator for the transmeta Efficeon VLIW processor,"K. -- Reuse in system-level stimuli-generation,"Y. -- Harnessing machine learning to improve the success rate of stimuli generation,"S. -- A new simulation-based property checking algorithm based on partitioned alternative search space traversal,"Qingwei -- Validating families of latency insensitive protocols,"S. -- GASIM: a fast Galois field based simulator for functional model,"D. -- Overlap reduction in symbolic system traversal,"P. -- Formal verification of high-level conformance with symbolic simulation,"R. -- A method for generation of GSTE assertion graphs,"E. -- Automatic abstraction refinement for Petri nets verification,"Zhenyu -- An optimum algorithm for compacting error traces for efficient functional debugging,"Chia-Chih -- Increasing the deducibility in CNF instances for efficient SAT-based bounded model checking,"V. -- B-cubing theory: new possibilities for efficient SAT-solving,"D. -- Multilevel design validation in a secure embedded system,"D. -- Security evaluation against electromagnetic analysis at design time,"Huiyun -- Formal meaning of coverage metrics in simulation-based hardware design verification,"I. -- Advanced analysis techniques for cross-product coverage,"H. -- A proof of correctness for the construction of property monitors,".
Record Nr.	UNINA-9910142188403321