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Advanced computer architecture : parallelism, scalability, programmability / Kai Hwang
| Advanced computer architecture : parallelism, scalability, programmability / Kai Hwang |
| Autore | Hwang, Kai |
| Pubbl/distr/stampa | New York : McGraw-Hill, copyr. 1993 |
| Descrizione fisica | XXIV, 771 p. : ill. ; 25 cm |
| Disciplina | 004.256 |
| Collana | McGraw-Hill computer science series. Computer organization and architecture. Networks, parallel and distibuted computing. McGraw- Hill computer engineering series |
| Soggetto non controllato | Microelaboratori elettronici - Struttura |
| ISBN | 0-07-031622-8 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | ita |
| Record Nr. | UNINA-990000133240403321 |
| Hwang, Kai | ||
| New York : McGraw-Hill, copyr. 1993 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Alpha architecture reference manual / The Alpha Architecture Committee
| Alpha architecture reference manual / The Alpha Architecture Committee |
| Edizione | [3. ed.] |
| Pubbl/distr/stampa | Boston [etc.], : Digital press, ©1998 |
| Descrizione fisica | 1 v. (paginazione varia) ; 24 cm. |
| Disciplina |
004.2
004.256 004.2565 |
| Soggetto topico |
Microprocessori
Microelaboratori - Struttura |
| ISBN | 1555582028 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISANNIO-NAP0391820 |
| Boston [etc.], : Digital press, ©1998 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Sannio | ||
| ||
Alpha implementations and architecture : complete reference and guide / Dileep P. Bhandarkar
| Alpha implementations and architecture : complete reference and guide / Dileep P. Bhandarkar |
| Autore | Bhandarkar, Dileep P. |
| Pubbl/distr/stampa | Boston [etc.], : Digital press, ©1996 |
| Descrizione fisica | XVIII, P. 19-328 : ill. ; 24 cm. |
| Disciplina |
004.2
004.256 004.2565 |
| Soggetto topico |
Microprocessori
Microprocessori Alpha |
| ISBN | 1555581307 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISANNIO-NAP0391831 |
Bhandarkar, Dileep P.
|
||
| Boston [etc.], : Digital press, ©1996 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Sannio | ||
| ||
The definitive guide to the ARM Cortex-M3 [[electronic resource] /] / Joseph Yiu
| The definitive guide to the ARM Cortex-M3 [[electronic resource] /] / Joseph Yiu |
| Autore | Yiu Joseph |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Newnes, c2007 |
| Descrizione fisica | 1 online resource (380 p.) |
| Disciplina |
004.16
004.256 |
| Collana | Embedded technology series |
| Soggetto topico |
Embedded computer systems
Microprocessors |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-03935-7
9786611039356 0-08-055143-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; The Definitive Guide to the ARM Cortex-M3; Copyright Page; Table of Contents; Foreword; Preface; Acknowledgments; Terms and Abbreviations; Conventions; References; Chapter 1 - Introduction; What Is the ARM Cortex-M3 Processor?; Background of ARM and ARM Architecture; A Brief History; Architecture Versions; Processor Naming; Instruction Set Development; The Thumb-2 Instruction Set Architecture (ISA); Cortex-M3 Processor Applications; Organization of This Book; Further Readings; Chapter 2 - Overview of the Cortex-M3; Fundamentals; Registers; R0 to R12: General-Purpose Registers
R13: Stack PointersR14: The Link Register; R15: The Program Counter; Special Registers; Operation Modes; The Built-In Nested Vectored Interrupt Controller; Nested Interrupt Support; Vectored Interrupt Support; Dynamic Priority Changes Support; Reduction of Interrupt Latency; Interrupt Masking; The Memory Map; The Bus Interface; The Memory Protection Unit; The Instruction Set; Interrupts and Exceptions; Debugging Support; Characteristics Summary; High Performance; Advanced Interrupt-Handling Features; Low Power Consumption; System Features; Debug Supports; Chapter 3 - Cortex-M3 Basics RegistersGeneral-Purpose Registers R0-R7; General-Purpose Registers R8-R12; Stack Pointer R13; Link Register R14; Program Counter R15; Special Registers; Program Status Registers (PSRs); PRIMASK, FAULTMASK, and BASEPRI Registers; The Control Register; Operation Mode; Exceptions and Interrupts; Vector Tables; Stack Memory Operations; Basic Operations of the Stack; Cortex-M3 Stack Implementation; The Two-Stack Model in the Cortex-M3; Reset Sequence; Chapter 4 - Instruction Sets; Assembly Basics; Assembler Language: Basic Syntax; Assembler Language: Use of Suffixes Assembler Language: Unified Assembler LanguageInstruction List; Unsupported Instructions; Instruction Descriptions; Assembler Language: Moving Data; LDR and ADR Pseudo Instructions; Assembler Language: Processing Data; Assembler Language: Call and Unconditional Branch; Assembler Language: Decisions and Conditional Branches; Assembler Language: Combined Compare and Conditional Branch; Assembler Language: Conditional Branches Using IT Instructions; Assembler Language: Instruction Barrier and Memory Barrier Instructions; Assembly Language: Saturation Operations Several Useful Instructions in the Cortex-M3MSR and MRS; IF-THEN; CBZ and CBNZ; SDIV and UDIV; REV, REVH, and REVSH; RBIT; SXTB, SXTH, UXTB, and UXTH; BFC and BFI; UBFX and SBFX; LDRD and STRD; TBB and TBH; Chapter 5 - Memory Systems; Memory System Features Overview; Memory Maps; Memory Access Attributes; Default Memory Access Permissions; Bit-Band Operations; Advantages of Bit-Band Operations; Bit-Band Operation of Different Data Sizes; Bit-Band Operations in C Programs; Unaligned Transfers; Exclusive Accesses; Endian Mode; Chapter 6 - Cortex-M3 Implementation Overview; The Pipeline A Detailed Block Diagram |
| Record Nr. | UNINA-9910457699403321 |
|
Yiu Joseph
|
||
| Amsterdam ; ; Boston, : Newnes, c2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
The definitive guide to the ARM Cortex-M3 [[electronic resource] /] / Joseph Yiu
| The definitive guide to the ARM Cortex-M3 [[electronic resource] /] / Joseph Yiu |
| Autore | Yiu Joseph |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Newnes, c2007 |
| Descrizione fisica | 1 online resource (380 p.) |
| Disciplina |
004.16
004.256 |
| Collana | Embedded technology series |
| Soggetto topico |
Embedded computer systems
Microprocessors |
| ISBN |
1-281-03935-7
9786611039356 0-08-055143-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; The Definitive Guide to the ARM Cortex-M3; Copyright Page; Table of Contents; Foreword; Preface; Acknowledgments; Terms and Abbreviations; Conventions; References; Chapter 1 - Introduction; What Is the ARM Cortex-M3 Processor?; Background of ARM and ARM Architecture; A Brief History; Architecture Versions; Processor Naming; Instruction Set Development; The Thumb-2 Instruction Set Architecture (ISA); Cortex-M3 Processor Applications; Organization of This Book; Further Readings; Chapter 2 - Overview of the Cortex-M3; Fundamentals; Registers; R0 to R12: General-Purpose Registers
R13: Stack PointersR14: The Link Register; R15: The Program Counter; Special Registers; Operation Modes; The Built-In Nested Vectored Interrupt Controller; Nested Interrupt Support; Vectored Interrupt Support; Dynamic Priority Changes Support; Reduction of Interrupt Latency; Interrupt Masking; The Memory Map; The Bus Interface; The Memory Protection Unit; The Instruction Set; Interrupts and Exceptions; Debugging Support; Characteristics Summary; High Performance; Advanced Interrupt-Handling Features; Low Power Consumption; System Features; Debug Supports; Chapter 3 - Cortex-M3 Basics RegistersGeneral-Purpose Registers R0-R7; General-Purpose Registers R8-R12; Stack Pointer R13; Link Register R14; Program Counter R15; Special Registers; Program Status Registers (PSRs); PRIMASK, FAULTMASK, and BASEPRI Registers; The Control Register; Operation Mode; Exceptions and Interrupts; Vector Tables; Stack Memory Operations; Basic Operations of the Stack; Cortex-M3 Stack Implementation; The Two-Stack Model in the Cortex-M3; Reset Sequence; Chapter 4 - Instruction Sets; Assembly Basics; Assembler Language: Basic Syntax; Assembler Language: Use of Suffixes Assembler Language: Unified Assembler LanguageInstruction List; Unsupported Instructions; Instruction Descriptions; Assembler Language: Moving Data; LDR and ADR Pseudo Instructions; Assembler Language: Processing Data; Assembler Language: Call and Unconditional Branch; Assembler Language: Decisions and Conditional Branches; Assembler Language: Combined Compare and Conditional Branch; Assembler Language: Conditional Branches Using IT Instructions; Assembler Language: Instruction Barrier and Memory Barrier Instructions; Assembly Language: Saturation Operations Several Useful Instructions in the Cortex-M3MSR and MRS; IF-THEN; CBZ and CBNZ; SDIV and UDIV; REV, REVH, and REVSH; RBIT; SXTB, SXTH, UXTB, and UXTH; BFC and BFI; UBFX and SBFX; LDRD and STRD; TBB and TBH; Chapter 5 - Memory Systems; Memory System Features Overview; Memory Maps; Memory Access Attributes; Default Memory Access Permissions; Bit-Band Operations; Advantages of Bit-Band Operations; Bit-Band Operation of Different Data Sizes; Bit-Band Operations in C Programs; Unaligned Transfers; Exclusive Accesses; Endian Mode; Chapter 6 - Cortex-M3 Implementation Overview; The Pipeline A Detailed Block Diagram |
| Record Nr. | UNINA-9910784350603321 |
|
Yiu Joseph
|
||
| Amsterdam ; ; Boston, : Newnes, c2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
The definitive guide to the ARM Cortex-M3 [[electronic resource] /] / Joseph Yiu
| The definitive guide to the ARM Cortex-M3 [[electronic resource] /] / Joseph Yiu |
| Autore | Yiu Joseph |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Newnes, c2007 |
| Descrizione fisica | 1 online resource (380 p.) |
| Disciplina |
004.16
004.256 |
| Collana | Embedded technology series |
| Soggetto topico |
Embedded computer systems
Microprocessors |
| ISBN |
1-281-03935-7
9786611039356 0-08-055143-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; The Definitive Guide to the ARM Cortex-M3; Copyright Page; Table of Contents; Foreword; Preface; Acknowledgments; Terms and Abbreviations; Conventions; References; Chapter 1 - Introduction; What Is the ARM Cortex-M3 Processor?; Background of ARM and ARM Architecture; A Brief History; Architecture Versions; Processor Naming; Instruction Set Development; The Thumb-2 Instruction Set Architecture (ISA); Cortex-M3 Processor Applications; Organization of This Book; Further Readings; Chapter 2 - Overview of the Cortex-M3; Fundamentals; Registers; R0 to R12: General-Purpose Registers
R13: Stack PointersR14: The Link Register; R15: The Program Counter; Special Registers; Operation Modes; The Built-In Nested Vectored Interrupt Controller; Nested Interrupt Support; Vectored Interrupt Support; Dynamic Priority Changes Support; Reduction of Interrupt Latency; Interrupt Masking; The Memory Map; The Bus Interface; The Memory Protection Unit; The Instruction Set; Interrupts and Exceptions; Debugging Support; Characteristics Summary; High Performance; Advanced Interrupt-Handling Features; Low Power Consumption; System Features; Debug Supports; Chapter 3 - Cortex-M3 Basics RegistersGeneral-Purpose Registers R0-R7; General-Purpose Registers R8-R12; Stack Pointer R13; Link Register R14; Program Counter R15; Special Registers; Program Status Registers (PSRs); PRIMASK, FAULTMASK, and BASEPRI Registers; The Control Register; Operation Mode; Exceptions and Interrupts; Vector Tables; Stack Memory Operations; Basic Operations of the Stack; Cortex-M3 Stack Implementation; The Two-Stack Model in the Cortex-M3; Reset Sequence; Chapter 4 - Instruction Sets; Assembly Basics; Assembler Language: Basic Syntax; Assembler Language: Use of Suffixes Assembler Language: Unified Assembler LanguageInstruction List; Unsupported Instructions; Instruction Descriptions; Assembler Language: Moving Data; LDR and ADR Pseudo Instructions; Assembler Language: Processing Data; Assembler Language: Call and Unconditional Branch; Assembler Language: Decisions and Conditional Branches; Assembler Language: Combined Compare and Conditional Branch; Assembler Language: Conditional Branches Using IT Instructions; Assembler Language: Instruction Barrier and Memory Barrier Instructions; Assembly Language: Saturation Operations Several Useful Instructions in the Cortex-M3MSR and MRS; IF-THEN; CBZ and CBNZ; SDIV and UDIV; REV, REVH, and REVSH; RBIT; SXTB, SXTH, UXTB, and UXTH; BFC and BFI; UBFX and SBFX; LDRD and STRD; TBB and TBH; Chapter 5 - Memory Systems; Memory System Features Overview; Memory Maps; Memory Access Attributes; Default Memory Access Permissions; Bit-Band Operations; Advantages of Bit-Band Operations; Bit-Band Operation of Different Data Sizes; Bit-Band Operations in C Programs; Unaligned Transfers; Exclusive Accesses; Endian Mode; Chapter 6 - Cortex-M3 Implementation Overview; The Pipeline A Detailed Block Diagram |
| Record Nr. | UNINA-9910819500303321 |
|
Yiu Joseph
|
||
| Amsterdam ; ; Boston, : Newnes, c2007 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Digital design principles and computer architecture / Edward Karalis
| Digital design principles and computer architecture / Edward Karalis |
| Autore | Karalis, Edward |
| Pubbl/distr/stampa | Upper Saddle River (NJ), : Prentice-Hall International, c1997 |
| Descrizione fisica | XIII, 528 p. : ill. ; 24 cm. |
| Disciplina |
004.2
004.256 |
| Soggetto topico |
Circuiti integrati - Progettazione
Microprocessori - Progettazione Microelaboratori - Struttura |
| ISBN | 0135712661 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISANNIO-RMS0048417 |
|
Karalis, Edward
|
||
| Upper Saddle River (NJ), : Prentice-Hall International, c1997 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Sannio | ||
| ||
Location- and context-awareness : third international symposium, LoCA 2007, Oberpfaffenhofen, Germany, September 20-21, 2007 : proceedings / / Jeffrey Hightower, Bernt Schiele, Thomas Strang (editors)
| Location- and context-awareness : third international symposium, LoCA 2007, Oberpfaffenhofen, Germany, September 20-21, 2007 : proceedings / / Jeffrey Hightower, Bernt Schiele, Thomas Strang (editors) |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Germany ; ; New York, New York : , : Springer, , [2007] |
| Descrizione fisica | 1 online resource (X, 300 p.) |
| Disciplina | 004.256 |
| Collana | Information Systems and Applications, incl. Internet/Web, and HCI |
| Soggetto topico |
Mobile communication systems - Data processing
Electronic data processing - Distributed processing Context-aware computing |
| ISBN | 3-540-75160-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Bootstrapping a Location Service Through Geocoded Postal Addresses -- Deployment, Calibration, and Measurement Factors for Position Errors in 802.11-Based Indoor Positioning Systems -- LifeTag: WiFi-Based Continuous Location Logging for Life Pattern Analysis -- Scalable Recognition of Daily Activities with Wearable Sensors -- Information Overlay for Camera Phones in Indoor Environments -- SocialMotion: Measuring the Hidden Social Life of a Building -- A Unified Semantics Space Model -- Federation and Sharing in the Context Marketplace -- A Taxonomy for Radio Location Fingerprinting -- Inferring the Everyday Task Capabilities of Locations -- The Whereabouts Diary -- Adaptive Learning of Semantic Locations and Routes -- Signal Dragging: Effects of Terminal Movement on War-Driving in CDMA/WCDMA Networks -- Modeling and Optimizing Positional Accuracy Based on Hyperbolic Geometry for the Adaptive Radio Interferometric Positioning System -- Inferring Position Knowledge from Location Predicates -- Preserving Anonymity in Indoor Location System by Context Sensing and Camera-Based Tracking -- Localizing Tags Using Mobile Infrastructure. |
| Record Nr. | UNISA-996465603603316 |
| Berlin, Germany ; ; New York, New York : , : Springer, , [2007] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Location- and context-awareness : third international symposium, LoCA 2007, Oberpfaffenhofen, Germany, September 20-21, 2007 : proceedings / / Jeffrey Hightower, Bernt Schiele, Thomas Strang (editors)
| Location- and context-awareness : third international symposium, LoCA 2007, Oberpfaffenhofen, Germany, September 20-21, 2007 : proceedings / / Jeffrey Hightower, Bernt Schiele, Thomas Strang (editors) |
| Edizione | [1st ed. 2007.] |
| Pubbl/distr/stampa | Berlin, Germany ; ; New York, New York : , : Springer, , [2007] |
| Descrizione fisica | 1 online resource (X, 300 p.) |
| Disciplina | 004.256 |
| Collana | Information Systems and Applications, incl. Internet/Web, and HCI |
| Soggetto topico |
Mobile communication systems - Data processing
Electronic data processing - Distributed processing Context-aware computing |
| ISBN | 3-540-75160-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Bootstrapping a Location Service Through Geocoded Postal Addresses -- Deployment, Calibration, and Measurement Factors for Position Errors in 802.11-Based Indoor Positioning Systems -- LifeTag: WiFi-Based Continuous Location Logging for Life Pattern Analysis -- Scalable Recognition of Daily Activities with Wearable Sensors -- Information Overlay for Camera Phones in Indoor Environments -- SocialMotion: Measuring the Hidden Social Life of a Building -- A Unified Semantics Space Model -- Federation and Sharing in the Context Marketplace -- A Taxonomy for Radio Location Fingerprinting -- Inferring the Everyday Task Capabilities of Locations -- The Whereabouts Diary -- Adaptive Learning of Semantic Locations and Routes -- Signal Dragging: Effects of Terminal Movement on War-Driving in CDMA/WCDMA Networks -- Modeling and Optimizing Positional Accuracy Based on Hyperbolic Geometry for the Adaptive Radio Interferometric Positioning System -- Inferring Position Knowledge from Location Predicates -- Preserving Anonymity in Indoor Location System by Context Sensing and Camera-Based Tracking -- Localizing Tags Using Mobile Infrastructure. |
| Record Nr. | UNINA-9910484710403321 |
| Berlin, Germany ; ; New York, New York : , : Springer, , [2007] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Pentium processor system architecture / MindShare, Inc. ; Don Anderson and Tom Shanley
| Pentium processor system architecture / MindShare, Inc. ; Don Anderson and Tom Shanley |
| Autore | Anderson, Don |
| Edizione | [2. ed] |
| Pubbl/distr/stampa | Reading, Mass. : Addison-Wesley, 1995 |
| Descrizione fisica | XXVII, 433 p. : ill. ; 24 cm. |
| Disciplina | 004.256 |
| ISBN | 02-01-40992-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNICAMPANIA-SUN0038902 |
|
Anderson, Don
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| Reading, Mass. : Addison-Wesley, 1995 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Vanvitelli | ||
| ||
