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Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013, Proceedings / / edited by Philip Brisk, José Gabriel de Figueiredo Coutinho, Pedro Diniz
| Reconfigurable Computing: Architectures, Tools and Applications [[electronic resource] ] : 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013, Proceedings / / edited by Philip Brisk, José Gabriel de Figueiredo Coutinho, Pedro Diniz |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 |
| Descrizione fisica | 1 online resource (XVI, 238 p. 104 illus.) |
| Disciplina | 006.3 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Computer engineering Computer networks Algorithms Computer Hardware Computer Engineering and Networks |
| ISBN | 3-642-36812-3 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications -- Hardware Acceleration of Genetic Sequence Alignment -- An FPGA Acceleration for the Kd-tree Search in Photon Mapping -- SEU Resilience of DES, AES in SRAM-based FPGA -- An Architecture for IPv6 Lookup Using Parallel Index Generation Units -- Hardware Index to Set Partition Converter -- Teaching SoC Using Video Games to Improve Student Engagement -- Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-based Custom Computing -- Hardware Acceleration of Matrix Multiplication Over Small Prime Finite Fields -- Flexible Design of a Modular Simultaneous Exponentiation Core for Embedded Platforms -- Architecture for Transparent Binary Acceleration of Loops with Memory Accesses -- Parametric Optimization of Reconfigurable Designs using Machine Learning -- Fast Template-based Heterogeneous MPSoC Synthesis on FPGA -- Hierarchical and Multiple Switching NoC with Floorplan based Adaptability -- Performance Analysis And Optimization of High Density Tree-Based 3D Multilevel FPGA. |
| Record Nr. | UNISA-996465621603316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Reconfigurable Computing: Architectures, Tools and Applications : 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013, Proceedings / / edited by Philip Brisk, José Gabriel de Figueiredo Coutinho, Pedro Diniz
| Reconfigurable Computing: Architectures, Tools and Applications : 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013, Proceedings / / edited by Philip Brisk, José Gabriel de Figueiredo Coutinho, Pedro Diniz |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 |
| Descrizione fisica | 1 online resource (XVI, 238 p. 104 illus.) |
| Disciplina | 006.3 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computers
Computer engineering Computer networks Algorithms Computer Hardware Computer Engineering and Networks |
| ISBN | 3-642-36812-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications -- Hardware Acceleration of Genetic Sequence Alignment -- An FPGA Acceleration for the Kd-tree Search in Photon Mapping -- SEU Resilience of DES, AES in SRAM-based FPGA -- An Architecture for IPv6 Lookup Using Parallel Index Generation Units -- Hardware Index to Set Partition Converter -- Teaching SoC Using Video Games to Improve Student Engagement -- Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-based Custom Computing -- Hardware Acceleration of Matrix Multiplication Over Small Prime Finite Fields -- Flexible Design of a Modular Simultaneous Exponentiation Core for Embedded Platforms -- Architecture for Transparent Binary Acceleration of Loops with Memory Accesses -- Parametric Optimization of Reconfigurable Designs using Machine Learning -- Fast Template-based Heterogeneous MPSoC Synthesis on FPGA -- Hierarchical and Multiple Switching NoC with Floorplan based Adaptability -- Performance Analysis And Optimization of High Density Tree-Based 3D Multilevel FPGA. |
| Record Nr. | UNINA-9910485024003321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||