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Biblioteca

MARC Lista (tabellare)
The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / / Joseph Yiu, ARM Ltd., Cambridge, UK
The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / / Joseph Yiu, ARM Ltd., Cambridge, UK
Autore Yiu Joseph
Edizione [Third edition.]
Pubbl/distr/stampa Amsterdam : , : Newnes/Elsevier, , [2014]
Descrizione fisica 1 online resource (1055 p.)
Disciplina 1055
Soggetto topico Embedded computer systems
Microprocessors
Soggetto genere / forma Electronic books.
ISBN 0-12-407918-0
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; The Definitive Guide to ARM® Cortex®-M3 and Cortex-M4 Processors; Copyright; Contents; Foreword; Preface; Synopsis; About this Book; Contributor Bio-Paul Beckmann; Acknowledgments; Terms and Abbreviations; Conventions; Chapter 1 - Introduction to ARM® Cortex®-M Processors; 1.1 What are the ARM® Cortex®-M processors?; 1.2 Advantages of the Cortex®-M processors; 1.3 Applications of the ARM® Cortex®-M processors; 1.4 Resources for using ARM® processors and ARM microcontrollers; 1.5 Background and history; Chapter 2 - Introduction to Embedded Software Development
2.1 What are inside typical ARM® microcontrollers?2.2 What you need to start; 2.3 Software development flow; 2.4 Compiling your applications; 2.5 Software flow; 2.6 Data types in C programming; 2.7 Inputs, outputs, and peripherals accesses; 2.8 Microcontroller interfaces; 2.9 The Cortex® microcontroller software interface standard (CMSIS); Chapter 3 - Technical Overview; 3.1 General information about the Cortex®-M3 and Cortex-M4 processors; 3.2 Features of the Cortex®-M3 and Cortex-M4 processors; Chapter 4 - Architecture; 4.1 Introduction to the architecture; 4.2 Programmer's model
4.3 Behavior of the application program status register (APSR)4.4 Memory system; 4.5 Exceptions and interrupts; 4.6 System control block (SCB); 4.7 Debug; 4.8 Reset and reset sequence; Chapter 5 - Instruction Set; 5.1 Background to the instruction set in ARM® Cortex®-M processors; 5.2 Comparison of the instruction set in ARM® Cortex®-M processors; 5.3 Understanding the assembly language syntax; 5.4 Use of a suffix in instructions; 5.5 Unified assembly language (UAL); 5.6 Instruction set; 5.7 Cortex®-M4-specific instructions; 5.8 Barrel shifter
5.9 Accessing special instructions and special registers in programmingChapter 6 - Memory System; 6.1 Overview of memory system features; 6.2 Memory map; 6.3 Connecting the processor to memory and peripherals; 6.4 Memory requirements; 6.5 Memory endianness; 6.6 Data alignment and unaligned data access support; 6.7 Bit-band operations; 6.8 Default memory access permissions; 6.9 Memory access attributes; 6.10 Exclusive accesses; 6.11 Memory barriers; 6.12 Memory system in a microcontroller; Chapter 7 - Exceptions and Interrupts; 7.1 Overview of exceptions and interrupts; 7.2 Exception types
7.3 Overview of interrupt management7.4 Definitions of priority; 7.5 Vector table and vector table relocation; 7.6 Interrupt inputs and pending behaviors; 7.7 Exception sequence overview; 7.8 Details of NVIC registers for interrupt control; 7.9 Details of SCB registers for exception and interrupt control; 7.10 Details of special registers for exception or interrupt masking; 7.11 Example procedures in setting up interrupts; 7.12 Software interrupts; 7.13 Tips and hints; Chapter 8 - Exception Handling in Detail; 8.1 Introduction; 8.2 Exception sequences
8.3 Interrupt latency and exception handling optimization
Record Nr. UNINA-9910452431203321
Yiu Joseph  
Amsterdam : , : Newnes/Elsevier, , [2014]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / / Joseph Yiu, ARM Ltd., Cambridge, UK
The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / / Joseph Yiu, ARM Ltd., Cambridge, UK
Autore Yiu Joseph
Edizione [Third edition.]
Pubbl/distr/stampa Oxford : , : Newnes, , 2014
Descrizione fisica 1 online resource (xxxv, 818, 200 pages) : illustrations (some color)
Disciplina 1055
Collana Gale eBooks
Soggetto topico Embedded computer systems
Microprocessors
ISBN 0-12-407918-0
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; The Definitive Guide to ARM® Cortex®-M3 and Cortex-M4 Processors; Copyright; Contents; Foreword; Preface; Synopsis; About this Book; Contributor Bio-Paul Beckmann; Acknowledgments; Terms and Abbreviations; Conventions; Chapter 1 - Introduction to ARM® Cortex®-M Processors; 1.1 What are the ARM® Cortex®-M processors?; 1.2 Advantages of the Cortex®-M processors; 1.3 Applications of the ARM® Cortex®-M processors; 1.4 Resources for using ARM® processors and ARM microcontrollers; 1.5 Background and history; Chapter 2 - Introduction to Embedded Software Development
2.1 What are inside typical ARM® microcontrollers?2.2 What you need to start; 2.3 Software development flow; 2.4 Compiling your applications; 2.5 Software flow; 2.6 Data types in C programming; 2.7 Inputs, outputs, and peripherals accesses; 2.8 Microcontroller interfaces; 2.9 The Cortex® microcontroller software interface standard (CMSIS); Chapter 3 - Technical Overview; 3.1 General information about the Cortex®-M3 and Cortex-M4 processors; 3.2 Features of the Cortex®-M3 and Cortex-M4 processors; Chapter 4 - Architecture; 4.1 Introduction to the architecture; 4.2 Programmer's model
4.3 Behavior of the application program status register (APSR)4.4 Memory system; 4.5 Exceptions and interrupts; 4.6 System control block (SCB); 4.7 Debug; 4.8 Reset and reset sequence; Chapter 5 - Instruction Set; 5.1 Background to the instruction set in ARM® Cortex®-M processors; 5.2 Comparison of the instruction set in ARM® Cortex®-M processors; 5.3 Understanding the assembly language syntax; 5.4 Use of a suffix in instructions; 5.5 Unified assembly language (UAL); 5.6 Instruction set; 5.7 Cortex®-M4-specific instructions; 5.8 Barrel shifter
5.9 Accessing special instructions and special registers in programmingChapter 6 - Memory System; 6.1 Overview of memory system features; 6.2 Memory map; 6.3 Connecting the processor to memory and peripherals; 6.4 Memory requirements; 6.5 Memory endianness; 6.6 Data alignment and unaligned data access support; 6.7 Bit-band operations; 6.8 Default memory access permissions; 6.9 Memory access attributes; 6.10 Exclusive accesses; 6.11 Memory barriers; 6.12 Memory system in a microcontroller; Chapter 7 - Exceptions and Interrupts; 7.1 Overview of exceptions and interrupts; 7.2 Exception types
7.3 Overview of interrupt management7.4 Definitions of priority; 7.5 Vector table and vector table relocation; 7.6 Interrupt inputs and pending behaviors; 7.7 Exception sequence overview; 7.8 Details of NVIC registers for interrupt control; 7.9 Details of SCB registers for exception and interrupt control; 7.10 Details of special registers for exception or interrupt masking; 7.11 Example procedures in setting up interrupts; 7.12 Software interrupts; 7.13 Tips and hints; Chapter 8 - Exception Handling in Detail; 8.1 Introduction; 8.2 Exception sequences
8.3 Interrupt latency and exception handling optimization
Record Nr. UNINA-9910790517303321
Yiu Joseph  
Oxford : , : Newnes, , 2014
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / / Joseph Yiu, ARM Ltd., Cambridge, UK
The definitive guide to ARM Cortex-M3 and Cortex-M4 processors / / Joseph Yiu, ARM Ltd., Cambridge, UK
Autore Yiu Joseph
Edizione [Third edition.]
Pubbl/distr/stampa Oxford : , : Newnes, , 2014
Descrizione fisica 1 online resource (xxxv, 818, 200 pages) : illustrations (some color)
Disciplina 1055
Collana Gale eBooks
Soggetto topico Embedded computer systems
Microprocessors
ISBN 0-12-407918-0
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; The Definitive Guide to ARM® Cortex®-M3 and Cortex-M4 Processors; Copyright; Contents; Foreword; Preface; Synopsis; About this Book; Contributor Bio-Paul Beckmann; Acknowledgments; Terms and Abbreviations; Conventions; Chapter 1 - Introduction to ARM® Cortex®-M Processors; 1.1 What are the ARM® Cortex®-M processors?; 1.2 Advantages of the Cortex®-M processors; 1.3 Applications of the ARM® Cortex®-M processors; 1.4 Resources for using ARM® processors and ARM microcontrollers; 1.5 Background and history; Chapter 2 - Introduction to Embedded Software Development
2.1 What are inside typical ARM® microcontrollers?2.2 What you need to start; 2.3 Software development flow; 2.4 Compiling your applications; 2.5 Software flow; 2.6 Data types in C programming; 2.7 Inputs, outputs, and peripherals accesses; 2.8 Microcontroller interfaces; 2.9 The Cortex® microcontroller software interface standard (CMSIS); Chapter 3 - Technical Overview; 3.1 General information about the Cortex®-M3 and Cortex-M4 processors; 3.2 Features of the Cortex®-M3 and Cortex-M4 processors; Chapter 4 - Architecture; 4.1 Introduction to the architecture; 4.2 Programmer's model
4.3 Behavior of the application program status register (APSR)4.4 Memory system; 4.5 Exceptions and interrupts; 4.6 System control block (SCB); 4.7 Debug; 4.8 Reset and reset sequence; Chapter 5 - Instruction Set; 5.1 Background to the instruction set in ARM® Cortex®-M processors; 5.2 Comparison of the instruction set in ARM® Cortex®-M processors; 5.3 Understanding the assembly language syntax; 5.4 Use of a suffix in instructions; 5.5 Unified assembly language (UAL); 5.6 Instruction set; 5.7 Cortex®-M4-specific instructions; 5.8 Barrel shifter
5.9 Accessing special instructions and special registers in programmingChapter 6 - Memory System; 6.1 Overview of memory system features; 6.2 Memory map; 6.3 Connecting the processor to memory and peripherals; 6.4 Memory requirements; 6.5 Memory endianness; 6.6 Data alignment and unaligned data access support; 6.7 Bit-band operations; 6.8 Default memory access permissions; 6.9 Memory access attributes; 6.10 Exclusive accesses; 6.11 Memory barriers; 6.12 Memory system in a microcontroller; Chapter 7 - Exceptions and Interrupts; 7.1 Overview of exceptions and interrupts; 7.2 Exception types
7.3 Overview of interrupt management7.4 Definitions of priority; 7.5 Vector table and vector table relocation; 7.6 Interrupt inputs and pending behaviors; 7.7 Exception sequence overview; 7.8 Details of NVIC registers for interrupt control; 7.9 Details of SCB registers for exception and interrupt control; 7.10 Details of special registers for exception or interrupt masking; 7.11 Example procedures in setting up interrupts; 7.12 Software interrupts; 7.13 Tips and hints; Chapter 8 - Exception Handling in Detail; 8.1 Introduction; 8.2 Exception sequences
8.3 Interrupt latency and exception handling optimization
Record Nr. UNINA-9910808435103321
Yiu Joseph  
Oxford : , : Newnes, , 2014
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
The definitive guide to the ARM cortex-M0 [[electronic resource] /] / Joseph Yiu
The definitive guide to the ARM cortex-M0 [[electronic resource] /] / Joseph Yiu
Autore Yiu Joseph
Edizione [1st edition]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Newnes, 2011
Descrizione fisica 1 online resource (553 p.)
Disciplina 621.39/16
621.3916
Soggetto topico Embedded computer systems
Microprocessors
Soggetto genere / forma Electronic books.
ISBN 1-283-52645-X
9786613838902
0-12-385478-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; The Definitive Guide to the ARM Cortex-M0; Copyright; Contents; Foreword; Preface; Acknowledgments; Conventions; Terms and Abbreviations; Chapter 1 Introduction; Why Cortex-M0?; Application of the Cortex-M0 Processors; Background of ARM and ARM processors; Cortex-M0 Processor Specification and ARM Architecture; ARM Processors and the ARM Ecosystem; Getting Started with the Cortex-M0 Processor; Organization of This Book and Resources; Chapter 2 Cortex-M0 Technical Overview; General Information on the Cortex-M0 Processor; The ARM Cortex-M0 Processor Features
Advantages of the Cortex-M0 ProcessorLow-Power Applications; Cortex-M0 Software Portability; Chapter 3 Architecture; Overview; Programmer's Model; Memory System Overview; Stack Memory Operations; Exceptions and Interrupts; Nested Vectored Interrupt Controller (NVIC); System Control Block (SCB); Program Image and Startup Sequence; Chapter 4 Introduction to Cortex-M0 Programming; Introduction to Embedded System Programming; Inputs and Outputs; Development Flow; C Programming and Assembly Programming; What Is in a Program Image?; C Programming: Data Types; Accessing Peripherals in C
Cortex Microcontroller Software Interface Standard (CMSIS)Benefits of CMSIS; Chapter 5 Instruction Set; Background of ARM and Thumb Instruction Set; Assembly Basics; Pseudo Instructions; Chapter 6 Instruction Usage Examples; Overview; Program Control; Data Accesses; Data Type Conversion; Data Processing; Chapter 7 Memory System; Overview; Memory Map; Program Memory, Boot Loader, and Memory Remapping; Data Memory; Little Endian and Big Endian Support; Memory Attributes; Chapter 8 Exceptions and Interrupts; What Are Exceptions and Interrupts?; Exception Types on the Cortex-M0 Processor
Exception Priority DefinitionVector Table; Exception Sequence Overview; EXC_RETURN; Details of Exception Entry Sequence; Details of Exception Exit Sequence; Chapter 9 Interrupt Control and System Control; Overview of the NVIC and System Control Block Features; Interrupt Enable and Clear Enable; Interrupt Pending and Clear Pending; Interrupt Priority Level; Generic Assembly Code for Interrupt Control; Exception Masking Register (PRIMASK); Interrupt Inputs and Pending Behavior; Interrupt Latency; Control Registers for System Exceptions; System Control Registers
Chapter 10 Operating System Support FeaturesOverview of the OS Support Features; The SysTick Timer; SysTick Registers; Process Stack and Process Stack Pointer; SVC; PendSV; Chapter 11 Low-Power Features; Low-Power Embedded System Overview; Low-Power Advantages of the Cortex-M0 Processor; Overview of the Low-Power Features; Sleep Modes; Wait-for-Event (WFE) and Wait-for-Interrupt (WFI); Sleep-on-Exit Feature; Wakeup Interrupt Controller; Chapter 12 Fault Handling; Fault Exception Overview; Analyze a Fault; Accidental Switching to ARM State; Error Handling in Real Applications; Lockup
Preventing Lockup
Record Nr. UNINA-9910465513203321
Yiu Joseph  
Amsterdam ; ; Boston, : Newnes, 2011
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
The definitive guide to the ARM cortex-M0 [[electronic resource] /] / Joseph Yiu
The definitive guide to the ARM cortex-M0 [[electronic resource] /] / Joseph Yiu
Autore Yiu Joseph
Edizione [1st edition]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Newnes, 2011
Descrizione fisica 1 online resource (553 p.)
Disciplina 621.39/16
621.3916
Soggetto topico Embedded computer systems
Microprocessors
ISBN 1-283-52645-X
9786613838902
0-12-385478-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; The Definitive Guide to the ARM Cortex-M0; Copyright; Contents; Foreword; Preface; Acknowledgments; Conventions; Terms and Abbreviations; Chapter 1 Introduction; Why Cortex-M0?; Application of the Cortex-M0 Processors; Background of ARM and ARM processors; Cortex-M0 Processor Specification and ARM Architecture; ARM Processors and the ARM Ecosystem; Getting Started with the Cortex-M0 Processor; Organization of This Book and Resources; Chapter 2 Cortex-M0 Technical Overview; General Information on the Cortex-M0 Processor; The ARM Cortex-M0 Processor Features
Advantages of the Cortex-M0 ProcessorLow-Power Applications; Cortex-M0 Software Portability; Chapter 3 Architecture; Overview; Programmer's Model; Memory System Overview; Stack Memory Operations; Exceptions and Interrupts; Nested Vectored Interrupt Controller (NVIC); System Control Block (SCB); Program Image and Startup Sequence; Chapter 4 Introduction to Cortex-M0 Programming; Introduction to Embedded System Programming; Inputs and Outputs; Development Flow; C Programming and Assembly Programming; What Is in a Program Image?; C Programming: Data Types; Accessing Peripherals in C
Cortex Microcontroller Software Interface Standard (CMSIS)Benefits of CMSIS; Chapter 5 Instruction Set; Background of ARM and Thumb Instruction Set; Assembly Basics; Pseudo Instructions; Chapter 6 Instruction Usage Examples; Overview; Program Control; Data Accesses; Data Type Conversion; Data Processing; Chapter 7 Memory System; Overview; Memory Map; Program Memory, Boot Loader, and Memory Remapping; Data Memory; Little Endian and Big Endian Support; Memory Attributes; Chapter 8 Exceptions and Interrupts; What Are Exceptions and Interrupts?; Exception Types on the Cortex-M0 Processor
Exception Priority DefinitionVector Table; Exception Sequence Overview; EXC_RETURN; Details of Exception Entry Sequence; Details of Exception Exit Sequence; Chapter 9 Interrupt Control and System Control; Overview of the NVIC and System Control Block Features; Interrupt Enable and Clear Enable; Interrupt Pending and Clear Pending; Interrupt Priority Level; Generic Assembly Code for Interrupt Control; Exception Masking Register (PRIMASK); Interrupt Inputs and Pending Behavior; Interrupt Latency; Control Registers for System Exceptions; System Control Registers
Chapter 10 Operating System Support FeaturesOverview of the OS Support Features; The SysTick Timer; SysTick Registers; Process Stack and Process Stack Pointer; SVC; PendSV; Chapter 11 Low-Power Features; Low-Power Embedded System Overview; Low-Power Advantages of the Cortex-M0 Processor; Overview of the Low-Power Features; Sleep Modes; Wait-for-Event (WFE) and Wait-for-Interrupt (WFI); Sleep-on-Exit Feature; Wakeup Interrupt Controller; Chapter 12 Fault Handling; Fault Exception Overview; Analyze a Fault; Accidental Switching to ARM State; Error Handling in Real Applications; Lockup
Preventing Lockup
Record Nr. UNINA-9910791978103321
Yiu Joseph  
Amsterdam ; ; Boston, : Newnes, 2011
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
The definitive guide to the ARM cortex-M0 / / Joseph Yiu
The definitive guide to the ARM cortex-M0 / / Joseph Yiu
Autore Yiu Joseph
Edizione [1st edition]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Newnes, 2011
Descrizione fisica 1 online resource (553 p.)
Disciplina 621.39/16
621.3916
Soggetto topico Embedded computer systems
Microprocessors
ISBN 1-283-52645-X
9786613838902
0-12-385478-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; The Definitive Guide to the ARM Cortex-M0; Copyright; Contents; Foreword; Preface; Acknowledgments; Conventions; Terms and Abbreviations; Chapter 1 Introduction; Why Cortex-M0?; Application of the Cortex-M0 Processors; Background of ARM and ARM processors; Cortex-M0 Processor Specification and ARM Architecture; ARM Processors and the ARM Ecosystem; Getting Started with the Cortex-M0 Processor; Organization of This Book and Resources; Chapter 2 Cortex-M0 Technical Overview; General Information on the Cortex-M0 Processor; The ARM Cortex-M0 Processor Features
Advantages of the Cortex-M0 ProcessorLow-Power Applications; Cortex-M0 Software Portability; Chapter 3 Architecture; Overview; Programmer's Model; Memory System Overview; Stack Memory Operations; Exceptions and Interrupts; Nested Vectored Interrupt Controller (NVIC); System Control Block (SCB); Program Image and Startup Sequence; Chapter 4 Introduction to Cortex-M0 Programming; Introduction to Embedded System Programming; Inputs and Outputs; Development Flow; C Programming and Assembly Programming; What Is in a Program Image?; C Programming: Data Types; Accessing Peripherals in C
Cortex Microcontroller Software Interface Standard (CMSIS)Benefits of CMSIS; Chapter 5 Instruction Set; Background of ARM and Thumb Instruction Set; Assembly Basics; Pseudo Instructions; Chapter 6 Instruction Usage Examples; Overview; Program Control; Data Accesses; Data Type Conversion; Data Processing; Chapter 7 Memory System; Overview; Memory Map; Program Memory, Boot Loader, and Memory Remapping; Data Memory; Little Endian and Big Endian Support; Memory Attributes; Chapter 8 Exceptions and Interrupts; What Are Exceptions and Interrupts?; Exception Types on the Cortex-M0 Processor
Exception Priority DefinitionVector Table; Exception Sequence Overview; EXC_RETURN; Details of Exception Entry Sequence; Details of Exception Exit Sequence; Chapter 9 Interrupt Control and System Control; Overview of the NVIC and System Control Block Features; Interrupt Enable and Clear Enable; Interrupt Pending and Clear Pending; Interrupt Priority Level; Generic Assembly Code for Interrupt Control; Exception Masking Register (PRIMASK); Interrupt Inputs and Pending Behavior; Interrupt Latency; Control Registers for System Exceptions; System Control Registers
Chapter 10 Operating System Support FeaturesOverview of the OS Support Features; The SysTick Timer; SysTick Registers; Process Stack and Process Stack Pointer; SVC; PendSV; Chapter 11 Low-Power Features; Low-Power Embedded System Overview; Low-Power Advantages of the Cortex-M0 Processor; Overview of the Low-Power Features; Sleep Modes; Wait-for-Event (WFE) and Wait-for-Interrupt (WFI); Sleep-on-Exit Feature; Wakeup Interrupt Controller; Chapter 12 Fault Handling; Fault Exception Overview; Analyze a Fault; Accidental Switching to ARM State; Error Handling in Real Applications; Lockup
Preventing Lockup
Record Nr. UNINA-9910810307403321
Yiu Joseph  
Amsterdam ; ; Boston, : Newnes, 2011
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
The definitive guide to the ARM Cortex-M3 [[electronic resource] /] / Joseph Yiu
The definitive guide to the ARM Cortex-M3 [[electronic resource] /] / Joseph Yiu
Autore Yiu Joseph
Edizione [2nd ed.]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Newnes, c2010
Descrizione fisica 1 online resource (481 p.)
Disciplina 621.39/16
Soggetto topico Embedded computer systems
Microprocessors
Soggetto genere / forma Electronic books.
ISBN 1-282-75584-6
9786612755842
1-85617-964-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; Half Title Page; The Definitive Guide to the ARM Cortex-M3; Copyright Page; Table of Contents; Foreword; Foreword; Preface; Acknowledgments; Conventions; Terms and Abbreviations; Chapter 1. Introduction; 1.1 What Is the ARM Cortex-M3 Processor?; 1.2 Background of ARM and ARM Architecture; 1.2.1 A Brief History; 1.2.2 Architecture Versions; 1.2.3 Processor Naming; 1.3 Instruction Set Development; 1.4 The Thumb-2 Technology and Instruction Set Architecture; 1.5 Cortex-M3 Processor Applications; 1.6 Organization of This Book; 1.7 Further Reading; Chapter 2. Overview of the Cortex-M3
2.1 Fundamentals2.2 Registers; 2.2.1 R0-R12: General-Purpose Registers; 2.2.2 R13: Stack Pointers; 2.2.3 R14: The Link Register; 2.2.4 R15: The Program Counter; 2.2.5 Special Registers; 2.3 Operation Modes; 2.4 The Built-In Nested Vectored Interrupt Controller; 2.4.1 Nested Interrupt Support; 2.4.2 Vectored Interrupt Support; 2.4.3 Dynamic Priority Changes Support; 2.4.4 Reduction of Interrupt Latency; 2.4.5 Interrupt Masking; 2.5 The Memory Map; 2.6 The Bus Interface; 2.7 The MPU; 2.8 The Instruction Set; 2.9 Interrupts and Exceptions; 2.9.1 Low Power and High Energy Efficiency
2.10 Debugging Support2.11 Characteristics Summary; 2.11.1 High Performance; 2.11.2 Advanced Interrupt-Handling Features; 2.11.3 Low Power Consumption; 2.11.4 System Features; 2.11.5 Debug Supports; Chapter 3. Cortex-M3 Basics; 3.1 Registers; 3.1.1 General Purpose Registers R0 through R7; 3.1.2 General Purpose Registers R8 through R12; 3.1.3 Stack Pointer R13; 3.1.4 Link Register R14; 3.1.5 Program Counter R15; 3.2 Special Registers; 3.2.1 Program Status Registers; 3.2.2 PRIMASK, FAULTMASK, and BASEPRI Registers; 3.2.3 The Control Register; 3.3 Operation Mode; 3.4 Exceptions and Interrupts
3.5 Vector Tables3.6 Stack Memory Operations; 3.6.1 Basic Operations of the Stack; 3.6.2 Cortex-M3 Stack Implementation; 3.6.3 The Two-Stack Model in the Cortex-M3; 3.7 Reset Sequence; Chapter 4. Instruction Sets; 4.1 Assembly Basics; 4.1.1 Assembler Language: Basic Syntax; 4.1.2 Assembler Language: Use of Suffixes; 4.1.3 Assembler Language: Unified Assembler Language; 4.2 Instruction List; 4.2.1 Unsupported Instructions; 4.3 Instruction Descriptions; 4.3.1 Assembler Language: Moving Data; 4.3.2 LDR and ADR Pseudo-Instructions; 4.3.3 Assembler Language: Processing Data
4.3.4 Assembler Language: Call and Unconditional Branch4.3.5 Assembler Language: Decisions and Conditional Branches; 4.3.6 Assembler Language: Combined Compare and Conditional Branch; 4.3.7 Assembler Language: Instruction Barrier and Memory Barrier Instructions; 4.3.8 Assembly Language: Saturation Operations; 4.4 Several Useful Instructions in the Cortex-M3; 4.4.1 MSR and MRS; 4.4.2 More on the IF-THEN Instruction Block; 4.4.3 SDIV and UDIV; 4.4.4 REV, REVH, and REVSH; 4.4.5 Reverse Bit; 4.4.6 SXTB, SXTH, UXTB, and UXTH; 4.4.7 Bit Field Clear and Bit Field Insert; 4.4.8 UBFX and SBFX
4.4.9 LDRD and STRD
Record Nr. UNINA-9910456662303321
Yiu Joseph  
Amsterdam ; ; Boston, : Newnes, c2010
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
The definitive guide to the ARM Cortex-M3 [[electronic resource] /] / Joseph Yiu
The definitive guide to the ARM Cortex-M3 [[electronic resource] /] / Joseph Yiu
Autore Yiu Joseph
Edizione [2nd ed.]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Newnes, c2010
Descrizione fisica 1 online resource (481 p.)
Disciplina 621.39/16
Soggetto topico Embedded computer systems
Microprocessors
ISBN 1-282-75584-6
9786612755842
1-85617-964-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; Half Title Page; The Definitive Guide to the ARM Cortex-M3; Copyright Page; Table of Contents; Foreword; Foreword; Preface; Acknowledgments; Conventions; Terms and Abbreviations; Chapter 1. Introduction; 1.1 What Is the ARM Cortex-M3 Processor?; 1.2 Background of ARM and ARM Architecture; 1.2.1 A Brief History; 1.2.2 Architecture Versions; 1.2.3 Processor Naming; 1.3 Instruction Set Development; 1.4 The Thumb-2 Technology and Instruction Set Architecture; 1.5 Cortex-M3 Processor Applications; 1.6 Organization of This Book; 1.7 Further Reading; Chapter 2. Overview of the Cortex-M3
2.1 Fundamentals2.2 Registers; 2.2.1 R0-R12: General-Purpose Registers; 2.2.2 R13: Stack Pointers; 2.2.3 R14: The Link Register; 2.2.4 R15: The Program Counter; 2.2.5 Special Registers; 2.3 Operation Modes; 2.4 The Built-In Nested Vectored Interrupt Controller; 2.4.1 Nested Interrupt Support; 2.4.2 Vectored Interrupt Support; 2.4.3 Dynamic Priority Changes Support; 2.4.4 Reduction of Interrupt Latency; 2.4.5 Interrupt Masking; 2.5 The Memory Map; 2.6 The Bus Interface; 2.7 The MPU; 2.8 The Instruction Set; 2.9 Interrupts and Exceptions; 2.9.1 Low Power and High Energy Efficiency
2.10 Debugging Support2.11 Characteristics Summary; 2.11.1 High Performance; 2.11.2 Advanced Interrupt-Handling Features; 2.11.3 Low Power Consumption; 2.11.4 System Features; 2.11.5 Debug Supports; Chapter 3. Cortex-M3 Basics; 3.1 Registers; 3.1.1 General Purpose Registers R0 through R7; 3.1.2 General Purpose Registers R8 through R12; 3.1.3 Stack Pointer R13; 3.1.4 Link Register R14; 3.1.5 Program Counter R15; 3.2 Special Registers; 3.2.1 Program Status Registers; 3.2.2 PRIMASK, FAULTMASK, and BASEPRI Registers; 3.2.3 The Control Register; 3.3 Operation Mode; 3.4 Exceptions and Interrupts
3.5 Vector Tables3.6 Stack Memory Operations; 3.6.1 Basic Operations of the Stack; 3.6.2 Cortex-M3 Stack Implementation; 3.6.3 The Two-Stack Model in the Cortex-M3; 3.7 Reset Sequence; Chapter 4. Instruction Sets; 4.1 Assembly Basics; 4.1.1 Assembler Language: Basic Syntax; 4.1.2 Assembler Language: Use of Suffixes; 4.1.3 Assembler Language: Unified Assembler Language; 4.2 Instruction List; 4.2.1 Unsupported Instructions; 4.3 Instruction Descriptions; 4.3.1 Assembler Language: Moving Data; 4.3.2 LDR and ADR Pseudo-Instructions; 4.3.3 Assembler Language: Processing Data
4.3.4 Assembler Language: Call and Unconditional Branch4.3.5 Assembler Language: Decisions and Conditional Branches; 4.3.6 Assembler Language: Combined Compare and Conditional Branch; 4.3.7 Assembler Language: Instruction Barrier and Memory Barrier Instructions; 4.3.8 Assembly Language: Saturation Operations; 4.4 Several Useful Instructions in the Cortex-M3; 4.4.1 MSR and MRS; 4.4.2 More on the IF-THEN Instruction Block; 4.4.3 SDIV and UDIV; 4.4.4 REV, REVH, and REVSH; 4.4.5 Reverse Bit; 4.4.6 SXTB, SXTH, UXTB, and UXTH; 4.4.7 Bit Field Clear and Bit Field Insert; 4.4.8 UBFX and SBFX
4.4.9 LDRD and STRD
Record Nr. UNINA-9910780944203321
Yiu Joseph  
Amsterdam ; ; Boston, : Newnes, c2010
Materiale a stampa
Lo trovi qui: Univ. Federico II
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The definitive guide to the ARM Cortex-M3 / / Joseph Yiu
The definitive guide to the ARM Cortex-M3 / / Joseph Yiu
Autore Yiu Joseph
Edizione [2nd ed.]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Newnes, c2010
Descrizione fisica 1 online resource (481 p.)
Disciplina 621.39/16
Soggetto topico Embedded computer systems
Microprocessors
ISBN 1-282-75584-6
9786612755842
1-85617-964-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; Half Title Page; The Definitive Guide to the ARM Cortex-M3; Copyright Page; Table of Contents; Foreword; Foreword; Preface; Acknowledgments; Conventions; Terms and Abbreviations; Chapter 1. Introduction; 1.1 What Is the ARM Cortex-M3 Processor?; 1.2 Background of ARM and ARM Architecture; 1.2.1 A Brief History; 1.2.2 Architecture Versions; 1.2.3 Processor Naming; 1.3 Instruction Set Development; 1.4 The Thumb-2 Technology and Instruction Set Architecture; 1.5 Cortex-M3 Processor Applications; 1.6 Organization of This Book; 1.7 Further Reading; Chapter 2. Overview of the Cortex-M3
2.1 Fundamentals2.2 Registers; 2.2.1 R0-R12: General-Purpose Registers; 2.2.2 R13: Stack Pointers; 2.2.3 R14: The Link Register; 2.2.4 R15: The Program Counter; 2.2.5 Special Registers; 2.3 Operation Modes; 2.4 The Built-In Nested Vectored Interrupt Controller; 2.4.1 Nested Interrupt Support; 2.4.2 Vectored Interrupt Support; 2.4.3 Dynamic Priority Changes Support; 2.4.4 Reduction of Interrupt Latency; 2.4.5 Interrupt Masking; 2.5 The Memory Map; 2.6 The Bus Interface; 2.7 The MPU; 2.8 The Instruction Set; 2.9 Interrupts and Exceptions; 2.9.1 Low Power and High Energy Efficiency
2.10 Debugging Support2.11 Characteristics Summary; 2.11.1 High Performance; 2.11.2 Advanced Interrupt-Handling Features; 2.11.3 Low Power Consumption; 2.11.4 System Features; 2.11.5 Debug Supports; Chapter 3. Cortex-M3 Basics; 3.1 Registers; 3.1.1 General Purpose Registers R0 through R7; 3.1.2 General Purpose Registers R8 through R12; 3.1.3 Stack Pointer R13; 3.1.4 Link Register R14; 3.1.5 Program Counter R15; 3.2 Special Registers; 3.2.1 Program Status Registers; 3.2.2 PRIMASK, FAULTMASK, and BASEPRI Registers; 3.2.3 The Control Register; 3.3 Operation Mode; 3.4 Exceptions and Interrupts
3.5 Vector Tables3.6 Stack Memory Operations; 3.6.1 Basic Operations of the Stack; 3.6.2 Cortex-M3 Stack Implementation; 3.6.3 The Two-Stack Model in the Cortex-M3; 3.7 Reset Sequence; Chapter 4. Instruction Sets; 4.1 Assembly Basics; 4.1.1 Assembler Language: Basic Syntax; 4.1.2 Assembler Language: Use of Suffixes; 4.1.3 Assembler Language: Unified Assembler Language; 4.2 Instruction List; 4.2.1 Unsupported Instructions; 4.3 Instruction Descriptions; 4.3.1 Assembler Language: Moving Data; 4.3.2 LDR and ADR Pseudo-Instructions; 4.3.3 Assembler Language: Processing Data
4.3.4 Assembler Language: Call and Unconditional Branch4.3.5 Assembler Language: Decisions and Conditional Branches; 4.3.6 Assembler Language: Combined Compare and Conditional Branch; 4.3.7 Assembler Language: Instruction Barrier and Memory Barrier Instructions; 4.3.8 Assembly Language: Saturation Operations; 4.4 Several Useful Instructions in the Cortex-M3; 4.4.1 MSR and MRS; 4.4.2 More on the IF-THEN Instruction Block; 4.4.3 SDIV and UDIV; 4.4.4 REV, REVH, and REVSH; 4.4.5 Reverse Bit; 4.4.6 SXTB, SXTH, UXTB, and UXTH; 4.4.7 Bit Field Clear and Bit Field Insert; 4.4.8 UBFX and SBFX
4.4.9 LDRD and STRD
Record Nr. UNINA-9910824992003321
Yiu Joseph  
Amsterdam ; ; Boston, : Newnes, c2010
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
The definitive guide to the ARM Cortex-M3 [[electronic resource] /] / Joseph Yiu
The definitive guide to the ARM Cortex-M3 [[electronic resource] /] / Joseph Yiu
Autore Yiu Joseph
Edizione [1st edition]
Pubbl/distr/stampa Amsterdam ; ; Boston, : Newnes, c2007
Descrizione fisica 1 online resource (380 p.)
Disciplina 004.16
004.256
Collana Embedded technology series
Soggetto topico Embedded computer systems
Microprocessors
Soggetto genere / forma Electronic books.
ISBN 1-281-03935-7
9786611039356
0-08-055143-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Front Cover; The Definitive Guide to the ARM Cortex-M3; Copyright Page; Table of Contents; Foreword; Preface; Acknowledgments; Terms and Abbreviations; Conventions; References; Chapter 1 - Introduction; What Is the ARM Cortex-M3 Processor?; Background of ARM and ARM Architecture; A Brief History; Architecture Versions; Processor Naming; Instruction Set Development; The Thumb-2 Instruction Set Architecture (ISA); Cortex-M3 Processor Applications; Organization of This Book; Further Readings; Chapter 2 - Overview of the Cortex-M3; Fundamentals; Registers; R0 to R12: General-Purpose Registers
R13: Stack PointersR14: The Link Register; R15: The Program Counter; Special Registers; Operation Modes; The Built-In Nested Vectored Interrupt Controller; Nested Interrupt Support; Vectored Interrupt Support; Dynamic Priority Changes Support; Reduction of Interrupt Latency; Interrupt Masking; The Memory Map; The Bus Interface; The Memory Protection Unit; The Instruction Set; Interrupts and Exceptions; Debugging Support; Characteristics Summary; High Performance; Advanced Interrupt-Handling Features; Low Power Consumption; System Features; Debug Supports; Chapter 3 - Cortex-M3 Basics
RegistersGeneral-Purpose Registers R0-R7; General-Purpose Registers R8-R12; Stack Pointer R13; Link Register R14; Program Counter R15; Special Registers; Program Status Registers (PSRs); PRIMASK, FAULTMASK, and BASEPRI Registers; The Control Register; Operation Mode; Exceptions and Interrupts; Vector Tables; Stack Memory Operations; Basic Operations of the Stack; Cortex-M3 Stack Implementation; The Two-Stack Model in the Cortex-M3; Reset Sequence; Chapter 4 - Instruction Sets; Assembly Basics; Assembler Language: Basic Syntax; Assembler Language: Use of Suffixes
Assembler Language: Unified Assembler LanguageInstruction List; Unsupported Instructions; Instruction Descriptions; Assembler Language: Moving Data; LDR and ADR Pseudo Instructions; Assembler Language: Processing Data; Assembler Language: Call and Unconditional Branch; Assembler Language: Decisions and Conditional Branches; Assembler Language: Combined Compare and Conditional Branch; Assembler Language: Conditional Branches Using IT Instructions; Assembler Language: Instruction Barrier and Memory Barrier Instructions; Assembly Language: Saturation Operations
Several Useful Instructions in the Cortex-M3MSR and MRS; IF-THEN; CBZ and CBNZ; SDIV and UDIV; REV, REVH, and REVSH; RBIT; SXTB, SXTH, UXTB, and UXTH; BFC and BFI; UBFX and SBFX; LDRD and STRD; TBB and TBH; Chapter 5 - Memory Systems; Memory System Features Overview; Memory Maps; Memory Access Attributes; Default Memory Access Permissions; Bit-Band Operations; Advantages of Bit-Band Operations; Bit-Band Operation of Different Data Sizes; Bit-Band Operations in C Programs; Unaligned Transfers; Exclusive Accesses; Endian Mode; Chapter 6 - Cortex-M3 Implementation Overview; The Pipeline
A Detailed Block Diagram
Record Nr. UNINA-9910457699403321
Yiu Joseph  
Amsterdam ; ; Boston, : Newnes, c2007
Materiale a stampa
Lo trovi qui: Univ. Federico II
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